1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#define DPTF_CPU_PASSIVE 95 4#define DPTF_CPU_CRITICAL 105 5#define DPTF_CPU_ACTIVE_AC0 87 6#define DPTF_CPU_ACTIVE_AC1 85 7#define DPTF_CPU_ACTIVE_AC2 83 8#define DPTF_CPU_ACTIVE_AC3 80 9#define DPTF_CPU_ACTIVE_AC4 75 10 11#define DPTF_TSR0_SENSOR_ID 0 12#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" 13#define DPTF_TSR0_PASSIVE 65 14#define DPTF_TSR0_CRITICAL 75 15#define DPTF_TSR0_ACTIVE_AC0 61 16#define DPTF_TSR0_ACTIVE_AC1 59 17#define DPTF_TSR0_ACTIVE_AC2 57 18#define DPTF_TSR0_ACTIVE_AC3 55 19#define DPTF_TSR0_ACTIVE_AC4 51 20#define DPTF_TSR0_ACTIVE_AC5 48 21#define DPTF_TSR0_ACTIVE_AC6 40 22 23#define DPTF_TSR1_SENSOR_ID 1 24#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" 25#define DPTF_TSR1_PASSIVE 38 26#define DPTF_TSR1_CRITICAL 75 27#define DPTF_TSR1_ACTIVE_AC0 42 28#define DPTF_TSR1_ACTIVE_AC1 40 29#define DPTF_TSR1_ACTIVE_AC2 38 30 31#define DPTF_TSR2_SENSOR_ID 2 32#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU" 33#define DPTF_TSR2_PASSIVE 62 34#define DPTF_TSR2_CRITICAL 105 35#define DPTF_TSR2_ACTIVE_AC0 62 36#define DPTF_TSR2_ACTIVE_AC1 60 37#define DPTF_TSR2_ACTIVE_AC2 59 38#define DPTF_TSR2_ACTIVE_AC3 54 39#define DPTF_TSR2_ACTIVE_AC4 51 40#define DPTF_TSR2_ACTIVE_AC5 48 41#define DPTF_TSR2_ACTIVE_AC6 45 42 43#define DPTF_ENABLE_CHARGER 44#define DPTF_ENABLE_FAN_CONTROL 45 46/* Charger performance states, board-specific values from charger and EC */ 47Name (CHPS, Package () { 48 Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ 49 Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ 50 Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ 51 Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ 52}) 53 54/* DFPS: Fan Performance States */ 55Name (DFPS, Package () { 56 0, // Revision 57 /* 58 * TODO : Need to update this Table after characterization. 59 * These are initial reference values. 60 */ 61 /* Control, Trip Point, Speed, NoiseLevel, Power */ 62 Package () {85, 0xFFFFFFFF, 5500, 180, 1800}, 63 Package () {79, 0xFFFFFFFF, 5400, 170, 1700}, 64 Package () {76, 0xFFFFFFFF, 5300, 165, 1650}, 65 Package () {73, 0xFFFFFFFF, 5200, 160, 1600}, 66 Package () {70, 0xFFFFFFFF, 5100, 155, 1550}, 67 Package () {68, 0xFFFFFFFF, 5000, 150, 1500}, 68 Package () {65, 0xFFFFFFFF, 4900, 145, 1450}, 69 Package () {62, 0xFFFFFFFF, 4800, 140, 1400}, 70 Package () {60, 0xFFFFFFFF, 4700, 135, 1350}, 71 Package () {58, 0xFFFFFFFF, 4600, 130, 1300}, 72 Package () {55, 0xFFFFFFFF, 4500, 120, 1200}, 73 Package () {53, 0xFFFFFFFF, 4400, 110, 1100}, 74 Package () {51, 0xFFFFFFFF, 4300, 100, 1000}, 75 Package () {49, 0xFFFFFFFF, 4200, 95, 950}, 76 Package () {47, 0xFFFFFFFF, 4100, 80, 800}, 77 Package () {46, 0xFFFFFFFF, 4000, 70, 700}, 78 Package () {45, 0xFFFFFFFF, 3900, 60, 600}, 79 Package () {43, 0xFFFFFFFF, 3800, 55, 550}, 80 Package () {42, 0xFFFFFFFF, 3700, 50, 500}, 81 Package () {40, 0xFFFFFFFF, 3600, 35, 350}, 82 Package () {38, 0xFFFFFFFF, 3500, 30, 300}, 83 Package () {36, 0xFFFFFFFF, 3400, 25, 250}, 84 Package () {33, 0xFFFFFFFF, 3300, 20, 200}, 85 Package () {32, 0xFFFFFFFF, 3200, 15, 150}, 86 Package () {31, 0xFFFFFFFF, 3100, 10, 100}, 87 Package () {30, 0xFFFFFFFF, 3000, 5, 50}, 88 Package () {0, 0xFFFFFFFF, 0, 0, 0} 89}) 90 91Name (DART, Package () { 92 /* Fan effect on CPU */ 93 0, // Revision 94 Package () { 95 /* 96 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, 97 * AC7, AC8, AC9 98 */ 99 \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0, 100 0, 0, 0 101 }, 102 Package () { 103 \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 85, 73, 62, 49, 33, 25, 14, 104 0, 0, 0 105 }, 106 Package () { 107 \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 85, 73, 62, 0, 0, 0, 0, 108 0, 0, 0 109 }, 110 Package () { 111 \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 85, 73, 65, 53, 33, 25, 14, 112 0, 0, 0 113 }, 114}) 115 116Name (DTRT, Package () { 117 /* CPU Throttle Effect on CPU */ 118 Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, 119 120 /* CPU Throttle Effect on Ambient (TSR0) */ 121 Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, 122 123 /* Charger Throttle Effect on Charger (TSR1) */ 124 Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, 125 126 /* CPU Throttle Effect on CPU (TSR2) */ 127 Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, 128}) 129 130Name (MPPC, Package () 131{ 132 0x2, /* Revision */ 133 Package () { /* Power Limit 1 */ 134 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 135 5000, /* PowerLimitMinimum */ 136 15000, /* PowerLimitMaximum */ 137 28000, /* TimeWindowMinimum */ 138 32000, /* TimeWindowMaximum */ 139 200 /* StepSize */ 140 }, 141 Package () { /* Power Limit 2 */ 142 1, /* PowerLimitIndex, 1 for Power Limit 2 */ 143 15000, /* PowerLimitMinimum */ 144 64000, /* PowerLimitMaximum */ 145 28000, /* TimeWindowMinimum */ 146 32000, /* TimeWindowMaximum */ 147 1000 /* StepSize */ 148 } 149}) 150