1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#define DPTF_CPU_PASSIVE 93 4#define DPTF_CPU_CRITICAL 99 5#define DPTF_CPU_ACTIVE_AC0 85 6#define DPTF_CPU_ACTIVE_AC1 70 7#define DPTF_CPU_ACTIVE_AC2 65 8#define DPTF_CPU_ACTIVE_AC3 60 9#define DPTF_CPU_ACTIVE_AC4 50 10#define DPTF_CPU_ACTIVE_AC5 40 11 12#define DPTF_TSR0_SENSOR_ID 0 13#define DPTF_TSR0_SENSOR_NAME "Charger" 14#define DPTF_TSR0_PASSIVE 90 15#define DPTF_TSR0_CRITICAL 99 16#define DPTF_TSR0_ACTIVE_AC0 80 17#define DPTF_TSR0_ACTIVE_AC1 70 18#define DPTF_TSR0_ACTIVE_AC2 65 19#define DPTF_TSR0_ACTIVE_AC3 60 20#define DPTF_TSR0_ACTIVE_AC4 55 21#define DPTF_TSR0_ACTIVE_AC5 50 22 23#define DPTF_TSR1_SENSOR_ID 2 24#define DPTF_TSR1_SENSOR_NAME "GPU" 25#define DPTF_TSR1_PASSIVE 93 26#define DPTF_TSR1_CRITICAL 99 27#define DPTF_TSR1_ACTIVE_AC0 85 28#define DPTF_TSR1_ACTIVE_AC1 70 29#define DPTF_TSR1_ACTIVE_AC2 65 30#define DPTF_TSR1_ACTIVE_AC3 60 31#define DPTF_TSR1_ACTIVE_AC4 50 32#define DPTF_TSR1_ACTIVE_AC5 40 33 34#define DPTF_TSR2_SENSOR_ID 4 35#define DPTF_TSR2_SENSOR_NAME "F75303_GPU" 36#define DPTF_TSR2_PASSIVE 93 37#define DPTF_TSR2_CRITICAL 99 38#define DPTF_TSR2_ACTIVE_AC0 85 39#define DPTF_TSR2_ACTIVE_AC1 70 40#define DPTF_TSR2_ACTIVE_AC2 65 41#define DPTF_TSR2_ACTIVE_AC3 60 42#define DPTF_TSR2_ACTIVE_AC4 50 43#define DPTF_TSR2_ACTIVE_AC5 40 44 45#define DPTF_TSR3_SENSOR_ID 5 46#define DPTF_TSR3_SENSOR_NAME "F75303_GPU_POWER" 47#define DPTF_TSR3_PASSIVE 90 48#define DPTF_TSR3_CRITICAL 99 49#define DPTF_TSR3_ACTIVE_AC0 80 50#define DPTF_TSR3_ACTIVE_AC1 70 51#define DPTF_TSR3_ACTIVE_AC2 65 52#define DPTF_TSR3_ACTIVE_AC3 60 53#define DPTF_TSR3_ACTIVE_AC4 55 54#define DPTF_TSR3_ACTIVE_AC5 50 55 56#define DPTF_ENABLE_CHARGER 57#define DPTF_ENABLE_FAN_CONTROL 58 59/* Charger performance states, board-specific values from charger and EC */ 60Name (CHPS, Package () { 61 Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ 62 Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ 63 Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ 64 Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ 65}) 66 67/* DFPS: Fan Performance States */ 68Name (DFPS, Package () { 69 0, // Revision 70 /* 71 * TODO : Need to update this Table after characterization. 72 * These are initial reference values. 73 */ 74 /* Control, Trip Point, Speed, NoiseLevel, Power */ 75 Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, 76 Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, 77 Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, 78 Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, 79 Package () {50, 0xFFFFFFFF, 3838, 90, 900}, 80 Package () {40, 0xFFFFFFFF, 2904, 55, 550}, 81 Package () {30, 0xFFFFFFFF, 2337, 30, 300}, 82 Package () {20, 0xFFFFFFFF, 1608, 15, 150}, 83 Package () {10, 0xFFFFFFFF, 800, 10, 100}, 84 Package () {0, 0xFFFFFFFF, 0, 0, 50} 85}) 86 87Name (DART, Package () { 88 /* Fan effect on CPU */ 89 0, // Revision 90 Package () { 91 /* 92 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, 93 * AC7, AC8, AC9 94 */ 95 \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 77, 71, 68, 65, 59, 55, 0, 96 0, 0, 0 97 }, 98 Package () { 99 \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 77, 71, 68, 65, 59, 55, 0, 100 0, 0, 0 101 }, 102 Package () { 103 \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 77, 71, 68, 65, 59, 55, 0, 104 0, 0, 0 105 }, 106 Package () { 107 \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 77, 71, 68, 65, 59, 55, 0, 108 0, 0, 0 109 }, 110 Package () { 111 \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 77, 71, 68, 65, 59, 55, 0, 112 0, 0, 0 113 } 114}) 115 116Name (DTRT, Package () { 117 /* CPU Throttle Effect on CPU */ 118 Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, 119 120 /* CPU Throttle Effect on GPU (TSR1) */ 121 Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 }, 122 123 /* CPU Throttle Effect on F75303_GPU (TSR2) */ 124 Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 }, 125 126 /* CPU Throttle Effect on F75303_GPU_POWER (TSR3) */ 127 Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 }, 128 129 /* Charger Throttle Effect on Charger (TSR0) */ 130 Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 10, 0, 0, 0, 0 } 131}) 132 133Name (MPPC, Package () 134{ 135 0x2, /* Revision */ 136 Package () { /* Power Limit 1 */ 137 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 138 15000, /* PowerLimitMinimum */ 139 25000, /* PowerLimitMaximum */ 140 28000, /* TimeWindowMinimum */ 141 32000, /* TimeWindowMaximum */ 142 500 /* StepSize */ 143 }, 144 Package () { /* Power Limit 2 */ 145 1, /* PowerLimitIndex, 1 for Power Limit 2 */ 146 25000, /* PowerLimitMinimum */ 147 44000, /* PowerLimitMaximum */ 148 28000, /* TimeWindowMinimum */ 149 32000, /* TimeWindowMaximum */ 150 500 /* StepSize */ 151 } 152}) 153