1chip soc/intel/alderlake 2 3 device domain 0 on 4 device ref pch_espi on 5 chip ec/google/chromeec 6 use conn0 as mux_conn[0] 7 use conn1 as mux_conn[1] 8 use conn2 as mux_conn[2] 9 device pnp 0c09.0 on end 10 end 11 end 12 device ref tcss_xhci on 13 chip drivers/usb/acpi 14 register "type" = "UPC_TYPE_HUB" 15 device ref tcss_root_hub on 16 chip drivers/usb/acpi 17 register "desc" = ""TypeC Port 1"" 18 device ref tcss_usb3_port1 on end 19 end 20 chip drivers/usb/acpi 21 register "desc" = ""TypeC Port 2"" 22 device ref tcss_usb3_port2 on end 23 end 24 chip drivers/usb/acpi 25 register "desc" = ""TypeC Port 3"" 26 device ref tcss_usb3_port3 on end 27 end 28 end 29 end 30 end 31 device ref pmc hidden 32 # The pmc_mux chip driver is a placeholder for the 33 # PMC.MUX device in the ACPI hierarchy. 34 chip drivers/intel/pmc_mux 35 device generic 0 on 36 chip drivers/intel/pmc_mux/conn 37 use usb2_port1 as usb2_port 38 use tcss_usb3_port1 as usb3_port 39 # SBU is fixed, HSL follows CC 40 register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" 41 device generic 0 alias conn0 on end 42 end 43 chip drivers/intel/pmc_mux/conn 44 use usb2_port2 as usb2_port 45 use tcss_usb3_port2 as usb3_port 46 # SBU is fixed, HSL follows CC 47 register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" 48 device generic 1 alias conn1 on end 49 end 50 chip drivers/intel/pmc_mux/conn 51 use usb2_port3 as usb2_port 52 use tcss_usb3_port3 as usb3_port 53 # SBU is fixed, HSL follows CC 54 register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" 55 device generic 2 alias conn2 on end 56 end 57 end 58 end 59 end 60 device ref pcie_rp6 on 61 # Enable WWAN PCIE 6 using clk 5 62 register "pch_pcie_rp[PCH_RP(6)]" = "{ 63 .clk_src = 5, 64 .clk_req = 5, 65 .flags = PCIE_RP_LTR | PCIE_RP_AER, 66 }" 67 chip soc/intel/common/block/pcie/rtd3 68 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C5)" 69 register "reset_off_delay_ms" = "20" 70 register "srcclk_pin" = "5" 71 register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" 72 register "skip_on_off_support" = "true" 73 register "use_rp_mutex" = "true" 74 device generic 0 alias rp6_rtd3 on 75 end 76 end 77 chip drivers/wwan/fm 78 register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F15)" 79 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F14)" 80 register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C5)" 81 register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" 82 register "add_acpi_dma_property" = "true" 83 use rp6_rtd3 as rtd3dev 84 device generic 0 on 85 end 86 end 87 end 88 device ref pcie_rp8 on 89 # NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7 90 register "pch_pcie_rp[PCH_RP(8)]" = "{ 91 .clk_src = 7, 92 .clk_req = 7, 93 .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, 94 .PcieRpL1Substates = L1_SS_L1_2, 95 .pcie_rp_detect_timeout_ms = 50, 96 }" 97 chip soc/intel/common/block/pcie/rtd3 98 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" 99 register "enable_delay_ms" = "100" 100 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" 101 register "reset_delay_ms" = "20" 102 register "srcclk_pin" = "7" 103 device generic 0 on 104 end 105 end 106 end 107 end 108end 109