1chip soc/intel/alderlake 2 3 device domain 0 on 4 device ref pch_espi on 5 chip ec/google/chromeec 6 use conn0 as mux_conn[0] 7 use conn1 as mux_conn[1] 8 device pnp 0c09.0 on end 9 end 10 end 11 device ref pmc hidden 12 # The pmc_mux chip driver is a placeholder for the 13 # PMC.MUX device in the ACPI hierarchy. 14 chip drivers/intel/pmc_mux 15 device generic 0 on 16 chip drivers/intel/pmc_mux/conn 17 use usb2_port1 as usb2_port 18 use tcss_usb3_port1 as usb3_port 19 # SBU is fixed, HSL follows CC 20 register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" 21 device generic 0 alias conn0 on end 22 end 23 chip drivers/intel/pmc_mux/conn 24 use usb2_port2 as usb2_port 25 use tcss_usb3_port2 as usb3_port 26 # SBU is fixed, HSL follows CC 27 register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" 28 device generic 1 alias conn1 on end 29 end 30 end 31 end 32 end 33 end 34end 35