1chip soc/intel/skylake 2 3 # Enable deep Sx states 4 register "deep_s5_enable_ac" = "0" 5 register "deep_s5_enable_dc" = "0" 6 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" 7 8 # GPE configuration 9 # Note that GPE events called out in ASL code rely on this 10 # route. i.e. If this route changes then the affected GPE 11 # offset bits also need to be changed. 12 register "gpe0_dw0" = "GPP_B" 13 register "gpe0_dw1" = "GPP_D" 14 register "gpe0_dw2" = "GPP_E" 15 16 # Enable DPTF 17 register "dptf_enable" = "1" 18 19 # FSP Configuration 20 register "IoBufferOwnership" = "0" 21 register "ScsEmmcHs400Enabled" = "1" 22 register "SkipExtGfxScan" = "1" 23 register "SaGv" = "SaGv_Enabled" 24 register "PchHdaVcType" = "Vc1" 25 26 # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch 27 # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s 28 register "PmConfigSlpS3MinAssert" = "2" 29 30 # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s 31 register "PmConfigSlpS4MinAssert" = "4" 32 33 # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s 34 register "PmConfigSlpSusMinAssert" = "3" 35 36 # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s 37 register "PmConfigSlpAMinAssert" = "3" 38 39 40 # VR Settings Configuration for 4 Domains 41 #+----------------+-------+-------+-------+-------+ 42 #| Domain/Setting | SA | IA | GTUS | GTS | 43 #+----------------+-------+-------+-------+-------+ 44 #| Psi1Threshold | 20A | 20A | 20A | 20A | 45 #| Psi2Threshold | 4A | 5A | 5A | 5A | 46 #| Psi3Threshold | 1A | 1A | 1A | 1A | 47 #| Psi3Enable | 1 | 1 | 1 | 1 | 48 #| Psi4Enable | 1 | 1 | 1 | 1 | 49 #| ImonSlope | 0 | 0 | 0 | 0 | 50 #| ImonOffset | 0 | 0 | 0 | 0 | 51 #| IccMax | 7A | 34A | 35A | 35A | 52 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 53 #+----------------+-------+-------+-------+-------+ 54 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ 55 .vr_config_enable = 1, 56 .psi1threshold = VR_CFG_AMP(20), 57 .psi2threshold = VR_CFG_AMP(4), 58 .psi3threshold = VR_CFG_AMP(1), 59 .psi3enable = 1, 60 .psi4enable = 1, 61 .imon_slope = 0, 62 .imon_offset = 0, 63 .icc_max = VR_CFG_AMP(7), 64 .voltage_limit = 1520 65 }" 66 67 register "domain_vr_config[VR_IA_CORE]" = "{ 68 .vr_config_enable = 1, 69 .psi1threshold = VR_CFG_AMP(20), 70 .psi2threshold = VR_CFG_AMP(5), 71 .psi3threshold = VR_CFG_AMP(1), 72 .psi3enable = 1, 73 .psi4enable = 1, 74 .imon_slope = 0, 75 .imon_offset = 0, 76 .icc_max = VR_CFG_AMP(34), 77 .voltage_limit = 1520 78 }" 79 80 register "domain_vr_config[VR_GT_UNSLICED]" = "{ 81 .vr_config_enable = 1, 82 .psi1threshold = VR_CFG_AMP(20), 83 .psi2threshold = VR_CFG_AMP(5), 84 .psi3threshold = VR_CFG_AMP(1), 85 .psi3enable = 1, 86 .psi4enable = 1, 87 .imon_slope = 0, 88 .imon_offset = 0, 89 .icc_max = VR_CFG_AMP(35), 90 .voltage_limit = 1520 91 }" 92 93 register "domain_vr_config[VR_GT_SLICED]" = "{ 94 .vr_config_enable = 1, 95 .psi1threshold = VR_CFG_AMP(20), 96 .psi2threshold = VR_CFG_AMP(5), 97 .psi3threshold = VR_CFG_AMP(1), 98 .psi3enable = 1, 99 .psi4enable = 1, 100 .imon_slope = 0, 101 .imon_offset = 0, 102 .icc_max = VR_CFG_AMP(35), 103 .voltage_limit = 1520 104 }" 105 106 # Send an extra VR mailbox command for the PS4 exit issue 107 register "SendVrMbxCmd" = "2" 108 109 device domain 0 on 110 device ref igpu on end 111 device ref sa_thermal on end 112 device ref south_xhci on end 113 device ref thermal on end 114 device ref i2c0 on end 115 device ref i2c1 on end 116 device ref i2c2 on end 117 device ref i2c3 on end 118 device ref heci1 on end 119 device ref uart2 on end 120 device ref i2c4 on end 121 device ref pcie_rp1 on end 122 device ref pcie_rp9 on end 123 device ref uart0 on end 124 device ref emmc on end 125 device ref sdxc on end 126 device ref smbus on end 127 device ref lpc_espi on 128 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f 129 register "gen1_dec" = "0x00fc0801" 130 end 131 device ref fast_spi on end 132 end 133end 134