1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _GPIORVP8_H 4 #define _GPIORVP8_H 5 6 #include <soc/gpe.h> 7 #include <soc/gpio.h> 8 9 /* TCA6424A I/O Expander */ 10 #define IO_EXPANDER_BUS 4 11 #define IO_EXPANDER_0_ADDR 0x22 12 #define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */ 13 #define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */ 14 #define IO_EXPANDER_P1CONF 0x0D 15 #define IO_EXPANDER_P1DOUT 0x05 16 #define IO_EXPANDER_P2CONF 0x0E 17 #define IO_EXPANDER_P2DOUT 0x06 18 #define IO_EXPANDER_1_ADDR 0x23 19 20 /* GPE_EC_WAKE */ 21 #define GPE_EC_WAKE GPE0_LAN_WAK 22 #define EC_SMI_GPI GPP_I3 23 24 /* 25 * Gpio based irq for touchpad, 18th index in North Bank 26 * MAX_DIRECT_IRQ + GPSW_SIZE + 19 27 */ 28 #define KBLRVP_TOUCHPAD_IRQ 33 29 30 #define KBLRVP_TOUCH_IRQ 31 31 32 #define BOARD_TOUCHPAD_NAME "touchpad" 33 #define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ 34 #define BOARD_TOUCHPAD_I2C_BUS 0 35 #define BOARD_TOUCHPAD_I2C_ADDR 0x20 36 37 #define BOARD_TOUCHSCREEN_NAME "touchscreen" 38 #define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ 39 #define BOARD_TOUCHSCREEN_I2C_BUS 0 40 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c 41 42 #ifndef __ACPI__ 43 44 /* Pad configuration in ramstage. */ 45 static const struct pad_config gpio_table[] = { 46 /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3), 47 /* EC_LPC_IO0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF3), 48 /* EC_LPC_IO1*/ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF3), 49 /* EC_LPC_IO2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF3), 50 /* EC_LPC_IO3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF3), 51 /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF3), 52 /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3), 53 /* PIRQAB */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), 54 /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), 55 /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), 56 /* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), 57 /* PMEB */ PAD_CFG_GPI(GPP_A11, NONE, DEEP), 58 /* SUS_PWR_ACK_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), 59 /* PM_SUS_ESPI_RST */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3), 60 /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), 61 /* BT_RF_KILL */ PAD_CFG_GPO(GPP_B3, 1, DEEP), 62 /* EXTTS_SNI_DRV1 */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), 63 /* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), 64 /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), 65 /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), 66 /* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1), 67 /* GSPI0_MISO */ PAD_CFG_GPO(GPP_B17, 1, DEEP), 68 /* PCHHOTB */ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), 69 /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), 70 /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), 71 /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), 72 /* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), 73 /* SML0_DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), 74 /* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), 75 /* SML1_DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), 76 /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), 77 /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), 78 /* UART0_RTS_N */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), 79 /* UART0_CTS_N */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), 80 /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), 81 /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), 82 /* UART2_RTS_N */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), 83 /* UART2_CTS_N */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), 84 /* SSP0_SFRM */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), 85 /* SSP0_TXD */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), 86 /* SSP0_RXD */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), 87 /* SSP0_SCLK */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), 88 /* SATAE_IFDET */ PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), 89 /* SATAE_IFDET */ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), 90 /* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), 91 /* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), 92 /* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), 93 /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), 94 /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), 95 /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), 96 /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), 97 /* SATAXPCIE_4 */ PAD_CFG_NF(GPP_F1, UP_20K, DEEP,NF1), 98 /* SATA_DEVSLP_3 */ PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, INVERT), 99 /* SATA_DEVSLP_4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), 100 /* SATA_SCLOCK */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, DEEP), 101 /* SATA_SLOAD */ PAD_CFG_GPI(GPP_F11, NONE, DEEP), 102 /* SATA_SDATAOUT1 */ PAD_CFG_GPI_APIC_HIGH(GPP_F12, NONE, DEEP), 103 /* SATA_SDATAOUT0 */ PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, DEEP), 104 /* H_SKTOCC_N */ PAD_CFG_GPI_APIC_HIGH(GPP_F14, NONE, DEEP), 105 /* USB_OC4_R_N */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), 106 /* USB_OC5_R_N */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), 107 /* USB_OC6_R_N */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), 108 /* USB_OC7_R_N */ PAD_CFG_GPO(GPP_F18, 1, DEEP), 109 /* GPIO_PEG_RESET */ PAD_CFG_GPO(GPP_F22, 1, DEEP), 110 /* VCORE_VBOOST_CTRL */ PAD_CFG_GPO(GPP_F23, 0, DEEP), 111 /* FAN_TACH_0 */ PAD_CFG_GPO(GPP_G0, 1, DEEP), 112 /* FAN_TACH_1 */ PAD_CFG_GPO(GPP_G1, 1, DEEP), 113 /* FAN_TACH_2 */ PAD_CFG_GPI_SCI(GPP_G2, NONE, DEEP, EDGE_SINGLE, INVERT), 114 /* FAN_TACH_3 */ PAD_CFG_GPI_SCI(GPP_G3, NONE, DEEP, EDGE_SINGLE, INVERT), 115 /* FAN_TACH_4 */ PAD_CFG_GPO(GPP_G4, 1, DEEP), 116 /* FAN_TACH_5 */ PAD_CFG_GPI_APIC_HIGH(GPP_G5, NONE, DEEP), 117 /* FAN_TACH_6 */ PAD_CFG_GPI_SCI(GPP_G6, NONE, DEEP, EDGE_SINGLE, INVERT), 118 /* FAN_TACH_7 */ PAD_CFG_GPO(GPP_G7, 1, DEEP), 119 /* GSXDOUT */ PAD_CFG_GPI_SCI(GPP_G12, DN_20K, DEEP, EDGE_SINGLE, INVERT), 120 /* GSXSLOAD */ PAD_CFG_GPO(GPP_G13, 1, DEEP), 121 /* GSXDIN */ PAD_CFG_GPI_SCI(GPP_G14, NONE, DEEP, EDGE_SINGLE, INVERT), 122 /* GSXSRESETB */ PAD_CFG_GPO(GPP_G15, 0, DEEP), 123 /* GSXCLK */ PAD_CFG_GPO(GPP_G16, 0, DEEP), 124 /* NMIB */ PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, DEEP), 125 /* SMIB */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), 126 /* TEST_SETUP_MENU */ PAD_CFG_GPI_APIC_HIGH(GPP_G20, NONE, DEEP), 127 /* P_INTF_N */ PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), 128 /* PCH_PEGSLOT1 */ PAD_CFG_GPO(GPP_G22, 1, DEEP), 129 /* IVCAM_DFU_R */ PAD_CFG_GPO(GPP_G23, 1, DEEP), 130 /* SRCCLKREQB_8 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), 131 /* SML2CLK */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), 132 /* SML2DATA */ PAD_CFG_GPI(GPP_H11, NONE, DEEP), 133 /* SML3CLK */ PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, DEEP), 134 /* SML3DATA */ PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, DEEP), 135 /* SML3ALERTB */ PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, DEEP), 136 /* SML4DATA */ PAD_CFG_GPO(GPP_H17, 1, DEEP), 137 /* LED_DRIVE */ PAD_CFG_GPO(GPP_H23, 0, DEEP), 138 /* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), 139 /* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), 140 /* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), 141 /* DDSP_HPD_1 */ PAD_CFG_GPI_SMI(GPP_I3, NONE, DEEP, EDGE_SINGLE, INVERT), 142 /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), 143 /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, DN_20K, DEEP, NF1), 144 /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), 145 /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, DN_20K, DEEP, NF1), 146 /* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), 147 /* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), 148 /* EC_PCH_ACPRESENT */ PAD_CFG_GPO(GPD1, 0, DEEP), 149 /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), 150 /* PM_PWRBTN_R_N */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), 151 /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), 152 /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), 153 /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), 154 /* USB_WAKEOUT_N */ PAD_CFG_NF(GPD7, NONE, DEEP, NF1), 155 /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), 156 /* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), 157 /* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), 158 /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), 159 160 }; 161 162 /* Early pad configuration in bootblock */ 163 static const struct pad_config early_gpio_table[] = { 164 /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), 165 /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), 166 /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), 167 /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), 168 }; 169 170 #endif 171 #endif 172