1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <console/console.h>
5 #include <edid.h>
6 #include <soc/clock.h>
7 #include <soc/display/mdssreg.h>
8
9 #define MDSS_MDP_MAX_PREFILL_FETCH 24
10
mdss_source_pipe_config(struct edid * edid)11 static void mdss_source_pipe_config(struct edid *edid)
12 {
13 uint32_t img_size, out_size, stride;
14 uint32_t fb_off = 0;
15 uint32_t flip_bits = 0;
16 uint32_t src_xy = 0;
17 uint32_t dst_xy = 0;
18
19 /* write active region size*/
20 img_size = (edid->mode.va << 16) | edid->mode.ha;
21 out_size = img_size;
22 stride = (edid->mode.ha * edid->framebuffer_bits_per_pixel/8);
23
24 if (!fb_off) { /* left */
25 dst_xy = (edid->mode.vborder << 16) | edid->mode.hborder;
26 src_xy = dst_xy;
27 } else { /* right */
28 dst_xy = (edid->mode.vborder << 16);
29 src_xy = (edid->mode.vborder << 16) | fb_off;
30 }
31
32 printk(BIOS_INFO, "%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n",
33 __func__, out_size, fb_off, src_xy, dst_xy);
34
35 write32(&mdp_sspp->sspp_src_ystride0, stride);
36 write32(&mdp_sspp->sspp_src_size, out_size);
37 write32(&mdp_sspp->sspp_out_size, out_size);
38 write32(&mdp_sspp->sspp_src_xy, src_xy);
39 write32(&mdp_sspp->sspp_out_xy, dst_xy);
40
41 /* Tight Packing 4bpp Alpha 8-bit A R B G */
42 write32(&mdp_sspp->sspp_src_format, 0x000236ff);
43 write32(&mdp_sspp->sspp_src_unpack_pattern, 0x03020001);
44
45 flip_bits |= SW_PIX_EXT_OVERRIDE;
46 write32(&mdp_sspp->sspp_sw_pic_ext_c0_req_pixels, out_size);
47 write32(&mdp_sspp->sspp_sw_pic_ext_c1c2_req_pixels, out_size);
48 write32(&mdp_sspp->sspp_sw_pic_ext_c3_req_pixels, out_size);
49 write32(&mdp_sspp->sspp_src_op_mode, flip_bits);
50 }
51
mdss_vbif_setup(void)52 static void mdss_vbif_setup(void)
53 {
54 write32(&vbif_rt->vbif_out_axi_amemtype_conf0, 0x33333333);
55 write32(&vbif_rt->vbif_out_axi_amemtype_conf1, 0x00333333);
56 }
57
mdss_intf_fetch_start_config(struct edid * edid)58 static void mdss_intf_fetch_start_config(struct edid *edid)
59 {
60 uint32_t v_total, h_total, fetch_start, vfp_start;
61 uint32_t prefetch_avail, prefetch_needed;
62 uint32_t fetch_enable = PROG_FETCH_START_EN;
63
64 /*
65 * MDP programmable fetch is for MDP with rev >= 1.05.
66 * Programmable fetch is not needed if vertical back porch
67 * plus vertical pulse width plus extra line for the extra h_total
68 * added during fetch start is >= 24.
69 */
70 if ((edid->mode.vbl - edid->mode.vso + 1) >= MDSS_MDP_MAX_PREFILL_FETCH)
71 return;
72
73 /*
74 * Fetch should always be outside the active lines. If the fetching
75 * is programmed within active region, hardware behavior is unknown.
76 */
77 v_total = edid->mode.va + edid->mode.vbl;
78 h_total = edid->mode.ha + edid->mode.hbl;
79 vfp_start = edid->mode.va + edid->mode.vbl - edid->mode.vso;
80 prefetch_avail = v_total - vfp_start;
81 prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - edid->mode.vbl + edid->mode.vso;
82
83 /*
84 * In some cases, vertical front porch is too high. In such cases limit
85 * the mdp fetch lines as the last (25 - vbp - vpw) lines of
86 * vertical front porch.
87 */
88 if (prefetch_avail > prefetch_needed)
89 prefetch_avail = prefetch_needed;
90
91 fetch_start = (v_total - prefetch_avail) * h_total + h_total + 1;
92 write32(&mdp_intf->intf_prof_fetch_start, fetch_start);
93 write32(&mdp_intf->intf_config, fetch_enable);
94 }
95
mdss_layer_mixer_setup(struct edid * edid)96 static void mdss_layer_mixer_setup(struct edid *edid)
97 {
98 uint32_t mdp_rgb_size;
99 uint32_t left_staging_level;
100
101 /* write active region size*/
102 mdp_rgb_size = (edid->mode.va << 16) | edid->mode.ha;
103
104 write32(&mdp_layer_mixer->layer_out_size, mdp_rgb_size);
105 write32(&mdp_layer_mixer->layer_op_mode, 0x0);
106 for (int i = 0; i < 6; i++) {
107 write32(&mdp_layer_mixer->layer_blend[i].layer_blend_op, 0x100);
108 write32(&mdp_layer_mixer->layer_blend[i].layer_blend_const_alpha, 0x00ff0000);
109 }
110
111 /* Enable border fill */
112 left_staging_level = BORDER_OUT;
113 left_staging_level |= VIG_0_OUT;
114
115 /* Base layer for layer mixer 0 */
116 write32(&mdp_ctl->ctl_layer0, left_staging_level);
117 }
118
mdss_vbif_qos_remapper_setup(void)119 static void mdss_vbif_qos_remapper_setup(void)
120 {
121 /*
122 * VBIF remapper registers are used for translating internal display hardware
123 * priority level (from 0 to 7) into system fabric priority level.
124 * These remapper settings are defined for all the clients which corresponds
125 * to the xin clients connected to SSPP on VBIF.
126 */
127 write32(&vbif_rt->qos_rp_remap[0].vbif_xinl_qos_rp_remap, 0x00000003);
128 write32(&vbif_rt->qos_rp_remap[1].vbif_xinl_qos_rp_remap, 0x11111113);
129 write32(&vbif_rt->qos_rp_remap[2].vbif_xinl_qos_rp_remap, 0x22222224);
130 write32(&vbif_rt->qos_rp_remap[3].vbif_xinl_qos_rp_remap, 0x33333334);
131 write32(&vbif_rt->qos_rp_remap[4].vbif_xinl_qos_rp_remap, 0x44444445);
132 write32(&vbif_rt->qos_rp_remap[7].vbif_xinl_qos_rp_remap, 0x77777776);
133 write32(&vbif_rt->qos_lvl_remap[0].vbif_xinl_qos_lvl_remap, 0x00000003);
134 write32(&vbif_rt->qos_lvl_remap[1].vbif_xinl_qos_lvl_remap, 0x11111113);
135 write32(&vbif_rt->qos_lvl_remap[2].vbif_xinl_qos_lvl_remap, 0x22222224);
136 write32(&vbif_rt->qos_lvl_remap[3].vbif_xinl_qos_lvl_remap, 0x33333334);
137 write32(&vbif_rt->qos_lvl_remap[4].vbif_xinl_qos_lvl_remap, 0x44444445);
138 write32(&vbif_rt->qos_lvl_remap[5].vbif_xinl_qos_lvl_remap, 0x77777776);
139 }
140
mdp_dsi_video_config(struct edid * edid)141 void mdp_dsi_video_config(struct edid *edid)
142 {
143 mdss_intf_tg_setup(edid);
144 mdss_intf_fetch_start_config(edid);
145 mdss_vbif_setup();
146 mdss_vbif_qos_remapper_setup();
147 mdss_source_pipe_config(edid);
148 mdss_layer_mixer_setup(edid);
149 mdss_ctrl_config();
150 write32(&mdp_intf->intf_mux, 0x0F0000);
151 }
152
mdp_dsi_video_on(void)153 void mdp_dsi_video_on(void)
154 {
155 uint32_t ctl0_reg_val;
156
157 ctl0_reg_val = VIG_0 | LAYER_MIXER_0 | CTL | INTF;
158 write32(&mdp_ctl->ctl_intf_flush, INTF_FLUSH);
159 write32(&mdp_ctl->ctl_flush, ctl0_reg_val);
160 }
161