xref: /aosp_15_r20/external/coreboot/src/superio/ite/it8783ef/acpi/superio.asl (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1/* SPDX-License-Identifier: GPL-2.0-only */
2
3/*
4 * Include this file into a mainboard's DSDT _SB device tree and it will
5 * expose the IT8783E/F SuperIO and some of its functionality.
6 *
7 * It allows the change of IO ports, IRQs and DMA settings on logical
8 * devices, disabling and reenabling logical devices.
9 *
10 *   LDN		State
11 * 0x0 FDC		Not implemented
12 * 0x1 UARTA		Implemented, untested
13 * 0x2 UARTB		Implemented, untested
14 * 0x3 PP		Not implemented
15 * 0x4 EC		Not implemented
16 * 0x5 KBC		Implemented, untested
17 * 0x6 MOUSE		Implemented, untested
18 * 0x7 GPIO		Not implemented
19 * 0x8 UARTC		Implemented, untested
20 * 0x9 UARTD		Implemented, untested
21 * 0xa UARTE		Not implemented
22 * 0xb UARTF		Not implemented
23 * 0xc CIR		Not implemented
24 *
25 * Controllable through preprocessor defines:
26 * SUPERIO_DEV		Device identifier for this SIO (e.g. SIO0)
27 * SUPERIO_PNP_BASE	I/O address of the first PnP configuration register
28 * IT8783EF_SHOW_UARTA	If defined, UARTA will be exposed.
29 * IT8783EF_SHOW_UARTB	If defined, UARTB will be exposed.
30 * IT8783EF_SHOW_UARTC	If defined, UARTC will be exposed.
31 * IT8783EF_SHOW_UARTD	If defined, UARTD will be exposed.
32 * IT8783EF_SHOW_KBC	If defined, the KBC will be exposed.
33 * IT8783EF_SHOW_PS2M	If defined, PS/2 mouse support will be exposed.
34 */
35
36#undef SUPERIO_CHIP_NAME
37#define SUPERIO_CHIP_NAME IT8783EF
38#include <superio/acpi/pnp.asl>
39
40#undef PNP_DEFAULT_PSC
41#define PNP_DEFAULT_PSC Return (0) /* no power management */
42
43#define CONFIGURE_CONTROL CCTL
44
45Device(SUPERIO_DEV) {
46	Name (_HID, EisaId("PNP0A05"))
47	Name (_STR, Unicode("ITE IT8783E/F Super I/O"))
48	Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
49
50	/* Mutex for accesses to the configuration ports */
51	Mutex(CRMX, 1)
52
53	/* SuperIO configuration ports */
54	OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
55	Field (CREG, ByteAcc, NoLock, Preserve)
56	{
57		PNP_ADDR_REG,	8,
58		PNP_DATA_REG,	8
59	}
60	IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
61	{
62		Offset (0x02),
63		CONFIGURE_CONTROL,	8, /* Global configure control */
64
65		Offset (0x07),
66		PNP_LOGICAL_DEVICE,	8, /* Logical device selector */
67
68		Offset (0x30),
69		PNP_DEVICE_ACTIVE,	1, /* Logical device activation */
70
71		Offset (0x60),
72		PNP_IO0_HIGH_BYTE,	8, /* First I/O port base - high byte */
73		PNP_IO0_LOW_BYTE,	8, /* First I/O port base - low byte */
74		Offset (0x62),
75		PNP_IO1_HIGH_BYTE,	8, /* Second I/O port base - high byte */
76		PNP_IO1_LOW_BYTE,	8, /* Second I/O port base - low byte */
77
78		Offset (0x70),
79		PNP_IRQ0,		8, /* First IRQ */
80	}
81
82	Method (_CRS)
83	{
84		/* Announce the used i/o ports to the OS */
85		Return (ResourceTemplate () {
86			IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
87		})
88	}
89
90	#undef PNP_ENTER_MAGIC_1ST
91	#undef PNP_ENTER_MAGIC_2ND
92	#undef PNP_ENTER_MAGIC_3RD
93	#undef PNP_ENTER_MAGIC_4TH
94	#undef PNP_EXIT_MAGIC_1ST
95	#define PNP_ENTER_MAGIC_1ST	0x87
96	#define PNP_ENTER_MAGIC_2ND	0x01
97	#define PNP_ENTER_MAGIC_3RD	0x55
98#if SUPERIO_PNP_BASE == 0x2e
99	#define PNP_ENTER_MAGIC_4TH	0x55
100#else
101	#define PNP_ENTER_MAGIC_4TH	0xaa
102#endif
103	#define PNP_EXIT_SPECIAL_REG	CONFIGURE_CONTROL
104	#define PNP_EXIT_SPECIAL_VAL	0x02
105	#include <superio/acpi/pnp_config.asl>
106
107#ifdef IT8783EF_SHOW_UARTA
108	#undef SUPERIO_UART_LDN
109	#undef SUPERIO_UART_DDN
110	#undef SUPERIO_UART_PM_REG
111	#undef SUPERIO_UART_PM_VAL
112	#undef SUPERIO_UART_PM_LDN
113	#define SUPERIO_UART_LDN 1
114	#include <superio/acpi/pnp_uart.asl>
115#endif
116
117#ifdef IT8783EF_SHOW_UARTB
118	#undef SUPERIO_UART_LDN
119	#undef SUPERIO_UART_DDN
120	#undef SUPERIO_UART_PM_REG
121	#undef SUPERIO_UART_PM_VAL
122	#undef SUPERIO_UART_PM_LDN
123	#define SUPERIO_UART_LDN 2
124	#include <superio/acpi/pnp_uart.asl>
125#endif
126
127#ifdef IT8783EF_SHOW_KBC
128	#undef SUPERIO_KBC_LDN
129	#undef SUPERIO_KBC_PS2M
130	#undef SUPERIO_KBC_PS2LDN
131	#define SUPERIO_KBC_LDN 5
132#ifdef IT8783EF_SHOW_PS2M
133	#define SUPERIO_KBC_PS2LDN 6
134#endif
135	#include <superio/acpi/pnp_kbc.asl>
136#endif
137
138#ifdef IT8783EF_SHOW_UARTC
139	#undef SUPERIO_UART_LDN
140	#undef SUPERIO_UART_DDN
141	#undef SUPERIO_UART_PM_REG
142	#undef SUPERIO_UART_PM_VAL
143	#undef SUPERIO_UART_PM_LDN
144	#define SUPERIO_UART_LDN 8
145	#include <superio/acpi/pnp_uart.asl>
146#endif
147
148#ifdef IT8783EF_SHOW_UARTD
149	#undef SUPERIO_UART_LDN
150	#undef SUPERIO_UART_DDN
151	#undef SUPERIO_UART_PM_REG
152	#undef SUPERIO_UART_PM_VAL
153	#undef SUPERIO_UART_PM_LDN
154	#define SUPERIO_UART_LDN 9
155	#include <superio/acpi/pnp_uart.asl>
156#endif
157}
158