1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3/* 4 * Include this file into a mainboard's DSDT _SB device tree and it will 5 * expose the NCT6776 SuperIO and some of its functionality. 6 * 7 * It allows the change of IO ports, IRQs and DMA settings on logical 8 * devices, disabling and reenabling logical devices. 9 * 10 * LDN State 11 * 0x1 PP Implemented, untested 12 * 0x2 SP1 Implemented, untested 13 * 0x5 KBC Implemented, untested 14 * 0x8 GPIO Implemented, untested 15 * 0xb HWM Implemented, untested 16 * 17 * Controllable through preprocessor defines: 18 * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) 19 * SUPERIO_PNP_BASE I/O address of the first PnP configuration register 20 * NCT6776_SHOW_PP If defined, the parallel port will be exposed. 21 * NCT6776_SHOW_SP1 If defined, Serial Port 1 will be exposed. 22 * NCT6776_SHOW_KBC If defined, the Keyboard Controller will be exposed. 23 * NCT6776_SHOW_GPIO If defined, GPIO support will be exposed. 24 * NCT6776_SHOW_HWM If defined, the Environment Controller will be exposed. 25 */ 26 27#undef SUPERIO_CHIP_NAME 28#define SUPERIO_CHIP_NAME NCT6776 29#include <superio/acpi/pnp.asl> 30 31#undef PNP_DEFAULT_PSC 32#define PNP_DEFAULT_PSC Return (0) /* no power management */ 33 34Device(SUPERIO_DEV) { 35 Name (_HID, EisaId("PNP0A05")) 36 Name (_STR, Unicode("Nuvoton NCT6776 Super I/O")) 37 Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) 38 39 /* SuperIO configuration ports */ 40 OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) 41 Field (CREG, ByteAcc, NoLock, Preserve) 42 { 43 PNP_ADDR_REG, 8, 44 PNP_DATA_REG, 8, 45 } 46 IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) 47 { 48 Offset (0x07), 49 PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ 50 51 Offset (0x30), 52 PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ 53 ACT1, 1, /* Logical device activation */ 54 ACT2, 1, /* Logical device activation */ 55 ACT3, 1, /* Logical device activation */ 56 ACT4, 1, /* Logical device activation */ 57 ACT5, 1, /* Logical device activation */ 58 ACT6, 1, /* Logical device activation */ 59 ACT7, 1, /* Logical device activation */ 60 61 Offset (0x60), 62 PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ 63 PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ 64 Offset (0x62), 65 PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ 66 PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ 67 Offset (0x64), 68 PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ 69 PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ 70 71 Offset (0x70), 72 PNP_IRQ0, 8, /* First IRQ */ 73 Offset (0x72), 74 PNP_IRQ1, 8, /* Second IRQ */ 75 Offset (0x74), 76 PNP_DMA0, 8, /* DRQ */ 77 } 78 79 Method (_CRS) 80 { 81 /* Announce the used I/O ports to the OS */ 82 Return (ResourceTemplate () { 83 IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) 84 }) 85 } 86 87 #undef PNP_ENTER_MAGIC_1ST 88 #undef PNP_ENTER_MAGIC_2ND 89 #undef PNP_ENTER_MAGIC_3RD 90 #undef PNP_ENTER_MAGIC_4TH 91 #undef PNP_EXIT_MAGIC_1ST 92 #undef PNP_EXIT_SPECIAL_REG 93 #undef PNP_EXIT_SPECIAL_VAL 94 #define PNP_ENTER_MAGIC_1ST 0x87 95 #define PNP_ENTER_MAGIC_2ND 0x87 96 #define PNP_EXIT_MAGIC_1ST 0xaa 97 #include <superio/acpi/pnp_config.asl> 98 99#ifdef NCT6776_SHOW_PP 100 #undef SUPERIO_PNP_HID 101 #undef SUPERIO_PNP_LDN 102 #undef SUPERIO_PNP_DDN 103 #undef SUPERIO_PNP_NO_DIS 104 #undef SUPERIO_PNP_PM_REG 105 #undef SUPERIO_PNP_PM_VAL 106 #undef SUPERIO_PNP_PM_LDN 107 #undef SUPERIO_PNP_IO0 108 #undef SUPERIO_PNP_IO1 109 #undef SUPERIO_PNP_IO2 110 #undef SUPERIO_PNP_IRQ0 111 #undef SUPERIO_PNP_IRQ1 112 #undef SUPERIO_PNP_DMA 113 /* 114 * The extra code required to dynamically reflect ECP in the HID 115 * isn't currently justified, so the HID is hardcoded as not 116 * using ECP. "PNP0401" would indicate ECP. 117 */ 118 #define SUPERIO_PNP_HID "PNP0400" 119 #define SUPERIO_PNP_LDN 1 120 #define SUPERIO_PNP_IO0 0x08, 0x08 121 #define SUPERIO_PNP_IRQ0 122 #define SUPERIO_PNP_DMA 123 #include <superio/acpi/pnp_generic.asl> 124#endif 125 126#ifdef NCT6776_SHOW_SP1 127 #undef SUPERIO_UART_LDN 128 #undef SUPERIO_UART_DDN 129 #undef SUPERIO_UART_PM_REG 130 #undef SUPERIO_UART_PM_VAL 131 #undef SUPERIO_UART_PM_LDN 132 #define SUPERIO_UART_LDN 2 133 #include <superio/acpi/pnp_uart.asl> 134#endif 135 136#ifdef NCT6776_SHOW_KBC 137 #undef SUPERIO_KBC_LDN 138 #undef SUPERIO_KBC_PS2M 139 #undef SUPERIO_KBC_PS2LDN 140 #define SUPERIO_KBC_LDN 5 141 #define SUPERIO_KBC_PS2M 142 #include <superio/acpi/pnp_kbc.asl> 143#endif 144 145#ifdef NCT6776_SHOW_HWM 146 #undef SUPERIO_PNP_HID 147 #undef SUPERIO_PNP_LDN 148 #undef SUPERIO_PNP_DDN 149 #undef SUPERIO_PNP_NO_DIS 150 #undef SUPERIO_PNP_PM_REG 151 #undef SUPERIO_PNP_PM_VAL 152 #undef SUPERIO_PNP_PM_LDN 153 #undef SUPERIO_PNP_IO0 154 #undef SUPERIO_PNP_IO1 155 #undef SUPERIO_PNP_IO2 156 #undef SUPERIO_PNP_IRQ0 157 #undef SUPERIO_PNP_IRQ1 158 #undef SUPERIO_PNP_DMA 159 #define SUPERIO_PNP_LDN 11 160 #define SUPERIO_PNP_IO0 0x08, 0x08 161 #define SUPERIO_PNP_IO1 0x08, 0x08 162 #define SUPERIO_PNP_IRQ0 163 #include <superio/acpi/pnp_generic.asl> 164#endif 165 166#ifdef NCT6776_SHOW_GPIO 167 #undef SUPERIO_PNP_HID 168 #undef SUPERIO_PNP_LDN 169 #undef SUPERIO_PNP_DDN 170 #undef SUPERIO_PNP_NO_DIS 171 #undef SUPERIO_PNP_PM_REG 172 #undef SUPERIO_PNP_PM_VAL 173 #undef SUPERIO_PNP_PM_LDN 174 #undef SUPERIO_PNP_IO0 175 #undef SUPERIO_PNP_IO1 176 #undef SUPERIO_PNP_IO2 177 #undef SUPERIO_PNP_IRQ0 178 #undef SUPERIO_PNP_IRQ1 179 #undef SUPERIO_PNP_DMA 180 #undef PNP_DEVICE_ACTIVE 181 #define PNP_DEVICE_ACTIVE ACT3 182 #define SUPERIO_PNP_LDN 8 183 #define SUPERIO_PNP_IO0 0x08, 0x08 184 #include <superio/acpi/pnp_generic.asl> 185#endif 186} 187