xref: /aosp_15_r20/external/coreboot/src/superio/smsc/sch5147/acpi/superio.asl (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1/* SPDX-License-Identifier: GPL-2.0-only */
2
3/*
4 * Include this file into a mainboard's DSDT _SB device tree and it will
5 * expose the SCH5147 SuperIO and some of its functionality.
6 *
7 * It allows the change of IO ports, IRQs and DMA settings on logical
8 * devices, disabling and reenabling logical devices and controlling power
9 * saving mode on logical devices or the whole chip.
10 *
11 *   LDN		State
12 * 0x0 FDC		Not implemented
13 * 0x3 PP		Not implemented
14 * 0x4 UARTA		Implemented
15 * 0x5 UARTB		Implemented
16 * 0x7 KBC		Implemented
17 * 0xa Runtime reg	Not implemented
18 *
19 * Controllable through preprocessor defines:
20 * SUPERIO_DEV		Device identifier for this SIO (e.g. SIO0)
21 * SUPERIO_PNP_BASE	I/o address of the first PnP configuration register
22 * SCH5147_SHOW_UARTA	If defined, UARTA will be exposed.
23 * SCH5147_SHOW_UARTB	If defined, UARTB will be exposed.
24 * SCH5147_SHOW_KBC	If defined, the KBC will be exposed.
25 */
26
27#undef SUPERIO_CHIP_NAME
28#define SUPERIO_CHIP_NAME SCH5147
29#include <superio/acpi/pnp.asl>
30
31#undef PNP_DEFAULT_PSC
32#define PNP_DEFAULT_PSC Return (0) /* no power management */
33
34Device(SUPERIO_DEV) {
35	Name (_HID, EisaId("PNP0A05"))
36	Name (_STR, Unicode("SMSC SCH5147 Super I/O"))
37	Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
38
39	/* Mutex for accesses to the configuration ports */
40	Mutex(CRMX, 1)
41
42	/* SuperIO configuration ports */
43	OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
44	Field (CREG, ByteAcc, NoLock, Preserve)
45	{
46		PNP_ADDR_REG,	8,
47		PNP_DATA_REG,	8
48	}
49	IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
50	{
51		Offset (0x07),
52		PNP_LOGICAL_DEVICE,	8, /* Logical device selector */
53
54		Offset (0x30),
55		PNP_DEVICE_ACTIVE,	1, /* Logical device activation */
56
57		Offset (0x60),
58		PNP_IO0_HIGH_BYTE,	8, /* First I/O port base - high byte */
59		PNP_IO0_LOW_BYTE,	8, /* First I/O port base - low byte */
60		Offset (0x62),
61		PNP_IO1_HIGH_BYTE,	8, /* Second I/O port base - high byte */
62		PNP_IO1_LOW_BYTE,	8, /* Second I/O port base - low byte */
63
64		Offset (0x70),
65		PNP_IRQ0,		8, /* First IRQ */
66		Offset (0x72),
67		PNP_IRQ1,		8, /* Second IRQ */
68
69		Offset (0x74),
70		PNP_DMA0,		8, /* DMA */
71	}
72
73	Method (_CRS)
74	{
75		/* Announce the used i/o ports to the OS */
76		Return (ResourceTemplate () {
77			IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
78		})
79	}
80
81	#undef PNP_ENTER_MAGIC_1ST
82	#undef PNP_ENTER_MAGIC_2ND
83	#undef PNP_ENTER_MAGIC_3RD
84	#undef PNP_ENTER_MAGIC_4TH
85	#undef PNP_EXIT_MAGIC_1ST
86	#undef PNP_EXIT_SPECIAL_REG
87	#undef PNP_EXIT_SPECIAL_VAL
88	#define PNP_ENTER_MAGIC_1ST	0x55
89	#define PNP_EXIT_MAGIC_1ST	0xaa
90	#include <superio/acpi/pnp_config.asl>
91
92#ifdef SCH5147_SHOW_UARTA
93	#undef SUPERIO_UART_LDN
94	#undef SUPERIO_UART_DDN
95	#undef SUPERIO_UART_PM_REG
96	#undef SUPERIO_UART_PM_VAL
97	#undef SUPERIO_UART_PM_LDN
98	#define SUPERIO_UART_LDN 4
99	#include <superio/acpi/pnp_uart.asl>
100#endif
101
102#ifdef SCH5147_SHOW_UARTB
103	#undef SUPERIO_UART_LDN
104	#undef SUPERIO_UART_DDN
105	#undef SUPERIO_UART_PM_REG
106	#undef SUPERIO_UART_PM_VAL
107	#undef SUPERIO_UART_PM_LDN
108	#define SUPERIO_UART_LDN 5
109	#include <superio/acpi/pnp_uart.asl>
110#endif
111
112#ifdef SCH5147_SHOW_KBC
113	/* we can't read back the IO resources so hardcode them */
114	#define SUPERIO_KBC_LDN 7
115Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) {
116	Name (_HID, EisaId ("PNP0303"))
117	Name (_UID, SUPERIO_UID(KBD, SUPERIO_KBC_LDN))
118
119	Method (_STA)
120	{
121		PNP_GENERIC_STA(SUPERIO_KBC_LDN)
122	}
123
124	Method (_DIS)
125	{
126		ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
127		  PNP_DEVICE_ACTIVE = 0
128		EXIT_CONFIG_MODE ()
129		#if defined(SUPERIO_KBC_PS2LDN)
130		Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1)
131		#elif defined(SUPERIO_KBC_PS2M)
132		Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1)
133		#endif
134	}
135
136	Method (_PSC) {
137		PNP_DEFAULT_PSC
138	}
139
140	Method (_CRS, 0, Serialized)
141	{
142		Name (CRS, ResourceTemplate () {
143			IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
144			IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
145			IRQNoFlags (IR0) {}
146		})
147		ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
148		  PNP_READ_IRQ(PNP_IRQ0, CRS, IR0)
149		EXIT_CONFIG_MODE ()
150		Return (CRS)
151	}
152
153	Name (_PRS, ResourceTemplate ()
154	{
155		StartDependentFn (0,0) {
156			IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
157			IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
158			IRQNoFlags () {1}
159		}
160		EndDependentFn()
161	})
162
163	Method (_SRS, 1, Serialized)
164	{
165		Name (TMPL, ResourceTemplate () {
166			IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
167			IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
168			IRQNoFlags (IR0) {}
169		})
170		ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
171		  PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0)
172		  PNP_DEVICE_ACTIVE = 1
173		EXIT_CONFIG_MODE ()
174		Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1)
175	}
176}
177
178Device (SUPERIO_ID(PS2, SUPERIO_KBC_LDN)) {
179	Name (_HID, EisaId ("PNP0F13"))
180	Name (_UID, SUPERIO_UID(PS2, SUPERIO_KBC_LDN))
181
182	Method (_STA)
183	{
184		Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA ())
185	}
186
187	Method (_PSC) {
188		Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._PSC ())
189	}
190
191	Method (_CRS, 0, Serialized)
192	{
193		Name (CRS, ResourceTemplate () {
194			IRQNoFlags (IR1) {}
195		})
196		ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
197		  PNP_READ_IRQ(PNP_IRQ1, CRS, IR1)
198		EXIT_CONFIG_MODE ()
199		Return (CRS)
200	}
201
202	Name (_PRS, ResourceTemplate ()
203	{
204		StartDependentFn (0,0) {
205			IRQNoFlags () {12}
206		}
207		EndDependentFn()
208	})
209
210	Method (_SRS, 1, Serialized)
211	{
212		Name (TMPL, ResourceTemplate () {
213			IRQNoFlags (IR1) {}
214		})
215		ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
216		  PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1)
217		EXIT_CONFIG_MODE ()
218	}
219}
220
221#endif
222}
223