1 /** @file 2 3 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 4 5 Redistribution and use in source and binary forms, with or without modification, 6 are permitted provided that the following conditions are met: 7 8 * Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, this 11 list of conditions and the following disclaimer in the documentation and/or 12 other materials provided with the distribution. 13 * Neither the name of Intel Corporation nor the names of its contributors may 14 be used to endorse or promote products derived from this software without 15 specific prior written permission. 16 17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 THE POSSIBILITY OF SUCH DAMAGE. 28 29 This file is automatically generated. Please do NOT modify !!! 30 31 **/ 32 33 #ifndef __FSPUPDVPD_H__ 34 #define __FSPUPDVPD_H__ 35 36 #pragma pack(push, 1) 37 38 39 #define MAX_CHANNELS_NUM 2 40 #define MAX_DIMMS_NUM 2 41 42 typedef struct { 43 UINT32 VendorDeviceId; 44 UINT16 SubSystemId; 45 UINT8 RevisionId; /// 0xFF applies to all steppings 46 UINT8 FrontPanelSupport; 47 UINT16 NumberOfRearJacks; 48 UINT16 NumberOfFrontJacks; 49 } BL_PCH_AZALIA_VERB_TABLE_HEADER; 50 51 typedef struct { 52 BL_PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; 53 UINT32 *VerbTableData; 54 } BL_PCH_AZALIA_VERB_TABLE; 55 56 typedef struct { 57 UINT8 Pme : 1; /// 0: Disable; 1: Enable 58 UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported 59 UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached 60 UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable 61 UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable 62 UINT8 Rsvdbits : 3; 63 UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform 64 BL_PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) 65 UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds 66 } BL_PCH_AZALIA_CONFIG; 67 68 typedef struct { 69 UINT32 Confg; 70 UINT32 ConfgChanges; 71 UINT32 Misc; 72 UINT32 MmioAddr; 73 CHAR16 *Name; 74 } BL_GPIO_FAMILY_INIT; 75 76 typedef struct { 77 UINT32 Confg0; 78 UINT32 Confg0Changes; 79 UINT32 Confg1; 80 UINT32 Confg1Changes; 81 UINT32 Community; 82 UINT32 MmioAddr; 83 CHAR16 *Name; 84 UINT32 Misc; 85 } BL_GPIO_PAD_INIT; 86 87 typedef struct { 88 UINT8 DimmId; 89 UINT32 SizeInMb; 90 UINT16 MfgId; 91 /** Module part number for DRR3 is 18 bytes 92 but DRR4 is 20 bytes as per JEDEC Spec, so 93 reserving 20 bytes **/ 94 UINT8 ModulePartNum[20]; 95 } DIMM_INFO; 96 97 typedef struct { 98 UINT8 ChannelId; 99 UINT8 DimmCount; 100 DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; 101 } CHANNEL_INFO; 102 103 typedef struct { 104 UINT8 Revision; 105 UINT8 DataWidth; 106 /** As defined in SMBIOS 3.0 spec 107 Section 7.18.2 and Table 75 108 **/ 109 UINT8 MemoryType; 110 UINT16 MemoryFrequencyInMHz; 111 /** As defined in SMBIOS 3.0 spec 112 Section 7.17.3 and Table 72 113 **/ 114 UINT8 ErrorCorrectionType; 115 UINT8 ChannelCount; 116 CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; 117 } FSP_SMBIOS_MEMORY_INFO; 118 119 120 121 typedef struct { 122 /** Offset 0x0020 123 **/ 124 UINT64 Signature; 125 /** Offset 0x0028 126 **/ 127 UINT8 Revision; 128 /** Offset 0x0029 129 **/ 130 UINT8 UnusedUpdSpace2[7]; 131 /** Offset 0x0030 132 Tseg Size 133 Size of SMRAM memory reserved. 134 **/ 135 UINT16 PcdMrcInitTsegSize; 136 /** Offset 0x0032 137 MMIO Size 138 Size of memory address space reserved for MMIO (Memory Mapped I/O). 139 **/ 140 UINT16 PcdMrcInitMmioSize; 141 /** Offset 0x0034 142 DIMM 0 SPD SMBus Address 143 SPD Address of DIMM. 144 **/ 145 UINT8 PcdMrcInitSpdAddr1; 146 /** Offset 0x0035 147 DIMM 1 SPD SMBus Address 148 SPD Address of DIMM. 149 **/ 150 UINT8 PcdMrcInitSpdAddr2; 151 /** Offset 0x0036 152 **/ 153 UINT8 PcdMemChannel0Config; 154 /** Offset 0x0037 155 **/ 156 UINT8 PcdMemChannel1Config; 157 /** Offset 0x0038 158 **/ 159 UINT32 PcdMemorySpdPtr; 160 /** Offset 0x003C 161 Internal Graphics Pre-allocated Memory 162 Size of memory preallocated for internal graphics 163 **/ 164 UINT8 PcdIgdDvmt50PreAlloc; 165 /** Offset 0x003D 166 Aperture Size 167 Select the Aperture Size. 168 **/ 169 UINT8 PcdApertureSize; 170 /** Offset 0x003E 171 GTT Size 172 Select the GTT Size. 173 **/ 174 UINT8 PcdGttSize; 175 /** Offset 0x003F 176 Enable Legacy E/F segments decoding to ROM 177 If disabled, E0000h-FFFFFh decoding will be routed to DRAM. 178 **/ 179 UINT8 PcdLegacySegDecode; 180 /** Offset 0x0040 181 Enable DVFS 182 Enable/disable DVFS. 183 **/ 184 UINT8 PcdDvfsEnable; 185 /** Offset 0x0041 186 MemoryType 187 To Configure Memory Type 188 **/ 189 UINT8 PcdMemoryTypeEnable; 190 /** Offset 0x0042 191 CaMirrorEn 192 To Enable/Disable CaMirrorEn 193 **/ 194 UINT8 PcdCaMirrorEn; 195 /** Offset 0x0043 196 DDR3 Auto Self Refresh 197 Enable/Disable DDR3 Auto Self Refresh 198 **/ 199 UINT8 PcdDdr3AutoSelfRefreshEnable; 200 /** Offset 0x0044 201 Disable Auto Detect Dram for LPDDR3 memory 202 To Enable/Disable AutoDetectDram 203 **/ 204 UINT8 PcdDisableAutoDetectDram; 205 /** Offset 0x0045 206 Dram Width 207 Select Dram Width 208 **/ 209 UINT8 PcdDramWidth; 210 /** Offset 0x0046 211 Dual Rank Enable 212 To Enable/Disable DualRankDram 213 **/ 214 UINT8 PcdDualRankDram; 215 /** Offset 0x0047 216 Dram Density 217 Select Dram Density 218 **/ 219 UINT8 PcdDramDensity; 220 /** Offset 0x0048 221 Channel 0 RX ODT Limit For Rx Power Training 222 Select RX ODT Limit for Channel 0 223 **/ 224 UINT8 PcdRxOdtLimitChannel0; 225 /** Offset 0x0049 226 Channel 1 RX ODT Limit For Rx Power Training 227 Select RX ODT Limit for Channel 1 228 **/ 229 UINT8 PcdRxOdtLimitChannel1; 230 /** Offset 0x004A 231 **/ 232 UINT8 ReservedMemoryInitUpd[182]; 233 } MEMORY_INIT_UPD; 234 235 typedef struct { 236 /** Offset 0x0100 237 **/ 238 UINT64 Signature; 239 /** Offset 0x0108 240 **/ 241 UINT8 Revision; 242 /** Offset 0x0109 243 **/ 244 UINT8 UnusedUpdSpace3[7]; 245 /** Offset 0x0110 246 SD Card Mode 247 SD Card Mode 248 **/ 249 UINT8 PcdSdcardMode; 250 /** Offset 0x0111 251 Enable HSUART0 252 Enable/disable HSUART0. 253 **/ 254 UINT8 PcdEnableHsuart0; 255 /** Offset 0x0112 256 Enable HSUART1 257 Enable/disable HSUART1. 258 **/ 259 UINT8 PcdEnableHsuart1; 260 /** Offset 0x0113 261 Enable Azalia 262 Enable/disable Azalia controller. 263 **/ 264 UINT8 PcdEnableAzalia; 265 /** Offset 0x0114 266 **/ 267 BL_PCH_AZALIA_CONFIG *AzaliaConfigPtr; 268 /** Offset 0x0118 269 Enable SATA 270 Enable/disable SATA controller. 271 **/ 272 UINT8 PcdEnableSata; 273 /** Offset 0x0119 274 Enable XHCI 275 Enable/disable XHCI controller. 276 **/ 277 UINT8 PcdEnableXhci; 278 /** Offset 0x011A 279 Enable LPE 280 Choose LPE Mode. 281 **/ 282 UINT8 PcdEnableLpe; 283 /** Offset 0x011B 284 Enable DMA0 285 Enable/disable DMA0. 286 **/ 287 UINT8 PcdEnableDma0; 288 /** Offset 0x011C 289 Enable DMA1 290 Enable/disable DMA1. 291 **/ 292 UINT8 PcdEnableDma1; 293 /** Offset 0x011D 294 Enable I2C0 295 Enable/disable I2C0. 296 **/ 297 UINT8 PcdEnableI2C0; 298 /** Offset 0x011E 299 Enable I2C1 300 Enable/disable I2C1. 301 **/ 302 UINT8 PcdEnableI2C1; 303 /** Offset 0x011F 304 Enable I2C2 305 Enable/disable I2C2. 306 **/ 307 UINT8 PcdEnableI2C2; 308 /** Offset 0x0120 309 Enable I2C3 310 Enable/disable I2C3. 311 **/ 312 UINT8 PcdEnableI2C3; 313 /** Offset 0x0121 314 Enable I2C4 315 Enable/disable I2C4. 316 **/ 317 UINT8 PcdEnableI2C4; 318 /** Offset 0x0122 319 Enable I2C5 320 Enable/disable I2C5. 321 **/ 322 UINT8 PcdEnableI2C5; 323 /** Offset 0x0123 324 Enable I2C6 325 Enable/disable I2C6. 326 **/ 327 UINT8 PcdEnableI2C6; 328 /** Offset 0x0124 329 **/ 330 UINT32 GraphicsConfigPtr; 331 /** Offset 0x0128 332 **/ 333 BL_GPIO_FAMILY_INIT *GpioFamilyInitTablePtr; 334 /** Offset 0x012C 335 **/ 336 BL_GPIO_PAD_INIT *GpioPadInitTablePtr; 337 /** Offset 0x0130 338 **/ 339 UINT8 PunitPwrConfigDisable; 340 /** Offset 0x0131 341 **/ 342 UINT8 ChvSvidConfig; 343 /** Offset 0x0132 344 **/ 345 UINT8 DptfDisable; 346 /** Offset 0x0133 347 eMMC Mode 348 EMMC Mode 349 **/ 350 UINT8 PcdEmmcMode; 351 /** Offset 0x0134 352 **/ 353 UINT8 PcdUsb3ClkSsc; 354 /** Offset 0x0135 355 **/ 356 UINT8 PcdDispClkSsc; 357 /** Offset 0x0136 358 **/ 359 UINT8 PcdSataClkSsc; 360 /** Offset 0x0137 361 **/ 362 UINT8 Usb2Port0PerPortPeTxiSet; 363 /** Offset 0x0138 364 **/ 365 UINT8 Usb2Port0PerPortTxiSet; 366 /** Offset 0x0139 367 **/ 368 UINT8 Usb2Port0IUsbTxEmphasisEn; 369 /** Offset 0x013A 370 **/ 371 UINT8 Usb2Port0PerPortTxPeHalf; 372 /** Offset 0x013B 373 **/ 374 UINT8 Usb2Port1PerPortPeTxiSet; 375 /** Offset 0x013C 376 **/ 377 UINT8 Usb2Port1PerPortTxiSet; 378 /** Offset 0x013D 379 **/ 380 UINT8 Usb2Port1IUsbTxEmphasisEn; 381 /** Offset 0x013E 382 **/ 383 UINT8 Usb2Port1PerPortTxPeHalf; 384 /** Offset 0x013F 385 **/ 386 UINT8 Usb2Port2PerPortPeTxiSet; 387 /** Offset 0x0140 388 **/ 389 UINT8 Usb2Port2PerPortTxiSet; 390 /** Offset 0x0141 391 **/ 392 UINT8 Usb2Port2IUsbTxEmphasisEn; 393 /** Offset 0x0142 394 **/ 395 UINT8 Usb2Port2PerPortTxPeHalf; 396 /** Offset 0x0143 397 **/ 398 UINT8 Usb2Port3PerPortPeTxiSet; 399 /** Offset 0x0144 400 **/ 401 UINT8 Usb2Port3PerPortTxiSet; 402 /** Offset 0x0145 403 **/ 404 UINT8 Usb2Port3IUsbTxEmphasisEn; 405 /** Offset 0x0146 406 **/ 407 UINT8 Usb2Port3PerPortTxPeHalf; 408 /** Offset 0x0147 409 **/ 410 UINT8 Usb2Port4PerPortPeTxiSet; 411 /** Offset 0x0148 412 **/ 413 UINT8 Usb2Port4PerPortTxiSet; 414 /** Offset 0x0149 415 **/ 416 UINT8 Usb2Port4IUsbTxEmphasisEn; 417 /** Offset 0x014A 418 **/ 419 UINT8 Usb2Port4PerPortTxPeHalf; 420 /** Offset 0x014B 421 **/ 422 UINT8 Usb3Lane0Ow2tapgen2deemph3p5; 423 /** Offset 0x014C 424 **/ 425 UINT8 Usb3Lane1Ow2tapgen2deemph3p5; 426 /** Offset 0x014D 427 **/ 428 UINT8 Usb3Lane2Ow2tapgen2deemph3p5; 429 /** Offset 0x014E 430 **/ 431 UINT8 Usb3Lane3Ow2tapgen2deemph3p5; 432 /** Offset 0x014F 433 SATA Interface Speed 434 Select SATA controller Interface Speed. 435 **/ 436 UINT8 PcdSataInterfaceSpeed; 437 /** Offset 0x0150 438 **/ 439 UINT8 PcdPchUsbSsicPort; 440 /** Offset 0x0151 441 **/ 442 UINT8 PcdPchUsbHsicPort; 443 /** Offset 0x0152 444 **/ 445 UINT8 PcdPcieRootPortSpeed; 446 /** Offset 0x0153 447 **/ 448 UINT8 PcdPchSsicEnable; 449 /** Offset 0x0154 450 **/ 451 UINT32 PcdLogoPtr; 452 /** Offset 0x0158 453 **/ 454 UINT32 PcdLogoSize; 455 /** Offset 0x015C 456 **/ 457 UINT8 PcdRtcLock; 458 /** Offset 0x015D 459 PMIC I2c Bus Number 460 I2c Bus Number to communicate with PMIC 461 **/ 462 UINT8 PMIC_I2CBus; 463 /** Offset 0x015E 464 Enable ISP 465 Enable/disable ISP. 466 **/ 467 UINT8 ISPEnable; 468 /** Offset 0x015F 469 Select ISP Device Number 470 Select ISP PCI Device Configuration 471 **/ 472 UINT8 ISPPciDevConfig; 473 /** Offset 0x0160 474 Processor Turbo Mode 475 Enable/disable Processor Turbo Mode. 476 **/ 477 UINT8 PcdTurboMode; 478 /** Offset 0x0161 479 Pnp Setting Type 480 Select Pnp type 481 **/ 482 UINT8 PcdPnpSettings; 483 /** Offset 0x0162 484 SdDetectChk 485 Check for Sd card detect 486 **/ 487 UINT8 PcdSdDetectChk; 488 /** Offset 0x0163 489 **/ 490 UINT8 I2C0Frequency; 491 /** Offset 0x0164 492 **/ 493 UINT8 I2C1Frequency; 494 /** Offset 0x0165 495 **/ 496 UINT8 I2C2Frequency; 497 /** Offset 0x0166 498 **/ 499 UINT8 I2C3Frequency; 500 /** Offset 0x0167 501 **/ 502 UINT8 I2C4Frequency; 503 /** Offset 0x0168 504 **/ 505 UINT8 I2C5Frequency; 506 /** Offset 0x0169 507 **/ 508 UINT8 I2C6Frequency; 509 /** Offset 0x016A 510 **/ 511 UINT8 D0Usb2Port0PerPortRXISet; 512 /** Offset 0x016B 513 **/ 514 UINT8 D0Usb2Port1PerPortRXISet; 515 /** Offset 0x016C 516 **/ 517 UINT8 D0Usb2Port2PerPortRXISet; 518 /** Offset 0x016D 519 **/ 520 UINT8 D0Usb2Port3PerPortRXISet; 521 /** Offset 0x016E 522 **/ 523 UINT8 D0Usb2Port4PerPortRXISet; 524 /** Offset 0x016F 525 **/ 526 UINT8 D0VnnBump100mV; 527 /** Offset 0x170 528 **/ 529 UINT8 ReservedSiliconInitUpd[398]; 530 } SILICON_INIT_UPD; 531 532 #define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */ 533 #define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ 534 #define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ 535 536 typedef struct _UPD_DATA_REGION { 537 /** Offset 0x0000 538 **/ 539 UINT64 Signature; 540 /** Offset 0x0008 541 **/ 542 UINT8 Revision; 543 /** Offset 0x0009 544 **/ 545 UINT8 UnusedUpdSpace0[7]; 546 /** Offset 0x0010 547 **/ 548 UINT32 MemoryInitUpdOffset; 549 /** Offset 0x0014 550 **/ 551 UINT32 SiliconInitUpdOffset; 552 /** Offset 0x0018 553 **/ 554 UINT64 UnusedUpdSpace1; 555 /** Offset 0x0020 556 **/ 557 MEMORY_INIT_UPD MemoryInitUpd; 558 /** Offset 0x0100 559 **/ 560 SILICON_INIT_UPD SiliconInitUpd; 561 /** Offset 0x0305 562 **/ 563 UINT16 PcdRegionTerminator; 564 } UPD_DATA_REGION; 565 566 #define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ 567 #define FSP_IMAGE_REV 0x01010700 568 569 typedef struct _VPD_DATA_REGION { 570 /** Offset 0x0000 571 **/ 572 UINT64 PcdVpdRegionSign; 573 /** Offset 0x0008 574 PcdImageRevision 575 **/ 576 UINT32 PcdImageRevision; 577 /** Offset 0x000C 578 **/ 579 UINT32 PcdUpdRegionOffset; 580 } VPD_DATA_REGION; 581 582 #pragma pack(pop) 583 584 #endif 585