1 /** @file 2 This file contains definitions required for creation of 3 Memory S3 Save data, Memory Info data and Memory Platform 4 data hobs. 5 6 @copyright 7 Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> 8 9 SPDX-License-Identifier: BSD-2-Clause-Patent 10 11 @par Specification Reference: 12 **/ 13 #ifndef _MEM_INFO_HOB_H_ 14 #define _MEM_INFO_HOB_H_ 15 16 17 #pragma pack (push, 1) 18 19 extern EFI_GUID gSiMemoryS3DataGuid; 20 extern EFI_GUID gSiMemoryInfoDataGuid; 21 extern EFI_GUID gSiMemoryPlatformDataGuid; 22 23 #define MAX_NODE 2 24 #define MAX_CH 4 25 #define MAX_DIMM 2 26 // Must match definitions in 27 // Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h 28 #define HOB_MAX_SAGV_POINTS 4 29 30 /// 31 /// Host reset states from MRC. 32 /// 33 #define WARM_BOOT 2 34 35 #define R_MC_CHNL_RANK_PRESENT 0x7C 36 #define B_RANK0_PRS BIT0 37 #define B_RANK1_PRS BIT1 38 #define B_RANK2_PRS BIT4 39 #define B_RANK3_PRS BIT5 40 41 // @todo remove and use the MdePkg\Include\Pi\PiHob.h 42 #if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) 43 #ifndef __HOB__H__ 44 typedef struct _EFI_HOB_GENERIC_HEADER { 45 UINT16 HobType; 46 UINT16 HobLength; 47 UINT32 Reserved; 48 } EFI_HOB_GENERIC_HEADER; 49 50 typedef struct _EFI_HOB_GUID_TYPE { 51 EFI_HOB_GENERIC_HEADER Header; 52 EFI_GUID Name; 53 /// 54 /// Guid specific data goes here 55 /// 56 } EFI_HOB_GUID_TYPE; 57 #endif 58 #endif 59 60 /// 61 /// Defines taken from MRC so avoid having to include MrcInterface.h 62 /// 63 64 // 65 // Matches MAX_SPD_SAVE define in MRC 66 // 67 #ifndef MAX_SPD_SAVE 68 #define MAX_SPD_SAVE 29 69 #endif 70 71 // 72 // MRC version description. 73 // 74 typedef struct { 75 UINT8 Major; ///< Major version number 76 UINT8 Minor; ///< Minor version number 77 UINT8 Rev; ///< Revision number 78 UINT8 Build; ///< Build number 79 } SiMrcVersion; 80 81 // 82 // Matches MrcChannelSts enum in MRC 83 // 84 #ifndef CHANNEL_NOT_PRESENT 85 #define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. 86 #endif 87 #ifndef CHANNEL_DISABLED 88 #define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. 89 #endif 90 #ifndef CHANNEL_PRESENT 91 #define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. 92 #endif 93 94 // 95 // Matches MrcDimmSts enum in MRC 96 // 97 #ifndef DIMM_ENABLED 98 #define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. 99 #endif 100 #ifndef DIMM_DISABLED 101 #define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. 102 #endif 103 #ifndef DIMM_PRESENT 104 #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. 105 #endif 106 #ifndef DIMM_NOT_PRESENT 107 #define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. 108 #endif 109 110 // 111 // Matches MrcBootMode enum in MRC 112 // 113 #ifndef __MRC_BOOT_MODE__ 114 #define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h 115 #ifndef INT32_MAX 116 #define INT32_MAX (0x7FFFFFFF) 117 #endif //INT32_MAX 118 typedef enum { 119 bmCold, ///< Cold boot 120 bmWarm, ///< Warm boot 121 bmS3, ///< S3 resume 122 bmFast, ///< Fast boot 123 MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. 124 MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. 125 } MRC_BOOT_MODE; 126 #endif //__MRC_BOOT_MODE__ 127 128 // 129 // Matches MrcDdrType enum in MRC 130 // 131 #ifndef MRC_DDR_TYPE_DDR5 132 #define MRC_DDR_TYPE_DDR5 1 133 #endif 134 #ifndef MRC_DDR_TYPE_LPDDR5 135 #define MRC_DDR_TYPE_LPDDR5 2 136 #endif 137 #ifndef MRC_DDR_TYPE_LPDDR4 138 #define MRC_DDR_TYPE_LPDDR4 3 139 #endif 140 #ifndef MRC_DDR_TYPE_UNKNOWN 141 #define MRC_DDR_TYPE_UNKNOWN 4 142 #endif 143 144 #define MAX_PROFILE_NUM 7 // number of memory profiles supported 145 #define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported 146 147 #define MAX_TRACE_REGION 5 148 #define MAX_TRACE_CACHE_TYPE 2 149 150 // 151 // DIMM timings 152 // 153 typedef struct { 154 UINT32 tCK; ///< Memory cycle time, in femtoseconds. 155 UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. 156 UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. 157 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. 158 UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. 159 UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. 160 UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. 161 UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. 162 UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. 163 UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. 164 UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. 165 UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. 166 UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. 167 UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. 168 UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. 169 UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. 170 UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. 171 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. 172 UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. 173 UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. 174 UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. 175 UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. 176 } MRC_CH_TIMING; 177 178 typedef struct { 179 UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay 180 } MRC_IP_TIMING; 181 182 /// 183 /// Memory SMBIOS & OC Memory Data Hob 184 /// 185 typedef struct { 186 UINT8 Status; ///< See MrcDimmStatus for the definition of this field. 187 UINT8 DimmId; 188 UINT32 DimmCapacity; ///< DIMM size in MBytes. 189 UINT16 MfgId; 190 UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes 191 UINT8 RankInDimm; ///< The number of ranks in this DIMM. 192 UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. 193 UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. 194 UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. 195 UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. 196 UINT16 Speed; ///< The maximum capable speed of the device, in MHz 197 UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. 198 } DIMM_INFO; 199 200 typedef struct { 201 UINT8 Status; ///< Indicates whether this channel should be used. 202 UINT8 ChannelId; 203 UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. 204 MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. 205 DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. 206 } CHANNEL_INFO; 207 208 typedef struct { 209 UINT8 Status; ///< Indicates whether this controller should be used. 210 UINT16 DeviceId; ///< The PCI device id of this memory controller. 211 UINT8 RevisionId; ///< The PCI revision id of this memory controller. 212 UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. 213 CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. 214 } CONTROLLER_INFO; 215 216 typedef struct { 217 UINT64 BaseAddress; ///< Trace Base Address 218 UINT64 TotalSize; ///< Total Trace Region of Same Cache type 219 UINT8 CacheType; ///< Trace Cache Type 220 UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code 221 UINT8 Rsvd[2]; 222 } PSMI_MEM_INFO; 223 224 /// This data structure contains per-SaGv timing values that are considered output by the MRC. 225 typedef struct { 226 UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s 227 MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec 228 MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific 229 } HOB_SAGV_TIMING_OUT; 230 231 /// This data structure contains SAGV config values that are considered output by the MRC. 232 typedef struct { 233 UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. 234 UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. 235 HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; 236 } HOB_SAGV_INFO; 237 238 typedef struct { 239 UINT8 Revision; 240 UINT16 DataWidth; ///< Data width, in bits, of this memory device 241 /** As defined in SMBIOS 3.0 spec 242 Section 7.18.2 and Table 75 243 **/ 244 UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 245 UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) 246 UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) 247 /** As defined in SMBIOS 3.0 spec 248 Section 7.17.3 and Table 72 249 **/ 250 UINT8 ErrorCorrectionType; 251 252 SiMrcVersion Version; 253 BOOLEAN EccSupport; 254 UINT8 MemoryProfile; 255 UINT8 IsDMBRunning; ///< Deprecated. 256 UINT32 TotalPhysicalMemorySize; 257 UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. 258 /// 259 /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported. 260 /// Bit 0: XMP Profile 1 capability status 261 /// Bit 1: XMP Profile 2 capability status 262 /// Bit 2: XMP Profile 3 capability status 263 /// Bit 3: User Profile 4 capability status 264 /// Bit 4: User Profile 5 capability status 265 /// 266 UINT8 XmpProfileEnable; 267 UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed 268 UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 269 UINT8 RefClk; 270 UINT32 VddVoltage[MAX_PROFILE_NUM]; 271 UINT32 VddqVoltage[MAX_PROFILE_NUM]; 272 UINT32 VppVoltage[MAX_PROFILE_NUM]; 273 CONTROLLER_INFO Controller[MAX_NODE]; 274 UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 275 UINT32 NumPopulatedChannels; ///< Total number of memory channels populated 276 HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. 277 UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels 278 BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population 279 BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config 280 BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. 281 } MEMORY_INFO_DATA_HOB; 282 283 /** 284 Memory Platform Data Hob 285 286 <b>Revision 1:</b> 287 - Initial version. 288 <b>Revision 2:</b> 289 - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields 290 **/ 291 typedef struct { 292 UINT8 Revision; 293 UINT8 Reserved[3]; 294 UINT32 BootMode; 295 UINT32 TsegSize; 296 UINT32 TsegBase; 297 UINT32 PrmrrSize; 298 UINT64 PrmrrBase; 299 UINT32 GttBase; 300 UINT32 MmioSize; 301 UINT32 PciEBaseAddress; 302 PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; 303 PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; 304 BOOLEAN MrcBasicMemoryTestPass; 305 } MEMORY_PLATFORM_DATA; 306 307 typedef struct { 308 EFI_HOB_GUID_TYPE EfiHobGuidType; 309 MEMORY_PLATFORM_DATA Data; 310 UINT8 *Buffer; 311 } MEMORY_PLATFORM_DATA_HOB; 312 313 #pragma pack (pop) 314 315 #endif // _MEM_INFO_HOB_H_ 316