1 /*
2  * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_X4_H
8 #define CORTEX_X4_H
9 
10 #define CORTEX_X4_MIDR					U(0x410FD821)
11 
12 /* Cortex X4 loop count for CVE-2022-23960 mitigation */
13 #define CORTEX_X4_BHB_LOOP_COUNT			U(132)
14 
15 /*******************************************************************************
16  * CPU Extended Control register specific definitions
17  ******************************************************************************/
18 #define CORTEX_X4_CPUECTLR_EL1				S3_0_C15_C1_4
19 
20 /*******************************************************************************
21  * CPU Power Control register specific definitions
22  ******************************************************************************/
23 #define CORTEX_X4_CPUPWRCTLR_EL1			S3_0_C15_C2_7
24 #define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
25 
26 /*******************************************************************************
27  * CPU Auxiliary control register specific definitions
28  ******************************************************************************/
29 #define CORTEX_X4_CPUACTLR3_EL1				S3_0_C15_C1_2
30 
31 #endif /* CORTEX_X4_H */
32