1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <acpi/acpi.h>
4 #include <acpi/acpigen.h>
5 #include <amdblocks/cppc.h>
6 #include <amdblocks/cpu.h>
7 #include <console/console.h>
8 #include <cpu/amd/msr.h>
9 #include <cpu/x86/msr.h>
10 #include <soc/msr.h>
11 #include <types.h>
12
get_pstate_core_power(union pstate_msr pstate_reg)13 static uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
14 {
15 uint32_t voltage_in_uvolts, current_value_amps, current_divisor, power_in_mw;
16
17 /* Get Voltage from core voltage ID */
18 voltage_in_uvolts = get_pstate_core_uvolts(pstate_reg);
19
20 /* Current value in amps */
21 current_value_amps = pstate_reg.idd_value;
22
23 /* Current divisor */
24 current_divisor = pstate_reg.idd_div;
25
26 /* Power in mW */
27 power_in_mw = (voltage_in_uvolts) / 10 * current_value_amps;
28
29 switch (current_divisor) {
30 case 0:
31 power_in_mw = power_in_mw / 100L;
32 break;
33 case 1:
34 power_in_mw = power_in_mw / 1000L;
35 break;
36 case 2:
37 power_in_mw = power_in_mw / 10000L;
38 break;
39 case 3:
40 /* current_divisor is set to an undefined value.*/
41 printk(BIOS_WARNING, "Undefined current_divisor set for enabled P-state .\n");
42 power_in_mw = 0;
43 break;
44 }
45
46 return power_in_mw;
47 }
48
get_visible_pstate_count(void)49 static uint32_t get_visible_pstate_count(void)
50 {
51 return (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
52 }
53
54 /*
55 * Populate structure describing enabled p-states and return count of enabled p-states.
56 */
get_pstate_info(struct acpi_sw_pstate * pstate_values,struct acpi_xpss_sw_pstate * pstate_xpss_values)57 static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
58 struct acpi_xpss_sw_pstate *pstate_xpss_values)
59 {
60 union pstate_msr pstate_reg;
61 size_t pstate_count, pstate;
62 uint32_t pstate_0_reg, max_pstate, latency;
63
64 pstate_count = 0;
65 pstate_0_reg = get_pstate_0_reg();
66 max_pstate = get_visible_pstate_count();
67 latency = get_pstate_latency();
68
69 for (pstate = 0; pstate <= max_pstate; pstate++) {
70 pstate_reg.raw = rdmsr(PSTATE_MSR(pstate_0_reg + pstate)).raw;
71
72 if (!pstate_reg.pstate_en)
73 continue;
74
75 pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_reg);
76 pstate_values[pstate_count].power = get_pstate_core_power(pstate_reg);
77 pstate_values[pstate_count].transition_latency = latency;
78 pstate_values[pstate_count].bus_master_latency = latency;
79 pstate_values[pstate_count].control_value = pstate;
80 pstate_values[pstate_count].status_value = pstate;
81
82 pstate_xpss_values[pstate_count].core_freq =
83 (uint64_t)pstate_values[pstate_count].core_freq;
84 pstate_xpss_values[pstate_count].power =
85 (uint64_t)pstate_values[pstate_count].power;
86 pstate_xpss_values[pstate_count].transition_latency = latency;
87 pstate_xpss_values[pstate_count].bus_master_latency = latency;
88 pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate;
89 pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate;
90 pstate_count++;
91 }
92
93 return pstate_count;
94 }
95
get_cstate_io_base_address(void)96 static uint16_t get_cstate_io_base_address(void)
97 {
98 static uint16_t cstate_io_base;
99
100 if (cstate_io_base)
101 return cstate_io_base;
102
103 cstate_io_base = rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK;
104
105 return cstate_io_base;
106 }
107
write_cstate_entry(acpi_cstate_t * entry,const acpi_cstate_t * data)108 static void write_cstate_entry(acpi_cstate_t *entry, const acpi_cstate_t *data)
109 {
110 if (!data->ctype) {
111 printk(BIOS_WARNING, "Invalid C-state data; skipping entry.\n");
112 return;
113 }
114
115 entry->ctype = data->ctype;
116 entry->latency = data->latency;
117 entry->power = data->power;
118
119 if (data->ctype == 1) {
120 entry->resource = (acpi_addr_t){
121 .space_id = ACPI_ADDRESS_SPACE_FIXED,
122 .bit_width = 2,
123 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
124 .addrl = 0,
125 .addrh = 0,
126 };
127 } else {
128 entry->resource = (acpi_addr_t){
129 .space_id = ACPI_ADDRESS_SPACE_IO,
130 .bit_width = 8,
131 .bit_offset = 0,
132 /* ctype is 1-indexed while the offset into the IO address returned by
133 get_cstate_io_base_address() is 0-indexed */
134 .addrl = get_cstate_io_base_address() + data->ctype - 1,
135 .addrh = 0,
136 .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS,
137 };
138 }
139 }
140
get_cstate_info(acpi_cstate_t * cstate_values)141 static size_t get_cstate_info(acpi_cstate_t *cstate_values)
142 {
143 size_t i;
144 size_t cstate_count;
145 const acpi_cstate_t *cstate_config = get_cstate_config_data(&cstate_count);
146
147 if (cstate_count > MAX_CSTATE_COUNT) {
148 printk(BIOS_WARNING, "cstate_info array has too many entries. "
149 "Skipping last %zu entries.\n",
150 cstate_count - MAX_CSTATE_COUNT);
151 cstate_count = MAX_CSTATE_COUNT;
152 }
153
154 for (i = 0; i < cstate_count; i++) {
155 write_cstate_entry(&cstate_values[i], &cstate_config[i]);
156 }
157
158 return i;
159 }
160
generate_cpu_entries(const struct device * device)161 void generate_cpu_entries(const struct device *device)
162 {
163 int logical_cores;
164 size_t cstate_count, pstate_count, cpu;
165 acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
166 struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
167 struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
168 uint32_t threads_per_core;
169
170 const acpi_addr_t perf_ctrl = {
171 .space_id = ACPI_ADDRESS_SPACE_FIXED,
172 .bit_width = 64,
173 .addrl = PS_CTL_REG,
174 };
175 const acpi_addr_t perf_sts = {
176 .space_id = ACPI_ADDRESS_SPACE_FIXED,
177 .bit_width = 64,
178 .addrl = PS_STS_REG,
179 };
180
181 threads_per_core = get_threads_per_core();
182 cstate_count = get_cstate_info(cstate_values);
183 pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
184 logical_cores = get_cpu_count();
185
186 for (cpu = 0; cpu < logical_cores; cpu++) {
187 acpigen_write_processor_device(cpu);
188
189 acpigen_write_pct_package(&perf_ctrl, &perf_sts);
190
191 acpigen_write_pss_object(pstate_values, pstate_count);
192
193 acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
194
195 if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
196 acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
197 HW_ALL);
198 else
199 acpigen_write_PSD_package(0, logical_cores, SW_ALL);
200
201 acpigen_write_PPC(0);
202
203 acpigen_write_CST_package(cstate_values, cstate_count);
204
205 acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
206 CSD_HW_ALL, 0);
207
208 if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_CPPC))
209 generate_cppc_entries(cpu);
210
211 acpigen_write_processor_device_end();
212 }
213
214 acpigen_write_processor_package("PPKG", 0, logical_cores);
215 }
216