1 /* 2 * Copyright © Microsoft Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #ifndef D3D12_VIDEO_ENC_NALU_WRITER_HEVC_H 25 #define D3D12_VIDEO_ENC_NALU_WRITER_HEVC_H 26 27 #include "d3d12_video_encoder_bitstream.h" 28 29 #define HEVC_MAX_REF_PICS 16 30 #define HEVC_MAX_SUB_LAYERS_NUM 7 31 #define HEVC_MAX_TILE_NUM 64 32 33 #define MAX_COMPRESSED_NALU (10*1024) 34 35 enum HEVCNaluType { 36 HEVC_NALU_TRAIL_N = 0, 37 HEVC_NALU_TRAIL_R = 1, 38 HEVC_NALU_TSA_N = 2, 39 HEVC_NALU_TSA_R = 3, 40 HEVC_NALU_STSA_N = 4, 41 HEVC_NALU_STSA_R = 5, 42 HEVC_NALU_RADL_N = 6, 43 HEVC_NALU_RADL_R = 7, 44 HEVC_NALU_RASL_N = 8, 45 HEVC_NALU_RASL_R = 9, 46 HEVC_NALU_RSV_VCL_N10 = 10, 47 HEVC_NALU_RSV_VCL_N12 = 12, 48 HEVC_NALU_RSV_VCL_N14 = 14, 49 HEVC_NALU_RSV_VCL_R11 = 11, 50 HEVC_NALU_RSV_VCL_R13 = 13, 51 HEVC_NALU_RSV_VCL_R15 = 15, 52 HEVC_NALU_BLA_W_LP = 16, 53 HEVC_NALU_BLA_W_RADL = 17, 54 HEVC_NALU_BLA_N_LP = 18, 55 HEVC_NALU_IDR_W_RADL = 19, 56 HEVC_NALU_IDR_N_LP = 20, 57 HEVC_NALU_CRA_NUT = 21, 58 HEVC_NALU_RSV_IRAP_VCL22 = 22, 59 HEVC_NALU_RSV_IRAP_VCL23 = 23, 60 HEVC_NALU_RSV_VCL_24 = 24, 61 HEVC_NALU_RSV_VCL_25 = 25, 62 HEVC_NALU_RSV_VCL_26 = 26, 63 HEVC_NALU_RSV_VCL_27 = 27, 64 HEVC_NALU_RSV_VCL_28 = 28, 65 HEVC_NALU_RSV_VCL_29 = 29, 66 HEVC_NALU_RSV_VCL_30 = 30, 67 HEVC_NALU_RSV_VCL_31 = 31, 68 HEVC_NALU_VPS_NUT = 32, 69 HEVC_NALU_SPS_NUT = 33, 70 HEVC_NALU_PPS_NUT = 34, 71 HEVC_NALU_AUD_NUT = 35, 72 HEVC_NALU_EOS_NUT = 36, 73 HEVC_NALU_EOB_NUT = 37, 74 HEVC_NALU_FD_NUT = 38, 75 HEVC_NALU_PREFIX_SEI_NUT = 39, 76 HEVC_NALU_SUFFIX_SEI_NUT = 40, 77 }; 78 79 struct HEVCNaluHeader { 80 uint8_t forbidden_zero_bit; 81 uint8_t nal_unit_type; 82 uint8_t nuh_layer_id; 83 uint8_t nuh_temporal_id_plus1; 84 }; 85 86 struct HEVCProfileTierLevel { 87 uint8_t general_profile_space; 88 uint8_t general_tier_flag; 89 uint8_t general_profile_idc; 90 uint8_t general_profile_compatibility_flag[32]; 91 uint8_t general_progressive_source_flag; 92 uint8_t general_interlaced_source_flag; 93 uint8_t general_non_packed_constraint_flag; 94 uint8_t general_frame_only_constraint_flag; 95 uint8_t general_max_12bit_constraint_flag; 96 uint8_t general_max_10bit_constraint_flag; 97 uint8_t general_max_8bit_constraint_flag; 98 uint8_t general_max_422chroma_constraint_flag; 99 uint8_t general_max_420chroma_constraint_flag; 100 uint8_t general_max_monochrome_constraint_flag; 101 uint8_t general_intra_constraint_flag; 102 uint8_t general_one_picture_only_constraint_flag; 103 uint8_t general_lower_bit_rate_constraint_flag; 104 uint8_t general_max_14bit_constraint_flag; 105 uint8_t general_inbld_flag; 106 uint8_t general_level_idc; 107 uint8_t sub_layer_profile_present_flag[HEVC_MAX_SUB_LAYERS_NUM - 1]; 108 uint8_t sub_layer_level_present_flag[HEVC_MAX_SUB_LAYERS_NUM - 1]; 109 uint8_t sub_layer_profile_space[HEVC_MAX_SUB_LAYERS_NUM - 1]; 110 uint8_t sub_layer_tier_flag[HEVC_MAX_SUB_LAYERS_NUM - 1]; 111 uint8_t sub_layer_profile_idc[HEVC_MAX_SUB_LAYERS_NUM - 1]; 112 uint8_t sub_layer_profile_compatibility_flag[HEVC_MAX_SUB_LAYERS_NUM - 1][32]; 113 uint8_t sub_layer_progressive_source_flag[HEVC_MAX_SUB_LAYERS_NUM - 1]; 114 uint8_t sub_layer_interlaced_source_flag[HEVC_MAX_SUB_LAYERS_NUM - 1]; 115 uint8_t sub_layer_non_packed_constraint_flag[HEVC_MAX_SUB_LAYERS_NUM - 1]; 116 uint8_t sub_layer_frame_only_constraint_flag[HEVC_MAX_SUB_LAYERS_NUM - 1]; 117 int32_t sub_layer_level_idc[HEVC_MAX_SUB_LAYERS_NUM - 1]; 118 }; 119 120 struct ReferencePictureSet { 121 int32_t numberOfPictures; 122 int32_t numberOfNegativePictures; 123 int32_t numberOfPositivePictures; 124 int32_t numberOfLongtermPictures; 125 int32_t deltaPOC[HEVC_MAX_REF_PICS]; 126 int32_t POC[HEVC_MAX_REF_PICS]; 127 uint8_t used[HEVC_MAX_REF_PICS]; 128 uint8_t interRPSPrediction; 129 int32_t deltaRIdxMinus1; 130 int32_t deltaRPS; 131 int32_t numRefIdc; 132 int32_t refIdc[HEVC_MAX_REF_PICS + 1]; 133 uint8_t bCheckLTMSB[HEVC_MAX_REF_PICS]; 134 int32_t pocLSBLT[HEVC_MAX_REF_PICS]; 135 int32_t deltaPOCMSBCycleLT[HEVC_MAX_REF_PICS]; 136 uint8_t deltaPocMSBPresentFlag[HEVC_MAX_REF_PICS]; 137 }; 138 139 struct HEVCReferencePictureSet { 140 uint8_t inter_ref_pic_set_prediction_flag; 141 union { 142 struct { 143 uint32_t delta_idx_minus1; 144 uint8_t delta_rps_sign; 145 uint32_t abs_delta_rps_minus1; 146 uint8_t used_by_curr_pic_flag[HEVC_MAX_REF_PICS]; 147 uint8_t use_delta_flag[HEVC_MAX_REF_PICS]; 148 }; 149 struct { 150 int32_t num_negative_pics; 151 int32_t num_positive_pics; 152 int32_t delta_poc_s0_minus1[HEVC_MAX_REF_PICS]; 153 uint8_t used_by_curr_pic_s0_flag[HEVC_MAX_REF_PICS]; 154 int32_t delta_poc_s1_minus1[HEVC_MAX_REF_PICS]; 155 uint8_t used_by_curr_pic_s1_flag[HEVC_MAX_REF_PICS]; 156 }; 157 }; 158 }; 159 160 struct HEVCVideoUsabilityInfo { 161 uint8_t aspect_ratio_info_present_flag; 162 uint8_t aspect_ratio_idc; 163 int32_t sar_width; 164 int32_t sar_height; 165 uint8_t overscan_info_present_flag; 166 uint8_t overscan_appropriate_flag; 167 uint8_t video_signal_type_present_flag; 168 uint8_t video_format; 169 uint8_t video_full_range_flag; 170 uint8_t colour_description_present_flag; 171 uint8_t colour_primaries; 172 uint8_t transfer_characteristics; 173 uint8_t matrix_coeffs; 174 uint8_t chroma_loc_info_present_flag; 175 int32_t chroma_sample_loc_type_top_field; 176 int32_t chroma_sample_loc_type_bottom_field; 177 uint8_t neutral_chroma_indication_flag; 178 uint8_t field_seq_flag; 179 uint8_t frame_field_info_present_flag; 180 uint8_t default_display_window_flag; 181 int32_t def_disp_win_left_offset; 182 int32_t def_disp_win_right_offset; 183 int32_t def_disp_win_top_offset; 184 int32_t def_disp_win_bottom_offset; 185 uint8_t timing_info_present_flag; 186 uint32_t num_units_in_tick; 187 uint32_t time_scale; 188 uint8_t poc_proportional_to_timing_flag; 189 uint32_t num_ticks_poc_diff_one_minus1; 190 uint8_t hrd_parameters_present_flag; 191 uint8_t bitstream_restriction_flag; 192 uint8_t tiles_fixed_structure_flag; 193 uint8_t motion_vectors_over_pic_boundaries_flag; 194 uint8_t restricted_ref_pic_lists_flag; 195 uint32_t min_spatial_segmentation_idc; 196 uint32_t max_bytes_per_pic_denom; 197 uint32_t max_bits_per_min_cu_denom; 198 uint32_t log2_max_mv_length_horizontal; 199 uint32_t log2_max_mv_length_vertical; 200 }; 201 202 struct HevcSeqParameterSet { 203 HEVCNaluHeader nalu; 204 uint8_t sps_video_parameter_set_id; 205 uint8_t sps_max_sub_layers_minus1; 206 uint8_t sps_temporal_id_nesting_flag; 207 HEVCProfileTierLevel ptl; 208 uint8_t sps_seq_parameter_set_id; 209 uint8_t chroma_format_idc; 210 uint8_t separate_colour_plane_flag; 211 int32_t pic_width_in_luma_samples; 212 int32_t pic_height_in_luma_samples; 213 uint8_t conformance_window_flag; 214 int32_t conf_win_left_offset; 215 int32_t conf_win_right_offset; 216 int32_t conf_win_top_offset; 217 int32_t conf_win_bottom_offset; 218 uint8_t bit_depth_luma_minus8; 219 uint8_t bit_depth_chroma_minus8; 220 uint8_t log2_max_pic_order_cnt_lsb_minus4; 221 int maxPicOrderCntLsb; 222 uint8_t sps_sub_layer_ordering_info_present_flag; 223 int32_t sps_max_dec_pic_buffering_minus1[HEVC_MAX_SUB_LAYERS_NUM]; 224 int32_t sps_max_num_reorder_pics[HEVC_MAX_SUB_LAYERS_NUM]; 225 int32_t sps_max_latency_increase_plus1[HEVC_MAX_SUB_LAYERS_NUM]; 226 uint8_t log2_min_luma_coding_block_size_minus3; 227 uint8_t log2_diff_max_min_luma_coding_block_size; 228 uint8_t log2_min_transform_block_size_minus2; 229 uint8_t log2_diff_max_min_transform_block_size; 230 uint8_t max_transform_hierarchy_depth_inter; 231 uint8_t max_transform_hierarchy_depth_intra; 232 uint8_t scaling_list_enabled_flag; 233 uint8_t sps_scaling_list_data_present_flag; 234 uint8_t scaling_list_pred_mode_flag[4][6]; 235 uint32_t scaling_list_pred_matrix_id_delta[4][6]; 236 int32_t scaling_list_dc_coef_minus8[2][6]; 237 int32_t scaling_list_delta_coef; 238 int32_t ScalingList[4][6][64]; 239 uint8_t amp_enabled_flag; 240 uint8_t sample_adaptive_offset_enabled_flag; 241 uint8_t pcm_enabled_flag; 242 uint8_t pcm_sample_bit_depth_luma_minus1; 243 uint8_t pcm_sample_bit_depth_chroma_minus1; 244 int32_t log2_min_pcm_luma_coding_block_size_minus3; 245 int32_t log2_diff_max_min_pcm_luma_coding_block_size; 246 uint8_t pcm_loop_filter_disabled_flag; 247 uint8_t num_short_term_ref_pic_sets; 248 HEVCReferencePictureSet rpsShortTerm[64]; 249 uint8_t long_term_ref_pics_present_flag; 250 uint8_t num_long_term_ref_pics_sps; 251 int32_t lt_ref_pic_poc_lsb_sps[32]; 252 uint8_t used_by_curr_pic_lt_sps_flag[32]; 253 uint8_t sps_temporal_mvp_enabled_flag; 254 uint8_t strong_intra_smoothing_enabled_flag; 255 uint8_t vui_parameters_present_flag; 256 HEVCVideoUsabilityInfo vui; 257 uint8_t sps_extension_present_flag; 258 uint8_t sps_extension_data_flag; 259 struct { 260 uint32_t sps_range_extension_flag; 261 uint32_t transform_skip_rotation_enabled_flag: 1; 262 uint32_t transform_skip_context_enabled_flag: 1; 263 uint32_t implicit_rdpcm_enabled_flag: 1; 264 uint32_t explicit_rdpcm_enabled_flag: 1; 265 uint32_t extended_precision_processing_flag: 1; 266 uint32_t intra_smoothing_disabled_flag: 1; 267 uint32_t high_precision_offsets_enabled_flag: 1; 268 uint32_t persistent_rice_adaptation_enabled_flag: 1; 269 uint32_t cabac_bypass_alignment_enabled_flag: 1; 270 } sps_range_extension; 271 }; 272 273 struct HevcPicParameterSet { 274 HEVCNaluHeader nalu; 275 uint8_t pps_pic_parameter_set_id; 276 uint8_t pps_seq_parameter_set_id; 277 uint8_t dependent_slice_segments_enabled_flag; 278 uint8_t output_flag_present_flag; 279 uint8_t num_extra_slice_header_bits; 280 uint8_t sign_data_hiding_enabled_flag; 281 uint8_t cabac_init_present_flag; 282 uint8_t num_ref_idx_lx_default_active_minus1[2]; 283 int8_t init_qp_minus26; 284 uint8_t constrained_intra_pred_flag; 285 uint8_t transform_skip_enabled_flag; 286 uint8_t cu_qp_delta_enabled_flag; 287 uint8_t diff_cu_qp_delta_depth; 288 int8_t pps_cb_qp_offset; 289 int8_t pps_cr_qp_offset; 290 uint8_t pps_slice_chroma_qp_offsets_present_flag; 291 uint8_t weighted_pred_flag; 292 uint8_t weighted_bipred_flag; 293 uint8_t transquant_bypass_enabled_flag; 294 uint8_t tiles_enabled_flag; 295 uint8_t entropy_coding_sync_enabled_flag; 296 int32_t num_tile_columns_minus1; 297 int32_t num_tile_rows_minus1; 298 uint8_t uniform_spacing_flag; 299 int32_t column_width_minus1[HEVC_MAX_TILE_NUM]; 300 int32_t row_height_minus1[HEVC_MAX_TILE_NUM]; 301 uint8_t loop_filter_across_tiles_enabled_flag; 302 uint8_t pps_loop_filter_across_slices_enabled_flag; 303 uint8_t deblocking_filter_control_present_flag; 304 uint8_t deblocking_filter_override_enabled_flag; 305 uint8_t pps_deblocking_filter_disabled_flag; 306 int8_t pps_beta_offset_div2; 307 int8_t pps_tc_offset_div2; 308 uint8_t pps_scaling_list_data_present_flag; 309 uint8_t lists_modification_present_flag; 310 uint8_t log2_parallel_merge_level_minus2; 311 uint8_t slice_segment_header_extension_present_flag; 312 uint8_t pps_extension_present_flag; 313 uint8_t pps_extension_data_flag; 314 struct { 315 uint8_t pps_range_extension_flag; 316 uint32_t log2_max_transform_skip_block_size_minus2; 317 uint32_t cross_component_prediction_enabled_flag: 1; 318 uint32_t chroma_qp_offset_list_enabled_flag: 1; 319 uint32_t diff_cu_chroma_qp_offset_depth; 320 uint32_t chroma_qp_offset_list_len_minus1; 321 int32_t cb_qp_offset_list[6]; 322 int32_t cr_qp_offset_list[6]; 323 uint32_t log2_sao_offset_scale_luma; 324 uint32_t log2_sao_offset_scale_chroma; 325 } pps_range_extension; 326 }; 327 328 struct HevcVideoParameterSet { 329 HEVCNaluHeader nalu; 330 uint8_t vps_video_parameter_set_id; 331 uint8_t vps_reserved_three_2bits; 332 uint8_t vps_max_layers_minus1; 333 uint8_t vps_max_sub_layers_minus1; 334 uint8_t vps_temporal_id_nesting_flag; 335 int32_t vps_reserved_0xffff_16bits; 336 HEVCProfileTierLevel ptl; 337 uint8_t vps_sub_layer_ordering_info_present_flag; 338 uint8_t vps_max_dec_pic_buffering_minus1[HEVC_MAX_SUB_LAYERS_NUM]; 339 uint8_t vps_max_num_reorder_pics[HEVC_MAX_SUB_LAYERS_NUM]; 340 uint8_t vps_max_latency_increase_plus1[HEVC_MAX_SUB_LAYERS_NUM]; 341 uint8_t vps_max_layer_id; 342 uint8_t vps_num_layer_sets_minus1; 343 uint8_t layer_id_included_flag[1024][1]; 344 uint8_t vps_timing_info_present_flag; 345 uint32_t vps_num_units_in_tick; 346 uint32_t vps_time_scale; 347 uint8_t vps_poc_proportional_to_timing_flag; 348 uint32_t vps_num_ticks_poc_diff_one_minus1; 349 uint32_t vps_num_hrd_parameters; 350 uint32_t hrd_layer_set_idx[1024]; 351 uint8_t cprms_present_flag[1024]; 352 uint8_t vps_extension_flag; 353 uint8_t vps_extension_data_flag; 354 }; 355 356 struct HevcAccessUnitDelimiter { 357 HEVCNaluHeader nalu; 358 uint8_t pic_type; 359 }; 360 361 class d3d12_video_nalu_writer_hevc 362 { 363 public: d3d12_video_nalu_writer_hevc()364 d3d12_video_nalu_writer_hevc() { } ~d3d12_video_nalu_writer_hevc()365 ~d3d12_video_nalu_writer_hevc() { } 366 367 // Writes the HEVC VPS structure into a bitstream passed in headerBitstream 368 // Function resizes bitstream accordingly and puts result in byte vector 369 void vps_to_nalu_bytes(HevcVideoParameterSet *pVPS, 370 std::vector<BYTE> 371 &headerBitstream, 372 std::vector<BYTE>::iterator 373 placingPositionStart, 374 size_t &writtenBytes); 375 376 // Writes the HEVC SPS structure into a bitstream passed in headerBitstream 377 // Function resizes bitstream accordingly and puts result in byte vector 378 void sps_to_nalu_bytes(HevcSeqParameterSet *pSPS, 379 std::vector<BYTE> 380 &headerBitstream, 381 std::vector<BYTE>::iterator 382 placingPositionStart, 383 size_t &writtenBytes); 384 385 // Writes the HEVC PPS structure into a bitstream passed in headerBitstream 386 // Function resizes bitstream accordingly and puts result in byte vector 387 void pps_to_nalu_bytes(HevcPicParameterSet *pPPS, 388 std::vector<BYTE> 389 &headerBitstream, 390 std::vector<BYTE>::iterator 391 placingPositionStart, 392 size_t &writtenBytes); 393 394 void write_end_of_stream_nalu(std::vector<BYTE> &headerBitstream, 395 std::vector<BYTE>::iterator 396 placingPositionStart, 397 size_t 398 &writtenBytes); 399 void write_end_of_sequence_nalu(std::vector<BYTE> 400 &headerBitstream, 401 std::vector<BYTE>::iterator 402 placingPositionStart, 403 size_t &writtenBytes); 404 405 void write_aud(std::vector<uint8_t> & headerBitstream, 406 std::vector<uint8_t>::iterator placingPositionStart, 407 D3D12_VIDEO_ENCODER_FRAME_TYPE_HEVC frameType, 408 size_t & writtenBytes); 409 private: 410 411 // Writes from structure into bitstream with RBSP trailing but WITHOUT NAL unit wrap (eg. nal_idc_type, etc) 412 uint32_t write_vps_bytes(d3d12_video_encoder_bitstream *pBitstream, HevcVideoParameterSet *pSPS); 413 uint32_t write_sps_bytes(d3d12_video_encoder_bitstream *pBitstream, HevcSeqParameterSet *pSPS); 414 uint32_t write_pps_bytes(d3d12_video_encoder_bitstream *pBitstream, HevcPicParameterSet *pPPS); 415 uint32_t write_aud_bytes(d3d12_video_encoder_bitstream *pBitstream, HevcAccessUnitDelimiter *pAUD); 416 417 // Adds NALU wrapping into structures and ending NALU control bits 418 uint32_t wrap_rbsp_into_nalu(d3d12_video_encoder_bitstream *pNALU, d3d12_video_encoder_bitstream *pRBSP, HEVCNaluHeader *pHeader); 419 420 // Helpers 421 void write_nalu_end(d3d12_video_encoder_bitstream *pNALU); 422 void rbsp_trailing(d3d12_video_encoder_bitstream *pBitstream); 423 void write_profile_tier_level(d3d12_video_encoder_bitstream* rbsp, HEVCProfileTierLevel* ptl); 424 425 void generic_write_bytes(std::vector<BYTE> &headerBitstream, 426 std::vector<BYTE>::iterator placingPositionStart, 427 size_t &writtenBytes, 428 void *pStructure); 429 uint32_t 430 write_bytes_from_struct(d3d12_video_encoder_bitstream *pBitstream, void *pData, uint8_t nal_unit_type); 431 432 void write_rps(d3d12_video_encoder_bitstream* rbsp, HevcSeqParameterSet* sps, int stRpsIdx, bool sliceRPS); 433 }; 434 435 #endif 436