1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4 
5 #ifndef __DCN401_CLK_MGR_SMU_MSG_H_
6 #define __DCN401_CLK_MGR_SMU_MSG_H_
7 
8 #include "os_types.h"
9 #include "core_types.h"
10 #include "dcn32/dcn32_clk_mgr_smu_msg.h"
11 
12 void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);
13 void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);
14 void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
15 void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
16 void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
17 unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);
18 void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);
19 void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate);
20 bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
21 		uint16_t uclk_freq_mhz,
22 		uint16_t fclk_freq_mhz);
23 bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
24 		uint16_t uclk_freq_mhz,
25 		uint16_t fclk_freq_mhz);
26 bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
27 		uint16_t uclk_freq_mhz,
28 		uint16_t fclk_freq_mhz);
29 void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);
30 void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);
31 unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr);
32 
33 #endif /* __DCN401_CLK_MGR_SMU_MSG_H_ */
34