1 /*
2 * Copyright (c) 2019-2023, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file     decode_status_report_defs.h
24 //! \brief    Defines the common struture for decode status report
25 //! \details
26 //!
27 #ifndef __DECODE_STATUS_REPORT_DEFS_H__
28 #define __DECODE_STATUS_REPORT_DEFS_H__
29 
30 #include "mos_defs.h"
31 #include "codec_def_common.h"
32 #include "media_status_report.h"
33 
34 namespace decode
35 {
36 
37 enum CsEngineIdDef
38 {
39     // Instance ID
40     csInstanceIdVdbox0 = 0,
41     csInstanceIdVdbox1 = 1,
42     csInstanceIdVdbox2 = 2,
43     csInstanceIdVdbox3 = 3,
44     csInstanceIdVdbox4 = 4,
45     csInstanceIdVdbox5 = 5,
46     csInstanceIdVdbox6 = 6,
47     csInstanceIdVdbox7 = 7,
48     csInstanceIdMax,
49     // Class ID
50     classIdVideoEngine = 1,
51 };
52 
53 union CsEngineId
54 {
55     struct
56     {
57         uint32_t       classId            : 3;    //[0...4]
58         uint32_t       reservedFiled1     : 1;    //[0]
59         uint32_t       instanceId         : 6;    //[0...7]
60         uint32_t       reservedField2     : 22;   //[0]
61     } fields;
62     uint32_t            value;
63 };
64 
65 enum DecodeStatusReportType
66 {
67     statusReportGlobalCount = STATUS_REPORT_GLOBAL_COUNT,
68     statusReportMfx,
69 
70     //! \brief decode error status
71     DecErrorStatusOffset,
72 
73     //! \brief decode MB count
74     DecMBCountOffset,
75 
76     //! \brief decode frame CRC
77     DecFrameCrcOffset,
78 
79     //! \brief CS engine ID
80     CsEngineIdOffset_0,
81     CsEngineIdOffset_1,
82     CsEngineIdOffset_2,
83     CsEngineIdOffset_3,
84     CsEngineIdOffset_4,
85     CsEngineIdOffset_5,
86     CsEngineIdOffset_6,
87     CsEngineIdOffset_7,
88 
89     //! \brief MMIO HuCErrorStatus2
90     HucErrorStatus2Reg,
91 
92     //! \brief mask of MMIO HuCErrorStatus2
93     HucErrorStatus2Mask,
94 
95     //! \brief MMIO HuCErrorStatus
96     HucErrorStatusReg,
97     //! \brief mask of MMIO HuCErrorStatus
98     HucErrorStatusMask,
99 
100     statusReportRcs,
101     statusReportMaxNum
102 };
103 
104 struct DecodeStatusParameters
105 {
106     uint32_t           statusReportFeedbackNumber;
107     uint32_t           numberTilesInFrame;
108     uint16_t           pictureCodingType;
109     CODEC_PICTURE      currOriginalPic;
110     CODECHAL_FUNCTION  codecFunction;
111     uint8_t            numUsedVdbox;
112     PCODEC_REF_LIST    currRefList;
113     uint16_t           picWidthInMb;
114     uint16_t           frameFieldHeightInMb;
115     uint32_t           numSlices;
116     MOS_RESOURCE       currDecodedPicRes;
117     bool               isSecondField;
118 #if (_DEBUG || _RELEASE_INTERNAL)
119     MOS_SURFACE       *sfcOutputSurface;
120     MOS_RESOURCE      *histogramOutputBuf;
121     MOS_RESOURCE      *fgOutputPicRes;
122     MOS_RESOURCE      *streamInBufRes;
123     MOS_RESOURCE      *streamOutBufRes;
124     uint32_t           streamSize;
125 #endif
126 };
127 
128 struct DecodeStatusMfx
129 {
130     //!< HW requires a QW aligned offset for data storage
131     uint32_t                status = 0;
132     //! \brief Value of MMIO decoding effor eStatus register
133     uint32_t                m_mmioErrorStatusReg = 0;
134     //! \brief Value of MMIO decoding MB error register
135     uint32_t                m_mmioMBCountReg = 0;
136     //! \brief Frame CRC related to current frames
137     uint32_t                m_mmioFrameCrcReg = 0;
138     //! \brief Value of MMIO CS Engine ID register for each BB
139     uint32_t                m_mmioCsEngineIdReg[csInstanceIdMax] = { 0 };
140     //! \brief Huc error for HEVC Fix Function, DWORD0: mask value, DWORD1: reg value
141     uint64_t                m_hucErrorStatus2 = 0;
142     //! \brief Huc error for HEVC Fix Function, DWORD0: mask value, DWORD1: reg value
143     uint64_t                m_hucErrorStatus = 0;
144 };
145 
146 struct DecodeStatusRcs
147 {
148     uint32_t                    status;
149     uint32_t                    pad;        //!< Pad
150 };
151 
152 }
153 
154 #endif