1 /** @file 2 3 Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> 4 5 Redistribution and use in source and binary forms, with or without modification, 6 are permitted provided that the following conditions are met: 7 8 * Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, this 11 list of conditions and the following disclaimer in the documentation and/or 12 other materials provided with the distribution. 13 * Neither the name of Intel Corporation nor the names of its contributors may 14 be used to endorse or promote products derived from this software without 15 specific prior written permission. 16 17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 THE POSSIBILITY OF SUCH DAMAGE. 28 29 This file is automatically generated. Please do NOT modify !!! 30 31 **/ 32 33 #ifndef __DEFS_IIO_H__ 34 #define __DEFS_IIO_H__ 35 36 #include <fsp/api.h> 37 38 #define IIO_MODE_GEN4_ONLY 0 39 #define IIO_MODE_GEN5 1 40 #define IIO_MODE_CXL 2 41 #define IIO_MODE_FORCE_CXL 3 42 #define IIO_MODE_INVALID 0xFF 43 44 #define IIO_BIFURCATE_xxxxxxxx 0xFE 45 #define IIO_BIFURCATE_x4x4x4x4 0x0 46 #define IIO_BIFURCATE_x4x4xxx8 0x1 47 #define IIO_BIFURCATE_xxx8x4x4 0x2 48 #define IIO_BIFURCATE_xxx8xxx8 0x3 49 #define IIO_BIFURCATE_xxxxxx16 0x4 50 #define IIO_BIFURCATE_x2x2x4x8 0x5 51 #define IIO_BIFURCATE_x4x2x2x8 0x6 52 #define IIO_BIFURCATE_x8x2x2x4 0x7 53 #define IIO_BIFURCATE_x8x4x2x2 0x8 54 #define IIO_BIFURCATE_x2x2x4x4x4 0x9 55 #define IIO_BIFURCATE_x4x2x2x4x4 0xA 56 #define IIO_BIFURCATE_x4x4x2x2x4 0xB 57 #define IIO_BIFURCATE_x4x4x4x2x2 0xC 58 #define IIO_BIFURCATE_x2x2x2x2x8 0xD 59 #define IIO_BIFURCATE_x8x2x2x2x2 0xE 60 #define IIO_BIFURCATE_x2x2x2x2x4x4 0xF 61 #define IIO_BIFURCATE_x2x2x4x2x2x4 0x10 62 #define IIO_BIFURCATE_x2x2x4x4x2x2 0x11 63 #define IIO_BIFURCATE_x4x2x2x2x2x4 0x12 64 #define IIO_BIFURCATE_x4x2x2x4x2x2 0x13 65 #define IIO_BIFURCATE_x4x4x2x2x2x2 0x14 66 #define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15 67 #define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16 68 #define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17 69 #define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18 70 #define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19 71 #define IIO_BIFURCATE_AUTO 0xFF 72 73 //------------------------------------------------------------------------------------ 74 // IIO IPs located in extended stacks for SPR program 75 //------------------------------------------------------------------------------------ 76 #define HCX_BUS_RANGE 0x04 77 #define HCB_BUS_RANGE 0x08 78 #define CPM_BUS_OFFSET 0x01 79 #define HQM_BUS_OFFSET 0x03 80 #define CPM1_BUS_OFFSET 0x05 81 #define HQM1_BUS_OFFSET 0x07 82 #define CPM_MMIO_SIZE 0x100000000 // 4G MMIO resource for CPM 83 #define HQM_MMIO_SIZE 0x400000000 // 16G MMIO resource for HQM 84 #define CPM_RESERVED_BUS 0x01 85 #define HQM_RESERVED_BUS 0x01 86 87 #define HCT_BUS_RANGE 0x02 88 #define HCM_BUS_RANGE 0x02 89 #define TIP_BUS_OFFSET 0x01 90 #define VID_BUS_OFFSET 0x01 91 #define TIP_MMIO_SIZE 0x80000 // 512K MMIO resource for TIP 92 #define VID_MMIO_SIZE 0x1000000 // 16MB MMIO resource for VID 93 #define TIP_RESERVED_BUS 0x01 94 #define VID_RESERVED_BUS 0x01 95 96 #pragma pack(1) 97 // It's better to align with UPD_IIO_PCIE_PORT_CONFIG 98 typedef struct { 99 UINT8 SLOTEIP; 100 UINT8 SLOTHPCAP; 101 UINT8 SLOTHPSUP; 102 UINT8 SLOTPIP; 103 UINT8 SLOTAIP; 104 UINT8 SLOTMRLSP; 105 UINT8 SLOTPCP; 106 UINT8 SLOTABP; 107 UINT8 SLOTIMP; 108 UINT8 SLOTSPLS; 109 UINT8 SLOTSPLV; 110 UINT16 SLOTPSP; 111 BOOLEAN VppEnabled; 112 UINT8 VppPort; 113 UINT8 VppAddress; 114 UINT8 MuxAddress; 115 UINT8 ChannelID; 116 UINT8 PciePortEnable; 117 UINT8 PEXPHIDE; 118 UINT8 HidePEXPMenu; 119 UINT8 PciePortOwnership; 120 UINT8 RetimerConnectCount; 121 UINT8 ConfigIOU; 122 UINT8 PcieHotPlugOnPort; 123 UINT8 VMDEnabled; 124 UINT8 VMDPortEnable; 125 UINT8 VMDHotPlugEnable; 126 UINT8 PcieMaxPayload; 127 UINT8 PciePortLinkSpeed; 128 UINT8 DfxDnTxPresetGen3; 129 } UPD_IIO_PCIE_PORT_CONFIG_ENTRY; 130 #pragma pack() 131 132 //------------------------------------------------------------------------------------ 133 // Uncomment line(s) below to override macro definitions in FSP IioUniversalDataHob.h 134 //------------------------------------------------------------------------------------ 135 // #define MAX_SOCKET 4 136 // #define MAX_IMC 4 137 // #define MAX_CH 8 138 // #define MAX_IIO_PORTS_PER_SOCKET 57 139 // #define MAX_IIO_STACK 12 140 141 #endif 142