1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _dma_v2_defs_h 8 #define _dma_v2_defs_h 9 10 #define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels 11 #define _DMA_V2_CONNECTIONS_ID Connections 12 #define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths 13 #define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth 14 #define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat 15 #define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass 16 #define _DMA_V2_DEV_NO_BURST_ID DevNoBurst 17 #define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept 18 #define _DMA_V2_DEV_SRMD_ID DevSRMD 19 #define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters 20 #define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth 21 #define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth 22 #define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat 23 #define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass 24 #define _DMA_V2_NO_PACK_ID has_no_pack 25 26 #define _DMA_V2_REG_ALIGN 4 27 #define _DMA_V2_REG_ADDR_BITS 2 28 29 /* Command word */ 30 #define _DMA_V2_CMD_IDX 0 31 #define _DMA_V2_CMD_BITS 6 32 #define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS) 33 #define _DMA_V2_CHANNEL_BITS 5 34 35 /* The command to set a parameter contains the PARAM field next */ 36 #define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) 37 #define _DMA_V2_PARAM_BITS 4 38 39 /* Commands to read, write or init specific blocks contain these 40 three values */ 41 #define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) 42 #define _DMA_V2_SPEC_DEV_A_XB_BITS 8 43 #define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS) 44 #define _DMA_V2_SPEC_DEV_B_XB_BITS 8 45 #define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS) 46 #define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS) 47 48 /* */ 49 #define _DMA_V2_CMD_CTRL_IDX 4 50 #define _DMA_V2_CMD_CTRL_BITS 4 51 52 /* Packing setup word */ 53 #define _DMA_V2_CONNECTION_IDX 0 54 #define _DMA_V2_CONNECTION_BITS 4 55 #define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS) 56 #define _DMA_V2_EXTENSION_BITS 1 57 58 /* Elements packing word */ 59 #define _DMA_V2_ELEMENTS_IDX 0 60 #define _DMA_V2_ELEMENTS_BITS 8 61 #define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS) 62 #define _DMA_V2_LEFT_CROPPING_BITS 8 63 64 #define _DMA_V2_WIDTH_IDX 0 65 #define _DMA_V2_WIDTH_BITS 16 66 67 #define _DMA_V2_HEIGHT_IDX 0 68 #define _DMA_V2_HEIGHT_BITS 16 69 70 #define _DMA_V2_STRIDE_IDX 0 71 #define _DMA_V2_STRIDE_BITS 32 72 73 /* Command IDs */ 74 #define _DMA_V2_MOVE_B2A_COMMAND 0 75 #define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1 76 #define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2 77 #define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3 78 #define _DMA_V2_MOVE_A2B_COMMAND 4 79 #define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5 80 #define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6 81 #define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7 82 #define _DMA_V2_INIT_A_COMMAND 8 83 #define _DMA_V2_INIT_A_BLOCK_COMMAND 9 84 #define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10 85 #define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11 86 #define _DMA_V2_INIT_B_COMMAND 12 87 #define _DMA_V2_INIT_B_BLOCK_COMMAND 13 88 #define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14 89 #define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15 90 #define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16) 91 #define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16) 92 #define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16) 93 #define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16) 94 #define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16) 95 #define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16) 96 #define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16) 97 #define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16) 98 #define _DMA_V2_CONFIG_CHANNEL_COMMAND 32 99 #define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33 100 #define _DMA_V2_SET_CRUN_COMMAND 62 101 102 /* Channel Parameter IDs */ 103 #define _DMA_V2_PACKING_SETUP_PARAM 0 104 #define _DMA_V2_STRIDE_A_PARAM 1 105 #define _DMA_V2_ELEM_CROPPING_A_PARAM 2 106 #define _DMA_V2_WIDTH_A_PARAM 3 107 #define _DMA_V2_STRIDE_B_PARAM 4 108 #define _DMA_V2_ELEM_CROPPING_B_PARAM 5 109 #define _DMA_V2_WIDTH_B_PARAM 6 110 #define _DMA_V2_HEIGHT_PARAM 7 111 #define _DMA_V2_QUEUED_CMDS 8 112 113 /* Parameter Constants */ 114 #define _DMA_V2_ZERO_EXTEND 0 115 #define _DMA_V2_SIGN_EXTEND 1 116 117 /* SLAVE address map */ 118 #define _DMA_V2_SEL_FSM_CMD 0 119 #define _DMA_V2_SEL_CH_REG 1 120 #define _DMA_V2_SEL_CONN_GROUP 2 121 #define _DMA_V2_SEL_DEV_INTERF 3 122 123 #define _DMA_V2_ADDR_SEL_COMP_IDX 12 124 #define _DMA_V2_ADDR_SEL_COMP_BITS 4 125 #define _DMA_V2_ADDR_SEL_CH_REG_IDX 2 126 #define _DMA_V2_ADDR_SEL_CH_REG_BITS 6 127 #define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX) 128 #define _DMA_V2_ADDR_SEL_PARAM_BITS 4 129 130 #define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2 131 #define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6 132 #define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX) 133 #define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4 134 135 #define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2 136 #define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6 137 #define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS) 138 #define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4 139 140 #define _DMA_V2_FSM_GROUP_CMD_IDX 0 141 #define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1 142 #define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2 143 #define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3 144 #define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4 145 #define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5 146 #define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6 147 #define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7 148 149 #define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0 150 #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1 151 #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2 152 #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3 153 #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4 154 #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5 155 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6 156 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7 157 #define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8 158 #define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9 159 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10 160 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11 161 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12 162 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13 163 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14 164 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15 165 #define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15 166 167 #define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0 168 #define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1 169 #define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2 170 #define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3 171 172 #define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0 173 #define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1 174 #define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2 175 #define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3 176 #define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4 177 178 #define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0 179 #define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1 180 #define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2 181 #define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3 182 #define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4 183 184 #define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0 185 #define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1 186 #define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2 187 #define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3 188 #define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4 189 #define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5 190 191 #endif /* _dma_v2_defs_h */ 192