1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ 3 4 #ifndef _DR_STE_V1_ 5 #define _DR_STE_V1_ 6 7 #include "dr_types.h" 8 #include "dr_ste.h" 9 10 #define DR_STE_DECAP_L3_ACTION_NUM 8 11 #define DR_STE_L2_HDR_MAX_SZ 20 12 #define DR_STE_CALC_DFNR_TYPE(lookup_type, inner) \ 13 ((inner) ? DR_STE_V1_LU_TYPE_##lookup_type##_I : \ 14 DR_STE_V1_LU_TYPE_##lookup_type##_O) 15 16 enum dr_ste_v1_entry_format { 17 DR_STE_V1_TYPE_BWC_BYTE = 0x0, 18 DR_STE_V1_TYPE_BWC_DW = 0x1, 19 DR_STE_V1_TYPE_MATCH = 0x2, 20 DR_STE_V1_TYPE_MATCH_RANGES = 0x7, 21 }; 22 23 /* Lookup type is built from 2B: [ Definer mode 1B ][ Definer index 1B ] */ 24 enum { 25 DR_STE_V1_LU_TYPE_NOP = 0x0000, 26 DR_STE_V1_LU_TYPE_ETHL2_TNL = 0x0002, 27 DR_STE_V1_LU_TYPE_IBL3_EXT = 0x0102, 28 DR_STE_V1_LU_TYPE_ETHL2_O = 0x0003, 29 DR_STE_V1_LU_TYPE_IBL4 = 0x0103, 30 DR_STE_V1_LU_TYPE_ETHL2_I = 0x0004, 31 DR_STE_V1_LU_TYPE_SRC_QP_GVMI = 0x0104, 32 DR_STE_V1_LU_TYPE_ETHL2_SRC_O = 0x0005, 33 DR_STE_V1_LU_TYPE_ETHL2_HEADERS_O = 0x0105, 34 DR_STE_V1_LU_TYPE_ETHL2_SRC_I = 0x0006, 35 DR_STE_V1_LU_TYPE_ETHL2_HEADERS_I = 0x0106, 36 DR_STE_V1_LU_TYPE_ETHL3_IPV4_5_TUPLE_O = 0x0007, 37 DR_STE_V1_LU_TYPE_IPV6_DES_O = 0x0107, 38 DR_STE_V1_LU_TYPE_ETHL3_IPV4_5_TUPLE_I = 0x0008, 39 DR_STE_V1_LU_TYPE_IPV6_DES_I = 0x0108, 40 DR_STE_V1_LU_TYPE_ETHL4_O = 0x0009, 41 DR_STE_V1_LU_TYPE_IPV6_SRC_O = 0x0109, 42 DR_STE_V1_LU_TYPE_ETHL4_I = 0x000a, 43 DR_STE_V1_LU_TYPE_IPV6_SRC_I = 0x010a, 44 DR_STE_V1_LU_TYPE_ETHL2_SRC_DST_O = 0x000b, 45 DR_STE_V1_LU_TYPE_MPLS_O = 0x010b, 46 DR_STE_V1_LU_TYPE_ETHL2_SRC_DST_I = 0x000c, 47 DR_STE_V1_LU_TYPE_MPLS_I = 0x010c, 48 DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_O = 0x000d, 49 DR_STE_V1_LU_TYPE_GRE = 0x010d, 50 DR_STE_V1_LU_TYPE_FLEX_PARSER_TNL_HEADER = 0x000e, 51 DR_STE_V1_LU_TYPE_GENERAL_PURPOSE = 0x010e, 52 DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_I = 0x000f, 53 DR_STE_V1_LU_TYPE_STEERING_REGISTERS_0 = 0x010f, 54 DR_STE_V1_LU_TYPE_STEERING_REGISTERS_1 = 0x0110, 55 DR_STE_V1_LU_TYPE_FLEX_PARSER_OK = 0x0011, 56 DR_STE_V1_LU_TYPE_FLEX_PARSER_0 = 0x0111, 57 DR_STE_V1_LU_TYPE_FLEX_PARSER_1 = 0x0112, 58 DR_STE_V1_LU_TYPE_ETHL4_MISC_O = 0x0113, 59 DR_STE_V1_LU_TYPE_ETHL4_MISC_I = 0x0114, 60 DR_STE_V1_LU_TYPE_INVALID = 0x00ff, 61 DR_STE_V1_LU_TYPE_DONT_CARE = MLX5DR_STE_LU_TYPE_DONT_CARE, 62 }; 63 64 enum dr_ste_v1_header_anchors { 65 DR_STE_HEADER_ANCHOR_START_OUTER = 0x00, 66 DR_STE_HEADER_ANCHOR_1ST_VLAN = 0x02, 67 DR_STE_HEADER_ANCHOR_IPV6_IPV4 = 0x07, 68 DR_STE_HEADER_ANCHOR_INNER_MAC = 0x13, 69 DR_STE_HEADER_ANCHOR_INNER_IPV6_IPV4 = 0x19, 70 }; 71 72 enum dr_ste_v1_action_size { 73 DR_STE_ACTION_SINGLE_SZ = 4, 74 DR_STE_ACTION_DOUBLE_SZ = 8, 75 DR_STE_ACTION_TRIPLE_SZ = 12, 76 }; 77 78 enum dr_ste_v1_action_insert_ptr_attr { 79 DR_STE_V1_ACTION_INSERT_PTR_ATTR_NONE = 0, /* Regular push header (e.g. push vlan) */ 80 DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP = 1, /* Encapsulation / Tunneling */ 81 DR_STE_V1_ACTION_INSERT_PTR_ATTR_ESP = 2, /* IPsec */ 82 }; 83 84 enum dr_ste_v1_action_id { 85 DR_STE_V1_ACTION_ID_NOP = 0x00, 86 DR_STE_V1_ACTION_ID_COPY = 0x05, 87 DR_STE_V1_ACTION_ID_SET = 0x06, 88 DR_STE_V1_ACTION_ID_ADD = 0x07, 89 DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE = 0x08, 90 DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER = 0x09, 91 DR_STE_V1_ACTION_ID_INSERT_INLINE = 0x0a, 92 DR_STE_V1_ACTION_ID_INSERT_POINTER = 0x0b, 93 DR_STE_V1_ACTION_ID_FLOW_TAG = 0x0c, 94 DR_STE_V1_ACTION_ID_QUEUE_ID_SEL = 0x0d, 95 DR_STE_V1_ACTION_ID_ACCELERATED_LIST = 0x0e, 96 DR_STE_V1_ACTION_ID_MODIFY_LIST = 0x0f, 97 DR_STE_V1_ACTION_ID_ASO = 0x12, 98 DR_STE_V1_ACTION_ID_TRAILER = 0x13, 99 DR_STE_V1_ACTION_ID_COUNTER_ID = 0x14, 100 DR_STE_V1_ACTION_ID_MAX = 0x21, 101 /* use for special cases */ 102 DR_STE_V1_ACTION_ID_SPECIAL_ENCAP_L3 = 0x22, 103 }; 104 105 enum { 106 DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_0 = 0x00, 107 DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_1 = 0x01, 108 DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_2 = 0x02, 109 DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_0 = 0x08, 110 DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_1 = 0x09, 111 DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0 = 0x0e, 112 DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0 = 0x18, 113 DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_1 = 0x19, 114 DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_0 = 0x40, 115 DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_1 = 0x41, 116 DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_0 = 0x44, 117 DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_1 = 0x45, 118 DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_2 = 0x46, 119 DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_3 = 0x47, 120 DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_0 = 0x4c, 121 DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_1 = 0x4d, 122 DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_2 = 0x4e, 123 DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_3 = 0x4f, 124 DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_0 = 0x5e, 125 DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_1 = 0x5f, 126 DR_STE_V1_ACTION_MDFY_FLD_CFG_HDR_0_0 = 0x6f, 127 DR_STE_V1_ACTION_MDFY_FLD_CFG_HDR_0_1 = 0x70, 128 DR_STE_V1_ACTION_MDFY_FLD_METADATA_2_CQE = 0x7b, 129 DR_STE_V1_ACTION_MDFY_FLD_GNRL_PURPOSE = 0x7c, 130 DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2_0 = 0x8c, 131 DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2_1 = 0x8d, 132 DR_STE_V1_ACTION_MDFY_FLD_REGISTER_1_0 = 0x8e, 133 DR_STE_V1_ACTION_MDFY_FLD_REGISTER_1_1 = 0x8f, 134 DR_STE_V1_ACTION_MDFY_FLD_REGISTER_0_0 = 0x90, 135 DR_STE_V1_ACTION_MDFY_FLD_REGISTER_0_1 = 0x91, 136 }; 137 138 enum dr_ste_v1_aso_ctx_type { 139 DR_STE_V1_ASO_CTX_TYPE_POLICERS = 0x2, 140 }; 141 142 bool dr_ste_v1_is_miss_addr_set(u8 *hw_ste_p); 143 void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr); 144 u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p); 145 void dr_ste_v1_set_byte_mask(u8 *hw_ste_p, u16 byte_mask); 146 u16 dr_ste_v1_get_byte_mask(u8 *hw_ste_p); 147 void dr_ste_v1_set_next_lu_type(u8 *hw_ste_p, u16 lu_type); 148 u16 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p); 149 void dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size); 150 void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type, bool is_rx, u16 gvmi); 151 void dr_ste_v1_prepare_for_postsend(u8 *hw_ste_p, u32 ste_size); 152 void dr_ste_v1_set_reparse(u8 *hw_ste_p); 153 void dr_ste_v1_set_encap(u8 *hw_ste_p, u8 *d_action, u32 reformat_id, int size); 154 void dr_ste_v1_set_push_vlan(u8 *hw_ste_p, u8 *d_action, u32 vlan_hdr); 155 void dr_ste_v1_set_pop_vlan(u8 *hw_ste_p, u8 *s_action, u8 vlans_num); 156 void dr_ste_v1_set_encap_l3(u8 *hw_ste_p, u8 *frst_s_action, u8 *scnd_d_action, 157 u32 reformat_id, int size); 158 void dr_ste_v1_set_rx_decap(u8 *hw_ste_p, u8 *s_action); 159 void dr_ste_v1_set_insert_hdr(u8 *hw_ste_p, u8 *d_action, u32 reformat_id, 160 u8 anchor, u8 offset, int size); 161 void dr_ste_v1_set_remove_hdr(u8 *hw_ste_p, u8 *s_action, u8 anchor, 162 u8 offset, int size); 163 void dr_ste_v1_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx, struct mlx5dr_domain *dmn, 164 u8 *action_type_set, u32 actions_caps, u8 *last_ste, 165 struct mlx5dr_ste_actions_attr *attr, u32 *added_stes); 166 void dr_ste_v1_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx, struct mlx5dr_domain *dmn, 167 u8 *action_type_set, u32 actions_caps, u8 *last_ste, 168 struct mlx5dr_ste_actions_attr *attr, u32 *added_stes); 169 void dr_ste_v1_set_action_set(u8 *d_action, u8 hw_field, u8 shifter, 170 u8 length, u32 data); 171 void dr_ste_v1_set_action_add(u8 *d_action, u8 hw_field, u8 shifter, 172 u8 length, u32 data); 173 void dr_ste_v1_set_action_copy(u8 *d_action, u8 dst_hw_field, u8 dst_shifter, 174 u8 dst_len, u8 src_hw_field, u8 src_shifter); 175 int dr_ste_v1_set_action_decap_l3_list(void *data, u32 data_sz, u8 *hw_action, 176 u32 hw_action_sz, u16 *used_hw_action_num); 177 int dr_ste_v1_alloc_modify_hdr_ptrn_arg(struct mlx5dr_action *action); 178 void dr_ste_v1_free_modify_hdr_ptrn_arg(struct mlx5dr_action *action); 179 void dr_ste_v1_build_eth_l2_src_dst_init(struct mlx5dr_ste_build *sb, 180 struct mlx5dr_match_param *mask); 181 void dr_ste_v1_build_eth_l3_ipv6_dst_init(struct mlx5dr_ste_build *sb, 182 struct mlx5dr_match_param *mask); 183 void dr_ste_v1_build_eth_l3_ipv6_src_init(struct mlx5dr_ste_build *sb, 184 struct mlx5dr_match_param *mask); 185 void dr_ste_v1_build_eth_l3_ipv4_5_tuple_init(struct mlx5dr_ste_build *sb, 186 struct mlx5dr_match_param *mask); 187 void dr_ste_v1_build_eth_l2_src_init(struct mlx5dr_ste_build *sb, 188 struct mlx5dr_match_param *mask); 189 void dr_ste_v1_build_eth_l2_dst_init(struct mlx5dr_ste_build *sb, 190 struct mlx5dr_match_param *mask); 191 void dr_ste_v1_build_eth_l2_tnl_init(struct mlx5dr_ste_build *sb, 192 struct mlx5dr_match_param *mask); 193 void dr_ste_v1_build_eth_l3_ipv4_misc_init(struct mlx5dr_ste_build *sb, 194 struct mlx5dr_match_param *mask); 195 void dr_ste_v1_build_eth_ipv6_l3_l4_init(struct mlx5dr_ste_build *sb, 196 struct mlx5dr_match_param *mask); 197 void dr_ste_v1_build_mpls_init(struct mlx5dr_ste_build *sb, 198 struct mlx5dr_match_param *mask); 199 void dr_ste_v1_build_tnl_gre_init(struct mlx5dr_ste_build *sb, 200 struct mlx5dr_match_param *mask); 201 void dr_ste_v1_build_tnl_mpls_init(struct mlx5dr_ste_build *sb, 202 struct mlx5dr_match_param *mask); 203 void dr_ste_v1_build_tnl_mpls_over_udp_init(struct mlx5dr_ste_build *sb, 204 struct mlx5dr_match_param *mask); 205 void dr_ste_v1_build_tnl_mpls_over_gre_init(struct mlx5dr_ste_build *sb, 206 struct mlx5dr_match_param *mask); 207 void dr_ste_v1_build_icmp_init(struct mlx5dr_ste_build *sb, 208 struct mlx5dr_match_param *mask); 209 void dr_ste_v1_build_general_purpose_init(struct mlx5dr_ste_build *sb, 210 struct mlx5dr_match_param *mask); 211 void dr_ste_v1_build_eth_l4_misc_init(struct mlx5dr_ste_build *sb, 212 struct mlx5dr_match_param *mask); 213 void dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init(struct mlx5dr_ste_build *sb, 214 struct mlx5dr_match_param *mask); 215 void dr_ste_v1_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb, 216 struct mlx5dr_match_param *mask); 217 void dr_ste_v1_build_tnl_header_0_1_init(struct mlx5dr_ste_build *sb, 218 struct mlx5dr_match_param *mask); 219 void dr_ste_v1_build_register_0_init(struct mlx5dr_ste_build *sb, 220 struct mlx5dr_match_param *mask); 221 void dr_ste_v1_build_register_1_init(struct mlx5dr_ste_build *sb, 222 struct mlx5dr_match_param *mask); 223 void dr_ste_v1_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb, 224 struct mlx5dr_match_param *mask); 225 void dr_ste_v1_build_flex_parser_0_init(struct mlx5dr_ste_build *sb, 226 struct mlx5dr_match_param *mask); 227 void dr_ste_v1_build_flex_parser_1_init(struct mlx5dr_ste_build *sb, 228 struct mlx5dr_match_param *mask); 229 void dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init(struct mlx5dr_ste_build *sb, 230 struct mlx5dr_match_param *mask); 231 void dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init(struct mlx5dr_ste_build *sb, 232 struct mlx5dr_match_param *mask); 233 void dr_ste_v1_build_flex_parser_tnl_gtpu_init(struct mlx5dr_ste_build *sb, 234 struct mlx5dr_match_param *mask); 235 void dr_ste_v1_build_tnl_gtpu_flex_parser_0_init(struct mlx5dr_ste_build *sb, 236 struct mlx5dr_match_param *mask); 237 void dr_ste_v1_build_tnl_gtpu_flex_parser_1_init(struct mlx5dr_ste_build *sb, 238 struct mlx5dr_match_param *mask); 239 240 #endif /* _DR_STE_V1_ */ 241