1 /***********************license start*********************************** 2 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * This Software, including technical data, may be subject to U.S. export 24 * control laws, including the U.S. Export Administration Act and its 25 * associated regulations, and may be subject to export or import 26 * regulations in other countries. 27 * 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT 31 * TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 32 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 33 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 34 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 35 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, 36 * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK 37 * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 /** 41 * Function for DDR3 init. Internal use only. 42 */ 43 44 extern void perform_octeon3_ddr3_sequence(bdk_node_t node, int rank_mask, 45 int ddr_interface_num, int sequence); 46 extern void perform_ddr_init_sequence(bdk_node_t node, int rank_mask, 47 int ddr_interface_num); 48 extern int ddr_memory_preserved(bdk_node_t node); 49 50 extern int init_octeon3_ddr3_interface(bdk_node_t node, 51 const ddr_configuration_t *ddr_configuration, uint32_t ddr_hertz, 52 uint32_t cpu_hertz, uint32_t ddr_ref_hertz, int board_type, 53 int board_rev_maj, int board_rev_min, int ddr_interface_num, 54 uint32_t ddr_interface_mask); 55 56 extern void 57 set_vref(bdk_node_t node, int ddr_interface_num, int rank, 58 int range, int value); 59 60 typedef struct { 61 unsigned char *rodt_ohms; 62 unsigned char *rtt_nom_ohms; 63 unsigned char *rtt_nom_table; 64 unsigned char *rtt_wr_ohms; 65 unsigned char *dic_ohms; 66 short *drive_strength; 67 short *dqx_strength; 68 } impedence_values_t; 69 70 extern impedence_values_t ddr4_impedence_values; 71 72 extern int 73 compute_vref_value(bdk_node_t node, int ddr_interface_num, 74 int rankx, int dimm_count, int rank_count, 75 impedence_values_t *imp_values, int is_stacked_die); 76 77 extern unsigned short 78 load_dac_override(int node, int ddr_interface_num, 79 int dac_value, int byte); 80 extern int 81 read_DAC_DBI_settings(int node, int ddr_interface_num, 82 int dac_or_dbi, int *settings); 83 extern void 84 display_DAC_DBI_settings(int node, int ddr_interface_num, int dac_or_dbi, 85 int ecc_ena, int *settings, const char *title); 86 87 #define RODT_OHMS_COUNT 8 88 #define RTT_NOM_OHMS_COUNT 8 89 #define RTT_NOM_TABLE_COUNT 8 90 #define RTT_WR_OHMS_COUNT 8 91 #define DIC_OHMS_COUNT 3 92 #define DRIVE_STRENGTH_COUNT 15 93 94 extern uint64_t hertz_to_psecs(uint64_t hertz); 95 extern uint64_t psecs_to_mts(uint64_t psecs); 96 extern uint64_t mts_to_hertz(uint64_t mts); 97 //extern uint64_t pretty_psecs_to_mts(uint64_t psecs); 98 extern unsigned long pretty_psecs_to_mts(uint64_t psecs); /* FIXME(dhendrix) */ 99