1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip AXI PCIe Bridge host controller driver
4 *
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
6 *
7 * Author: Daire McNamara <[email protected]>
8 */
9
10 #include <linux/align.h>
11 #include <linux/bits.h>
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/log2.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci-ecam.h>
22 #include <linux/platform_device.h>
23 #include <linux/wordpart.h>
24
25 #include "../../pci.h"
26 #include "pcie-plda.h"
27
28 #define MC_MAX_NUM_INBOUND_WINDOWS 8
29 #define MPFS_NC_BOUNCE_ADDR 0x80000000
30
31 /* PCIe Bridge Phy and Controller Phy offsets */
32 #define MC_PCIE1_BRIDGE_ADDR 0x00008000u
33 #define MC_PCIE1_CTRL_ADDR 0x0000a000u
34
35 /* PCIe Controller Phy Regs */
36 #define SEC_ERROR_EVENT_CNT 0x20
37 #define DED_ERROR_EVENT_CNT 0x24
38 #define SEC_ERROR_INT 0x28
39 #define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0)
40 #define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4)
41 #define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8)
42 #define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12)
43 #define SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT GENMASK(15, 0)
44 #define NUM_SEC_ERROR_INTS (4)
45 #define SEC_ERROR_INT_MASK 0x2c
46 #define DED_ERROR_INT 0x30
47 #define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0)
48 #define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4)
49 #define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8)
50 #define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12)
51 #define DED_ERROR_INT_ALL_RAM_DED_ERR_INT GENMASK(15, 0)
52 #define NUM_DED_ERROR_INTS (4)
53 #define DED_ERROR_INT_MASK 0x34
54 #define ECC_CONTROL 0x38
55 #define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0)
56 #define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1)
57 #define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2)
58 #define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3)
59 #define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4)
60 #define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5)
61 #define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6)
62 #define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7)
63 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8)
64 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9)
65 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10)
66 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11)
67 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12)
68 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13)
69 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14)
70 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15)
71 #define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24)
72 #define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25)
73 #define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26)
74 #define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27)
75 #define PCIE_EVENT_INT 0x14c
76 #define PCIE_EVENT_INT_L2_EXIT_INT BIT(0)
77 #define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1)
78 #define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2)
79 #define PCIE_EVENT_INT_MASK GENMASK(2, 0)
80 #define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16)
81 #define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17)
82 #define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18)
83 #define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16)
84 #define PCIE_EVENT_INT_ENB_SHIFT 16
85 #define NUM_PCIE_EVENTS (3)
86
87 /* PCIe Config space MSI capability structure */
88 #define MC_MSI_CAP_CTRL_OFFSET 0xe0u
89
90 /* Events */
91 #define EVENT_PCIE_L2_EXIT 0
92 #define EVENT_PCIE_HOTRST_EXIT 1
93 #define EVENT_PCIE_DLUP_EXIT 2
94 #define EVENT_SEC_TX_RAM_SEC_ERR 3
95 #define EVENT_SEC_RX_RAM_SEC_ERR 4
96 #define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5
97 #define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6
98 #define EVENT_DED_TX_RAM_DED_ERR 7
99 #define EVENT_DED_RX_RAM_DED_ERR 8
100 #define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9
101 #define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10
102 #define EVENT_LOCAL_DMA_END_ENGINE_0 11
103 #define EVENT_LOCAL_DMA_END_ENGINE_1 12
104 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13
105 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14
106 #define NUM_MC_EVENTS 15
107 #define EVENT_LOCAL_A_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_AXI_POST_ERR)
108 #define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_AXI_FETCH_ERR)
109 #define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_AXI_DISCARD_ERR)
110 #define EVENT_LOCAL_A_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_AXI_DOORBELL)
111 #define EVENT_LOCAL_P_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_PCIE_POST_ERR)
112 #define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_PCIE_FETCH_ERR)
113 #define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_PCIE_DISCARD_ERR)
114 #define EVENT_LOCAL_P_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_PCIE_DOORBELL)
115 #define EVENT_LOCAL_PM_MSI_INT_INTX (NUM_MC_EVENTS + PLDA_INTX)
116 #define EVENT_LOCAL_PM_MSI_INT_MSI (NUM_MC_EVENTS + PLDA_MSI)
117 #define EVENT_LOCAL_PM_MSI_INT_AER_EVT (NUM_MC_EVENTS + PLDA_AER_EVENT)
118 #define EVENT_LOCAL_PM_MSI_INT_EVENTS (NUM_MC_EVENTS + PLDA_MISC_EVENTS)
119 #define EVENT_LOCAL_PM_MSI_INT_SYS_ERR (NUM_MC_EVENTS + PLDA_SYS_ERR)
120 #define NUM_EVENTS (NUM_MC_EVENTS + PLDA_INT_EVENT_NUM)
121
122 #define PCIE_EVENT_CAUSE(x, s) \
123 [EVENT_PCIE_ ## x] = { __stringify(x), s }
124
125 #define SEC_ERROR_CAUSE(x, s) \
126 [EVENT_SEC_ ## x] = { __stringify(x), s }
127
128 #define DED_ERROR_CAUSE(x, s) \
129 [EVENT_DED_ ## x] = { __stringify(x), s }
130
131 #define LOCAL_EVENT_CAUSE(x, s) \
132 [EVENT_LOCAL_ ## x] = { __stringify(x), s }
133
134 #define PCIE_EVENT(x) \
135 .offset = PCIE_EVENT_INT, \
136 .mask_offset = PCIE_EVENT_INT, \
137 .mask_high = 1, \
138 .mask = PCIE_EVENT_INT_ ## x ## _INT, \
139 .enb_mask = PCIE_EVENT_INT_ENB_MASK
140
141 #define SEC_EVENT(x) \
142 .offset = SEC_ERROR_INT, \
143 .mask_offset = SEC_ERROR_INT_MASK, \
144 .mask = SEC_ERROR_INT_ ## x ## _INT, \
145 .mask_high = 1, \
146 .enb_mask = 0
147
148 #define DED_EVENT(x) \
149 .offset = DED_ERROR_INT, \
150 .mask_offset = DED_ERROR_INT_MASK, \
151 .mask_high = 1, \
152 .mask = DED_ERROR_INT_ ## x ## _INT, \
153 .enb_mask = 0
154
155 #define LOCAL_EVENT(x) \
156 .offset = ISTATUS_LOCAL, \
157 .mask_offset = IMASK_LOCAL, \
158 .mask_high = 0, \
159 .mask = x ## _MASK, \
160 .enb_mask = 0
161
162 #define PCIE_EVENT_TO_EVENT_MAP(x) \
163 { PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x }
164
165 #define SEC_ERROR_TO_EVENT_MAP(x) \
166 { SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x }
167
168 #define DED_ERROR_TO_EVENT_MAP(x) \
169 { DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x }
170
171 #define LOCAL_STATUS_TO_EVENT_MAP(x) \
172 { x ## _MASK, EVENT_LOCAL_ ## x }
173
174 struct event_map {
175 u32 reg_mask;
176 u32 event_bit;
177 };
178
179
180 struct mc_pcie {
181 struct plda_pcie_rp plda;
182 void __iomem *bridge_base_addr;
183 void __iomem *ctrl_base_addr;
184 };
185
186 struct cause {
187 const char *sym;
188 const char *str;
189 };
190
191 static const struct cause event_cause[NUM_EVENTS] = {
192 PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"),
193 PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"),
194 PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"),
195 SEC_ERROR_CAUSE(TX_RAM_SEC_ERR, "sec error in tx buffer"),
196 SEC_ERROR_CAUSE(RX_RAM_SEC_ERR, "sec error in rx buffer"),
197 SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR, "sec error in pcie2axi buffer"),
198 SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR, "sec error in axi2pcie buffer"),
199 DED_ERROR_CAUSE(TX_RAM_DED_ERR, "ded error in tx buffer"),
200 DED_ERROR_CAUSE(RX_RAM_DED_ERR, "ded error in rx buffer"),
201 DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR, "ded error in pcie2axi buffer"),
202 DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR, "ded error in axi2pcie buffer"),
203 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"),
204 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"),
205 LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"),
206 LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"),
207 LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"),
208 LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"),
209 LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"),
210 LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"),
211 LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"),
212 LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"),
213 LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"),
214 };
215
216 static struct event_map pcie_event_to_event[] = {
217 PCIE_EVENT_TO_EVENT_MAP(L2_EXIT),
218 PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT),
219 PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT),
220 };
221
222 static struct event_map sec_error_to_event[] = {
223 SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR),
224 SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR),
225 SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR),
226 SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR),
227 };
228
229 static struct event_map ded_error_to_event[] = {
230 DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR),
231 DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR),
232 DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR),
233 DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR),
234 };
235
236 static struct event_map local_status_to_event[] = {
237 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0),
238 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1),
239 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0),
240 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1),
241 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR),
242 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR),
243 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR),
244 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL),
245 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR),
246 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR),
247 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR),
248 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL),
249 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX),
250 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI),
251 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT),
252 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS),
253 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR),
254 };
255
256 static struct {
257 u32 offset;
258 u32 mask;
259 u32 shift;
260 u32 enb_mask;
261 u32 mask_high;
262 u32 mask_offset;
263 } event_descs[] = {
264 { PCIE_EVENT(L2_EXIT) },
265 { PCIE_EVENT(HOTRST_EXIT) },
266 { PCIE_EVENT(DLUP_EXIT) },
267 { SEC_EVENT(TX_RAM_SEC_ERR) },
268 { SEC_EVENT(RX_RAM_SEC_ERR) },
269 { SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) },
270 { SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) },
271 { DED_EVENT(TX_RAM_DED_ERR) },
272 { DED_EVENT(RX_RAM_DED_ERR) },
273 { DED_EVENT(PCIE2AXI_RAM_DED_ERR) },
274 { DED_EVENT(AXI2PCIE_RAM_DED_ERR) },
275 { LOCAL_EVENT(DMA_END_ENGINE_0) },
276 { LOCAL_EVENT(DMA_END_ENGINE_1) },
277 { LOCAL_EVENT(DMA_ERROR_ENGINE_0) },
278 { LOCAL_EVENT(DMA_ERROR_ENGINE_1) },
279 { LOCAL_EVENT(A_ATR_EVT_POST_ERR) },
280 { LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) },
281 { LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) },
282 { LOCAL_EVENT(A_ATR_EVT_DOORBELL) },
283 { LOCAL_EVENT(P_ATR_EVT_POST_ERR) },
284 { LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) },
285 { LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) },
286 { LOCAL_EVENT(P_ATR_EVT_DOORBELL) },
287 { LOCAL_EVENT(PM_MSI_INT_INTX) },
288 { LOCAL_EVENT(PM_MSI_INT_MSI) },
289 { LOCAL_EVENT(PM_MSI_INT_AER_EVT) },
290 { LOCAL_EVENT(PM_MSI_INT_EVENTS) },
291 { LOCAL_EVENT(PM_MSI_INT_SYS_ERR) },
292 };
293
294 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" };
295
296 static struct mc_pcie *port;
297
mc_pcie_enable_msi(struct mc_pcie * port,void __iomem * ecam)298 static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam)
299 {
300 struct plda_msi *msi = &port->plda.msi;
301 u16 reg;
302 u8 queue_size;
303
304 /* Fixup MSI enable flag */
305 reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
306 reg |= PCI_MSI_FLAGS_ENABLE;
307 writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
308
309 /* Fixup PCI MSI queue flags */
310 queue_size = FIELD_GET(PCI_MSI_FLAGS_QMASK, reg);
311 reg |= FIELD_PREP(PCI_MSI_FLAGS_QSIZE, queue_size);
312 writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS);
313
314 /* Fixup MSI addr fields */
315 writel_relaxed(lower_32_bits(msi->vector_phy),
316 ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_LO);
317 writel_relaxed(upper_32_bits(msi->vector_phy),
318 ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI);
319 }
320
reg_to_event(u32 reg,struct event_map field)321 static inline u32 reg_to_event(u32 reg, struct event_map field)
322 {
323 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0;
324 }
325
pcie_events(struct mc_pcie * port)326 static u32 pcie_events(struct mc_pcie *port)
327 {
328 u32 reg = readl_relaxed(port->ctrl_base_addr + PCIE_EVENT_INT);
329 u32 val = 0;
330 int i;
331
332 for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++)
333 val |= reg_to_event(reg, pcie_event_to_event[i]);
334
335 return val;
336 }
337
sec_errors(struct mc_pcie * port)338 static u32 sec_errors(struct mc_pcie *port)
339 {
340 u32 reg = readl_relaxed(port->ctrl_base_addr + SEC_ERROR_INT);
341 u32 val = 0;
342 int i;
343
344 for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++)
345 val |= reg_to_event(reg, sec_error_to_event[i]);
346
347 return val;
348 }
349
ded_errors(struct mc_pcie * port)350 static u32 ded_errors(struct mc_pcie *port)
351 {
352 u32 reg = readl_relaxed(port->ctrl_base_addr + DED_ERROR_INT);
353 u32 val = 0;
354 int i;
355
356 for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++)
357 val |= reg_to_event(reg, ded_error_to_event[i]);
358
359 return val;
360 }
361
local_events(struct mc_pcie * port)362 static u32 local_events(struct mc_pcie *port)
363 {
364 u32 reg = readl_relaxed(port->bridge_base_addr + ISTATUS_LOCAL);
365 u32 val = 0;
366 int i;
367
368 for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++)
369 val |= reg_to_event(reg, local_status_to_event[i]);
370
371 return val;
372 }
373
mc_get_events(struct plda_pcie_rp * port)374 static u32 mc_get_events(struct plda_pcie_rp *port)
375 {
376 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda);
377 u32 events = 0;
378
379 events |= pcie_events(mc_port);
380 events |= sec_errors(mc_port);
381 events |= ded_errors(mc_port);
382 events |= local_events(mc_port);
383
384 return events;
385 }
386
mc_event_handler(int irq,void * dev_id)387 static irqreturn_t mc_event_handler(int irq, void *dev_id)
388 {
389 struct plda_pcie_rp *port = dev_id;
390 struct device *dev = port->dev;
391 struct irq_data *data;
392
393 data = irq_domain_get_irq_data(port->event_domain, irq);
394
395 if (event_cause[data->hwirq].str)
396 dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str);
397 else
398 dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq);
399
400 return IRQ_HANDLED;
401 }
402
mc_ack_event_irq(struct irq_data * data)403 static void mc_ack_event_irq(struct irq_data *data)
404 {
405 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
406 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda);
407 u32 event = data->hwirq;
408 void __iomem *addr;
409 u32 mask;
410
411 if (event_descs[event].offset == ISTATUS_LOCAL)
412 addr = mc_port->bridge_base_addr;
413 else
414 addr = mc_port->ctrl_base_addr;
415
416 addr += event_descs[event].offset;
417 mask = event_descs[event].mask;
418 mask |= event_descs[event].enb_mask;
419
420 writel_relaxed(mask, addr);
421 }
422
mc_mask_event_irq(struct irq_data * data)423 static void mc_mask_event_irq(struct irq_data *data)
424 {
425 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
426 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda);
427 u32 event = data->hwirq;
428 void __iomem *addr;
429 u32 mask;
430 u32 val;
431
432 if (event_descs[event].offset == ISTATUS_LOCAL)
433 addr = mc_port->bridge_base_addr;
434 else
435 addr = mc_port->ctrl_base_addr;
436
437 addr += event_descs[event].mask_offset;
438 mask = event_descs[event].mask;
439 if (event_descs[event].enb_mask) {
440 mask <<= PCIE_EVENT_INT_ENB_SHIFT;
441 mask &= PCIE_EVENT_INT_ENB_MASK;
442 }
443
444 if (!event_descs[event].mask_high)
445 mask = ~mask;
446
447 raw_spin_lock(&port->lock);
448 val = readl_relaxed(addr);
449 if (event_descs[event].mask_high)
450 val |= mask;
451 else
452 val &= mask;
453
454 writel_relaxed(val, addr);
455 raw_spin_unlock(&port->lock);
456 }
457
mc_unmask_event_irq(struct irq_data * data)458 static void mc_unmask_event_irq(struct irq_data *data)
459 {
460 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
461 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda);
462 u32 event = data->hwirq;
463 void __iomem *addr;
464 u32 mask;
465 u32 val;
466
467 if (event_descs[event].offset == ISTATUS_LOCAL)
468 addr = mc_port->bridge_base_addr;
469 else
470 addr = mc_port->ctrl_base_addr;
471
472 addr += event_descs[event].mask_offset;
473 mask = event_descs[event].mask;
474
475 if (event_descs[event].enb_mask)
476 mask <<= PCIE_EVENT_INT_ENB_SHIFT;
477
478 if (event_descs[event].mask_high)
479 mask = ~mask;
480
481 if (event_descs[event].enb_mask)
482 mask &= PCIE_EVENT_INT_ENB_MASK;
483
484 raw_spin_lock(&port->lock);
485 val = readl_relaxed(addr);
486 if (event_descs[event].mask_high)
487 val &= mask;
488 else
489 val |= mask;
490 writel_relaxed(val, addr);
491 raw_spin_unlock(&port->lock);
492 }
493
494 static struct irq_chip mc_event_irq_chip = {
495 .name = "Microchip PCIe EVENT",
496 .irq_ack = mc_ack_event_irq,
497 .irq_mask = mc_mask_event_irq,
498 .irq_unmask = mc_unmask_event_irq,
499 };
500
mc_pcie_deinit_clk(void * data)501 static inline void mc_pcie_deinit_clk(void *data)
502 {
503 struct clk *clk = data;
504
505 clk_disable_unprepare(clk);
506 }
507
mc_pcie_init_clk(struct device * dev,const char * id)508 static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id)
509 {
510 struct clk *clk;
511 int ret;
512
513 clk = devm_clk_get_optional(dev, id);
514 if (IS_ERR(clk))
515 return clk;
516 if (!clk)
517 return clk;
518
519 ret = clk_prepare_enable(clk);
520 if (ret)
521 return ERR_PTR(ret);
522
523 devm_add_action_or_reset(dev, mc_pcie_deinit_clk, clk);
524
525 return clk;
526 }
527
mc_pcie_init_clks(struct device * dev)528 static int mc_pcie_init_clks(struct device *dev)
529 {
530 int i;
531 struct clk *fic;
532
533 /*
534 * PCIe may be clocked via Fabric Interface using between 1 and 4
535 * clocks. Scan DT for clocks and enable them if present
536 */
537 for (i = 0; i < ARRAY_SIZE(poss_clks); i++) {
538 fic = mc_pcie_init_clk(dev, poss_clks[i]);
539 if (IS_ERR(fic))
540 return PTR_ERR(fic);
541 }
542
543 return 0;
544 }
545
mc_request_event_irq(struct plda_pcie_rp * plda,int event_irq,int event)546 static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq,
547 int event)
548 {
549 return devm_request_irq(plda->dev, event_irq, mc_event_handler,
550 0, event_cause[event].sym, plda);
551 }
552
553 static const struct plda_event_ops mc_event_ops = {
554 .get_events = mc_get_events,
555 };
556
557 static const struct plda_event mc_event = {
558 .request_event_irq = mc_request_event_irq,
559 .intx_event = EVENT_LOCAL_PM_MSI_INT_INTX,
560 .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI,
561 };
562
mc_clear_secs(struct mc_pcie * port)563 static inline void mc_clear_secs(struct mc_pcie *port)
564 {
565 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT,
566 port->ctrl_base_addr + SEC_ERROR_INT);
567 writel_relaxed(0, port->ctrl_base_addr + SEC_ERROR_EVENT_CNT);
568 }
569
mc_clear_deds(struct mc_pcie * port)570 static inline void mc_clear_deds(struct mc_pcie *port)
571 {
572 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT,
573 port->ctrl_base_addr + DED_ERROR_INT);
574 writel_relaxed(0, port->ctrl_base_addr + DED_ERROR_EVENT_CNT);
575 }
576
mc_disable_interrupts(struct mc_pcie * port)577 static void mc_disable_interrupts(struct mc_pcie *port)
578 {
579 u32 val;
580
581 /* Ensure ECC bypass is enabled */
582 val = ECC_CONTROL_TX_RAM_ECC_BYPASS |
583 ECC_CONTROL_RX_RAM_ECC_BYPASS |
584 ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS |
585 ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS;
586 writel_relaxed(val, port->ctrl_base_addr + ECC_CONTROL);
587
588 /* Disable SEC errors and clear any outstanding */
589 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT,
590 port->ctrl_base_addr + SEC_ERROR_INT_MASK);
591 mc_clear_secs(port);
592
593 /* Disable DED errors and clear any outstanding */
594 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT,
595 port->ctrl_base_addr + DED_ERROR_INT_MASK);
596 mc_clear_deds(port);
597
598 /* Disable local interrupts and clear any outstanding */
599 writel_relaxed(0, port->bridge_base_addr + IMASK_LOCAL);
600 writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_LOCAL);
601 writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_MSI);
602
603 /* Disable PCIe events and clear any outstanding */
604 val = PCIE_EVENT_INT_L2_EXIT_INT |
605 PCIE_EVENT_INT_HOTRST_EXIT_INT |
606 PCIE_EVENT_INT_DLUP_EXIT_INT |
607 PCIE_EVENT_INT_L2_EXIT_INT_MASK |
608 PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK |
609 PCIE_EVENT_INT_DLUP_EXIT_INT_MASK;
610 writel_relaxed(val, port->ctrl_base_addr + PCIE_EVENT_INT);
611
612 /* Disable host interrupts and clear any outstanding */
613 writel_relaxed(0, port->bridge_base_addr + IMASK_HOST);
614 writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_HOST);
615 }
616
mc_pcie_setup_inbound_atr(struct mc_pcie * port,int window_index,u64 axi_addr,u64 pcie_addr,u64 size)617 static void mc_pcie_setup_inbound_atr(struct mc_pcie *port, int window_index,
618 u64 axi_addr, u64 pcie_addr, u64 size)
619 {
620 u32 table_offset = window_index * ATR_ENTRY_SIZE;
621 void __iomem *table_addr = port->bridge_base_addr + table_offset;
622 u32 atr_sz;
623 u32 val;
624
625 atr_sz = ilog2(size) - 1;
626
627 val = ALIGN_DOWN(lower_32_bits(pcie_addr), SZ_4K);
628 val |= FIELD_PREP(ATR_SIZE_MASK, atr_sz);
629 val |= ATR_IMPL_ENABLE;
630
631 writel(val, table_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
632
633 writel(upper_32_bits(pcie_addr), table_addr + ATR0_PCIE_WIN0_SRC_ADDR);
634
635 writel(lower_32_bits(axi_addr), table_addr + ATR0_PCIE_WIN0_TRSL_ADDR_LSB);
636 writel(upper_32_bits(axi_addr), table_addr + ATR0_PCIE_WIN0_TRSL_ADDR_UDW);
637
638 writel(TRSL_ID_AXI4_MASTER_0, table_addr + ATR0_PCIE_WIN0_TRSL_PARAM);
639 }
640
mc_pcie_setup_inbound_ranges(struct platform_device * pdev,struct mc_pcie * port)641 static int mc_pcie_setup_inbound_ranges(struct platform_device *pdev,
642 struct mc_pcie *port)
643 {
644 struct device *dev = &pdev->dev;
645 struct device_node *dn = dev->of_node;
646 struct of_range_parser parser;
647 struct of_range range;
648 int atr_index = 0;
649
650 /*
651 * MPFS PCIe Root Port is 32-bit only, behind a Fabric Interface
652 * Controller FPGA logic block which contains the AXI-S interface.
653 *
654 * From the point of view of the PCIe Root Port, there are only two
655 * supported Root Port configurations:
656 *
657 * Configuration 1: for use with fully coherent designs; supports a
658 * window from 0x0 (CPU space) to specified PCIe space.
659 *
660 * Configuration 2: for use with non-coherent designs; supports two
661 * 1 GB windows to CPU space; one mapping CPU space 0 to PCIe space
662 * 0x80000000 and a second mapping CPU space 0x40000000 to PCIe
663 * space 0xc0000000. This cfg needs two windows because of how the
664 * MSI space is allocated in the AXI-S range on MPFS.
665 *
666 * The FIC interface outside the PCIe block *must* complete the
667 * inbound address translation as per MCHP MPFS FPGA design
668 * guidelines.
669 */
670 if (device_property_read_bool(dev, "dma-noncoherent")) {
671 /*
672 * Always need same two tables in this case. Need two tables
673 * due to hardware interactions between address and size.
674 */
675 mc_pcie_setup_inbound_atr(port, 0, 0,
676 MPFS_NC_BOUNCE_ADDR, SZ_1G);
677 mc_pcie_setup_inbound_atr(port, 1, SZ_1G,
678 MPFS_NC_BOUNCE_ADDR + SZ_1G, SZ_1G);
679 } else {
680 /* Find any DMA ranges */
681 if (of_pci_dma_range_parser_init(&parser, dn)) {
682 /* No DMA range property - setup default */
683 mc_pcie_setup_inbound_atr(port, 0, 0, 0, SZ_4G);
684 return 0;
685 }
686
687 for_each_of_range(&parser, &range) {
688 if (atr_index >= MC_MAX_NUM_INBOUND_WINDOWS) {
689 dev_err(dev, "too many inbound ranges; %d available tables\n",
690 MC_MAX_NUM_INBOUND_WINDOWS);
691 return -EINVAL;
692 }
693 mc_pcie_setup_inbound_atr(port, atr_index, 0,
694 range.pci_addr, range.size);
695 atr_index++;
696 }
697 }
698
699 return 0;
700 }
701
mc_platform_init(struct pci_config_window * cfg)702 static int mc_platform_init(struct pci_config_window *cfg)
703 {
704 struct device *dev = cfg->parent;
705 struct platform_device *pdev = to_platform_device(dev);
706 struct pci_host_bridge *bridge = platform_get_drvdata(pdev);
707 int ret;
708
709 /* Configure address translation table 0 for PCIe config space */
710 plda_pcie_setup_window(port->bridge_base_addr, 0, cfg->res.start,
711 cfg->res.start,
712 resource_size(&cfg->res));
713
714 /* Need some fixups in config space */
715 mc_pcie_enable_msi(port, cfg->win);
716
717 /* Configure non-config space outbound ranges */
718 ret = plda_pcie_setup_iomems(bridge, &port->plda);
719 if (ret)
720 return ret;
721
722 ret = mc_pcie_setup_inbound_ranges(pdev, port);
723 if (ret)
724 return ret;
725
726 port->plda.event_ops = &mc_event_ops;
727 port->plda.event_irq_chip = &mc_event_irq_chip;
728 port->plda.events_bitmap = GENMASK(NUM_EVENTS - 1, 0);
729
730 /* Address translation is up; safe to enable interrupts */
731 ret = plda_init_interrupts(pdev, &port->plda, &mc_event);
732 if (ret)
733 return ret;
734
735 return 0;
736 }
737
mc_host_probe(struct platform_device * pdev)738 static int mc_host_probe(struct platform_device *pdev)
739 {
740 struct device *dev = &pdev->dev;
741 void __iomem *apb_base_addr;
742 struct plda_pcie_rp *plda;
743 int ret;
744 u32 val;
745
746 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
747 if (!port)
748 return -ENOMEM;
749
750 plda = &port->plda;
751 plda->dev = dev;
752
753 port->bridge_base_addr = devm_platform_ioremap_resource_byname(pdev,
754 "bridge");
755 port->ctrl_base_addr = devm_platform_ioremap_resource_byname(pdev,
756 "ctrl");
757 if (!IS_ERR(port->bridge_base_addr) && !IS_ERR(port->ctrl_base_addr))
758 goto addrs_set;
759
760 /*
761 * The original, incorrect, binding that lumped the control and
762 * bridge addresses together still needs to be handled by the driver.
763 */
764 apb_base_addr = devm_platform_ioremap_resource_byname(pdev, "apb");
765 if (IS_ERR(apb_base_addr))
766 return dev_err_probe(dev, PTR_ERR(apb_base_addr),
767 "both legacy apb register and ctrl/bridge regions missing");
768
769 port->bridge_base_addr = apb_base_addr + MC_PCIE1_BRIDGE_ADDR;
770 port->ctrl_base_addr = apb_base_addr + MC_PCIE1_CTRL_ADDR;
771
772 addrs_set:
773 mc_disable_interrupts(port);
774
775 plda->bridge_addr = port->bridge_base_addr;
776 plda->num_events = NUM_EVENTS;
777
778 /* Allow enabling MSI by disabling MSI-X */
779 val = readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0);
780 val &= ~MSIX_CAP_MASK;
781 writel(val, port->bridge_base_addr + PCIE_PCI_IRQ_DW0);
782
783 /* Pick num vectors from bitfile programmed onto FPGA fabric */
784 val = readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0);
785 val &= NUM_MSI_MSGS_MASK;
786 val >>= NUM_MSI_MSGS_SHIFT;
787
788 plda->msi.num_vectors = 1 << val;
789
790 /* Pick vector address from design */
791 plda->msi.vector_phy = readl_relaxed(port->bridge_base_addr + IMSI_ADDR);
792
793 ret = mc_pcie_init_clks(dev);
794 if (ret) {
795 dev_err(dev, "failed to get clock resources, error %d\n", ret);
796 return -ENODEV;
797 }
798
799 return pci_host_common_probe(pdev);
800 }
801
802 static const struct pci_ecam_ops mc_ecam_ops = {
803 .init = mc_platform_init,
804 .pci_ops = {
805 .map_bus = pci_ecam_map_bus,
806 .read = pci_generic_config_read,
807 .write = pci_generic_config_write,
808 }
809 };
810
811 static const struct of_device_id mc_pcie_of_match[] = {
812 {
813 .compatible = "microchip,pcie-host-1.0",
814 .data = &mc_ecam_ops,
815 },
816 {},
817 };
818
819 MODULE_DEVICE_TABLE(of, mc_pcie_of_match);
820
821 static struct platform_driver mc_pcie_driver = {
822 .probe = mc_host_probe,
823 .driver = {
824 .name = "microchip-pcie",
825 .of_match_table = mc_pcie_of_match,
826 .suppress_bind_attrs = true,
827 },
828 };
829
830 builtin_platform_driver(mc_pcie_driver);
831 MODULE_LICENSE("GPL");
832 MODULE_DESCRIPTION("Microchip PCIe host controller driver");
833 MODULE_AUTHOR("Daire McNamara <[email protected]>");
834