1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H 8 #define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H 9 10 #define GPLL0 0 11 #define GPLL4 1 12 #define GPLL2 2 13 #define GPLL2_OUT_MAIN 3 14 #define GCC_SLEEP_CLK_SRC 4 15 #define GCC_USB0_EUD_AT_CLK 6 16 #define GCC_PCIE0_AXI_M_CLK_SRC 7 17 #define GCC_PCIE0_AXI_M_CLK 8 18 #define GCC_PCIE1_AXI_M_CLK_SRC 9 19 #define GCC_PCIE1_AXI_M_CLK 10 20 #define GCC_PCIE2_AXI_M_CLK_SRC 11 21 #define GCC_PCIE2_AXI_M_CLK 12 22 #define GCC_PCIE3_AXI_M_CLK_SRC 13 23 #define GCC_PCIE3_AXI_M_CLK 14 24 #define GCC_PCIE0_AXI_S_CLK_SRC 15 25 #define GCC_PCIE0_AXI_S_BRIDGE_CLK 16 26 #define GCC_PCIE0_AXI_S_CLK 17 27 #define GCC_PCIE1_AXI_S_CLK_SRC 18 28 #define GCC_PCIE1_AXI_S_BRIDGE_CLK 19 29 #define GCC_PCIE1_AXI_S_CLK 20 30 #define GCC_PCIE2_AXI_S_CLK_SRC 21 31 #define GCC_PCIE2_AXI_S_BRIDGE_CLK 22 32 #define GCC_PCIE2_AXI_S_CLK 23 33 #define GCC_PCIE3_AXI_S_CLK_SRC 24 34 #define GCC_PCIE3_AXI_S_BRIDGE_CLK 25 35 #define GCC_PCIE3_AXI_S_CLK 26 36 #define GCC_PCIE0_PIPE_CLK_SRC 27 37 #define GCC_PCIE0_PIPE_CLK 28 38 #define GCC_PCIE1_PIPE_CLK_SRC 29 39 #define GCC_PCIE1_PIPE_CLK 30 40 #define GCC_PCIE2_PIPE_CLK_SRC 31 41 #define GCC_PCIE2_PIPE_CLK 32 42 #define GCC_PCIE3_PIPE_CLK_SRC 33 43 #define GCC_PCIE3_PIPE_CLK 34 44 #define GCC_PCIE_AUX_CLK_SRC 35 45 #define GCC_PCIE0_AUX_CLK 36 46 #define GCC_PCIE1_AUX_CLK 37 47 #define GCC_PCIE2_AUX_CLK 38 48 #define GCC_PCIE3_AUX_CLK 39 49 #define GCC_PCIE0_AHB_CLK 40 50 #define GCC_PCIE1_AHB_CLK 41 51 #define GCC_PCIE2_AHB_CLK 42 52 #define GCC_PCIE3_AHB_CLK 43 53 #define GCC_USB0_AUX_CLK_SRC 44 54 #define GCC_USB0_AUX_CLK 45 55 #define GCC_USB0_MASTER_CLK 46 56 #define GCC_USB0_MOCK_UTMI_CLK_SRC 47 57 #define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 48 58 #define GCC_USB0_MOCK_UTMI_CLK 49 59 #define GCC_USB0_PIPE_CLK_SRC 50 60 #define GCC_USB0_PIPE_CLK 51 61 #define GCC_USB0_PHY_CFG_AHB_CLK 52 62 #define GCC_USB0_SLEEP_CLK 53 63 #define GCC_SDCC1_APPS_CLK_SRC 54 64 #define GCC_SDCC1_APPS_CLK 55 65 #define GCC_SDCC1_ICE_CORE_CLK_SRC 56 66 #define GCC_SDCC1_ICE_CORE_CLK 57 67 #define GCC_SDCC1_AHB_CLK 58 68 #define GCC_PCNOC_BFDCD_CLK_SRC 59 69 #define GCC_NSSCFG_CLK 60 70 #define GCC_NSSNOC_NSSCC_CLK 61 71 #define GCC_NSSCC_CLK 62 72 #define GCC_NSSNOC_PCNOC_1_CLK 63 73 #define GCC_QPIC_AHB_CLK 64 74 #define GCC_QPIC_CLK 65 75 #define GCC_MDIO_AHB_CLK 66 76 #define GCC_PRNG_AHB_CLK 67 77 #define GCC_UNIPHY0_AHB_CLK 68 78 #define GCC_UNIPHY1_AHB_CLK 69 79 #define GCC_UNIPHY2_AHB_CLK 70 80 #define GCC_CMN_12GPLL_AHB_CLK 71 81 #define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 72 82 #define GCC_NSSNOC_SNOC_CLK 73 83 #define GCC_NSSNOC_SNOC_1_CLK 74 84 #define GCC_WCSS_AHB_CLK_SRC 75 85 #define GCC_QDSS_AT_CLK_SRC 76 86 #define GCC_NSSNOC_ATB_CLK 77 87 #define GCC_QDSS_AT_CLK 78 88 #define GCC_QDSS_TSCTR_CLK_SRC 79 89 #define GCC_NSS_TS_CLK 80 90 #define GCC_QPIC_IO_MACRO_CLK_SRC 81 91 #define GCC_QPIC_IO_MACRO_CLK 82 92 #define GCC_LPASS_AXIM_CLK_SRC 83 93 #define GCC_LPASS_CORE_AXIM_CLK 84 94 #define GCC_LPASS_SWAY_CLK_SRC 85 95 #define GCC_LPASS_SWAY_CLK 86 96 #define GCC_CNOC_LPASS_CFG_CLK 87 97 #define GCC_SNOC_LPASS_CLK 88 98 #define GCC_ADSS_PWM_CLK_SRC 89 99 #define GCC_ADSS_PWM_CLK 90 100 #define GCC_XO_CLK_SRC 91 101 #define GCC_NSSNOC_XO_DCD_CLK 92 102 #define GCC_NSSNOC_QOSGEN_REF_CLK 93 103 #define GCC_NSSNOC_TIMEOUT_REF_CLK 94 104 #define GCC_UNIPHY0_SYS_CLK 95 105 #define GCC_UNIPHY1_SYS_CLK 96 106 #define GCC_UNIPHY2_SYS_CLK 97 107 #define GCC_CMN_12GPLL_SYS_CLK 98 108 #define GCC_UNIPHY_SYS_CLK_SRC 99 109 #define GCC_NSS_TS_CLK_SRC 100 110 #define GCC_ANOC_PCIE0_1LANE_M_CLK 101 111 #define GCC_ANOC_PCIE1_1LANE_M_CLK 102 112 #define GCC_ANOC_PCIE2_2LANE_M_CLK 103 113 #define GCC_ANOC_PCIE3_2LANE_M_CLK 104 114 #define GCC_CNOC_PCIE0_1LANE_S_CLK 105 115 #define GCC_CNOC_PCIE1_1LANE_S_CLK 106 116 #define GCC_CNOC_PCIE2_2LANE_S_CLK 107 117 #define GCC_CNOC_PCIE3_2LANE_S_CLK 108 118 #define GCC_CNOC_USB_CLK 109 119 #define GCC_CNOC_WCSS_AHB_CLK 110 120 #define GCC_QUPV3_AHB_MST_CLK 111 121 #define GCC_QUPV3_AHB_SLV_CLK 112 122 #define GCC_QUPV3_I2C0_CLK 113 123 #define GCC_QUPV3_I2C1_CLK 114 124 #define GCC_QUPV3_SPI0_CLK 115 125 #define GCC_QUPV3_SPI1_CLK 116 126 #define GCC_QUPV3_UART0_CLK 117 127 #define GCC_QUPV3_UART1_CLK 118 128 #define GCC_QPIC_CLK_SRC 119 129 #define GCC_QUPV3_I2C0_CLK_SRC 120 130 #define GCC_QUPV3_I2C1_CLK_SRC 121 131 #define GCC_QUPV3_I2C0_DIV_CLK_SRC 122 132 #define GCC_QUPV3_I2C1_DIV_CLK_SRC 123 133 #define GCC_QUPV3_SPI0_CLK_SRC 124 134 #define GCC_QUPV3_SPI1_CLK_SRC 125 135 #define GCC_QUPV3_UART0_CLK_SRC 126 136 #define GCC_QUPV3_UART1_CLK_SRC 127 137 #define GCC_USB1_MASTER_CLK 128 138 #define GCC_USB1_MOCK_UTMI_CLK_SRC 129 139 #define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 130 140 #define GCC_USB1_MOCK_UTMI_CLK 131 141 #define GCC_USB1_SLEEP_CLK 132 142 #define GCC_USB1_PHY_CFG_AHB_CLK 133 143 #define GCC_USB0_MASTER_CLK_SRC 134 144 #define GCC_QDSS_DAP_CLK 135 145 #define GCC_PCIE0_RCHNG_CLK_SRC 136 146 #define GCC_PCIE0_RCHNG_CLK 137 147 #define GCC_PCIE1_RCHNG_CLK_SRC 138 148 #define GCC_PCIE1_RCHNG_CLK 139 149 #define GCC_PCIE2_RCHNG_CLK_SRC 140 150 #define GCC_PCIE2_RCHNG_CLK 141 151 #define GCC_PCIE3_RCHNG_CLK_SRC 142 152 #define GCC_PCIE3_RCHNG_CLK 143 153 #define GCC_IM_SLEEP_CLK 144 154 #define GCC_XO_CLK 145 155 156 #endif 157