1 /*
2 * Copyright (c) 2021-2024, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file     encode_av1_scc.h
24 //! \brief    SCC feature
25 //!
26 
27 #ifndef __ENCODE_AV1_SCC_H__
28 #define __ENCODE_AV1_SCC_H__
29 
30 #include "encode_av1_basic_feature.h"
31 
32 namespace encode
33 {
34 
35 enum
36 {
37     IBC_DISABLED = 0,
38     LBC_ONLY     = 1,
39     IBC_ENABLED  = 3
40 };
41 
42 enum
43 {
44     vdencCmd2Par3Value0 = 0,
45     vdencCmd2Par3Value1 = 1,
46     vdencCmd2Par3Value2 = 2,
47     vdencCmd2Par3Value3 = 3
48 };
49 
50 enum
51 {
52     vdencCmd2Par136Value0 = 0,
53     vdencCmd2Par136Value1 = 2
54 };
55 
56 enum
57 {
58     vdencCmd2Par135Value0,
59     vdencCmd2Par135Value1,
60     vdencCmd2Par135Value2,
61     vdencCmd2Par135Value3
62 };
63 
64 class Av1Segmentation;
65 
66 class Av1Scc : public MediaFeature, public mhw::vdbox::vdenc::Itf::ParSetting, public mhw::vdbox::avp::Itf::ParSetting
67 {
68 public:
69     Av1Scc(EncodeAllocator *allocator,
70         CodechalHwInterfaceNext *hwInterface,
71         void *constSettings,
72         MediaFeatureManager *featureManager);
73 
74     MOS_STATUS Update(void *params) override;
75 
76     virtual ~Av1Scc();
77 
78     MHW_SETPAR_DECL_HDR(VDENC_HEVC_VP9_TILE_SLICE_STATE);
79 
80     MHW_SETPAR_DECL_HDR(VDENC_CMD2);
81 
82     MHW_SETPAR_DECL_HDR(VDENC_CMD1);
83 
84     MHW_SETPAR_DECL_HDR(VDENC_PIPE_BUF_ADDR_STATE);
85 
86     MHW_SETPAR_DECL_HDR(AVP_PIC_STATE);
87 
88     MHW_SETPAR_DECL_HDR(AVP_PIPE_BUF_ADDR_STATE);
89 
90     MHW_SETPAR_DECL_HDR(AVP_SURFACE_STATE);
91 
92     MOS_STATUS UpdateIBCStatusForCurrentTile();
93 
94 protected:
95 
96     MOS_STATUS MakeCdfTrackedBufferLockable();
97     MOS_STATUS ResetMvProbsToDefault();
98 
99     bool m_enablePalette            = false;
100     bool m_enableIBC                = false;
101     bool m_IBCPossible              = false;
102     bool m_resetMvProbs             = false;
103     bool m_IBCEnabledForCurrentTile = false;
104 
105     Av1BasicFeature *m_basicFeature = nullptr;  //!< AV1 Basic Feature
106     Av1Segmentation *m_segmentation = nullptr;  //!< AV1 Segmentation Feature
107     EncodeAllocator *m_allocator    = nullptr;
108     MOS_INTERFACE   *m_osInterface  = nullptr;
109     const uint16_t   AV1table[10][3] =
110     {
111         {16, 2, 4},
112         {16, 2, 4},
113         {16, 2, 4},
114         {16, 2, 4},
115         {16, 2, 4},
116         {16, 2, 5},
117         {16, 2, 5},
118         {16, 2, 5},
119         {16, 2, 5},
120         {16, 2, 5},
121     };
122 
123     PMOS_SURFACE m_intrabcReconSurface = nullptr;  //!< IntraBC reconstructed surface
124 
125 MEDIA_CLASS_DEFINE_END(encode__Av1Scc)
126 };
127 }  // namespace encode
128 
129 #endif  // __ENCODE_AV1_SCC_H__
130