1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ 3 4 #ifndef __MLX5_ESW_QOS_H__ 5 #define __MLX5_ESW_QOS_H__ 6 7 #ifdef CONFIG_MLX5_ESWITCH 8 9 int mlx5_esw_qos_init(struct mlx5_eswitch *esw); 10 void mlx5_esw_qos_cleanup(struct mlx5_eswitch *esw); 11 12 int mlx5_esw_qos_set_vport_rate(struct mlx5_vport *evport, u32 max_rate, u32 min_rate); 13 bool mlx5_esw_qos_get_vport_rate(struct mlx5_vport *vport, u32 *max_rate, u32 *min_rate); 14 void mlx5_esw_qos_vport_disable(struct mlx5_vport *vport); 15 16 void mlx5_esw_qos_vport_qos_free(struct mlx5_vport *vport); 17 u32 mlx5_esw_qos_vport_get_sched_elem_ix(const struct mlx5_vport *vport); 18 struct mlx5_esw_sched_node *mlx5_esw_qos_vport_get_parent(const struct mlx5_vport *vport); 19 20 int mlx5_esw_devlink_rate_leaf_tx_share_set(struct devlink_rate *rate_leaf, void *priv, 21 u64 tx_share, struct netlink_ext_ack *extack); 22 int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, void *priv, 23 u64 tx_max, struct netlink_ext_ack *extack); 24 int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node, void *priv, 25 u64 tx_share, struct netlink_ext_ack *extack); 26 int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, void *priv, 27 u64 tx_max, struct netlink_ext_ack *extack); 28 int mlx5_esw_devlink_rate_node_new(struct devlink_rate *rate_node, void **priv, 29 struct netlink_ext_ack *extack); 30 int mlx5_esw_devlink_rate_node_del(struct devlink_rate *rate_node, void *priv, 31 struct netlink_ext_ack *extack); 32 int mlx5_esw_devlink_rate_parent_set(struct devlink_rate *devlink_rate, 33 struct devlink_rate *parent, 34 void *priv, void *parent_priv, 35 struct netlink_ext_ack *extack); 36 #endif 37 38 #endif 39