1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H 4 #define SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H 5 6 /* From JEDEC SFDP JESD216F.02 */ 7 #define SFDP_HDR_SIG 0x00 /* 1st DWORD of SFDP header */ 8 #define SFDP_PARAM_DENSITY 0x04 /* 2nd DWORD of SFDP params */ 9 #define SFDP_SIGNATURE 0x50444653 /* Valid sig in 1st DWORD of SFDP header */ 10 11 /* PCI configuration registers */ 12 #define SPI_BIOS_DECODE_EN 0xd8 13 #define SPI_BIOS_DECODE_LOCK BIT(31) 14 15 #define SPI_BIOS_CONTROL 0xdc 16 17 /* Extended Bios Support Registers */ 18 #define SPI_CFG_BAR1 0xe0 /* SPI BAR1 MMIO */ 19 20 /* Bit definitions for BIOS_CONTROL */ 21 #define SPI_BIOS_CONTROL_WPD (1 << 0) 22 #define SPI_BIOS_CONTROL_LOCK_ENABLE (1 << 1) 23 #define SPI_BIOS_CONTROL_CACHE_DISABLE (1 << 2) 24 #define SPI_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) 25 #define SPI_BIOS_CONTROL_EISS (1 << 5) 26 #define SPI_BIOS_CONTROL_BILD (1 << 7) 27 #define SPI_BIOS_CONTROL_SYNC_SS (1 << 8) 28 #define SPI_BIOS_CONTROL_EXT_BIOS_ENABLE (1 << 27) 29 #define SPI_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE (1 << 28) 30 #define SPI_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff)) 31 32 /* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ 33 34 #define SPIBAR_BFPREG 0x00 35 #define SPIBAR_HSFSTS_CTL 0x04 36 #define SPIBAR_FADDR 0x08 37 #define SPIBAR_DLOCK 0x0c 38 #define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) 39 #define SPIBAR_FPR_BASE 0x84 40 #define SPIBAR_FPR(n) (0x84 + (4 * (n))) 41 #define SPIBAR_PREOP 0xa4 42 #define SPIBAR_OPTYPE 0xa6 43 #define SPIBAR_OPMENU_LOWER 0xa8 44 #define SPIBAR_OPMENU_UPPER 0xac 45 #define SPIBAR_FDOC 0xb4 46 #define SPIBAR_FDOD 0xb8 47 #define SPIBAR_SFDP0_VSCC0 0xc4 48 #define SPIBAR_PTINX 0xcc 49 #define SPIBAR_PTDATA 0xd0 50 51 /* Bit definitions for BFPREG (0x00) register */ 52 #define SPIBAR_BFPREG_PRB_MASK 0x7fff 53 #define SPIBAR_BFPREG_PRL_SHIFT 16 54 #define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) 55 #define SPIBAR_BFPREG_SBRS (1 << 31) 56 57 /* Bit definitions for HSFSTS_CTL (0x04) register */ 58 #define SPIBAR_HSFSTS_FDBC_MASK (0x3f << 24) 59 #define SPIBAR_HSFSTS_FDBC(n) (((n) << 24) & SPIBAR_HSFSTS_FDBC_MASK) 60 #define SPIBAR_HSFSTS_WET (1 << 21) 61 #define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) 62 #define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK) 63 64 /* Supported flash cycle types */ 65 #define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0) 66 #define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2) 67 #define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) 68 #define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) 69 #define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) 70 71 #define SPIBAR_HSFSTS_FGO (1 << 16) 72 #define SPIBAR_HSFSTS_FLOCKDN (1 << 15) 73 #define SPIBAR_HSFSTS_FDV (1 << 14) 74 #define SPIBAR_HSFSTS_FDOPSS (1 << 13) 75 #define SPIBAR_HSFSTS_PRR34_LOCKDN (1 << 12) 76 #define SPIBAR_HSFSTS_WRSDIS (1 << 11) 77 #define SPIBAR_HSFSTS_SAF_CE (1 << 8) 78 #define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) 79 #define SPIBAR_HSFSTS_SAF_LE (1 << 6) 80 #define SPIBAR_HSFSTS_SCIP (1 << 5) 81 #define SPIBAR_HSFSTS_SAF_DLE (1 << 4) 82 #define SPIBAR_HSFSTS_SAF_ERROR (1 << 3) 83 #define SPIBAR_HSFSTS_AEL (1 << 2) 84 #define SPIBAR_HSFSTS_FCERR (1 << 1) 85 #define SPIBAR_HSFSTS_FDONE (1 << 0) 86 #define SPIBAR_HSFSTS_W1C_BITS 0x1ff 87 88 /* Bit definitions for FADDR (0x08) register */ 89 #define SPIBAR_FADDR_MASK 0x7ffffff 90 91 /* Bit definitions for DLOCK (0x0c) register */ 92 #define SPIBAR_DLOCK_PR0LOCKDN (1 << 8) 93 #define SPIBAR_DLOCK_PR1LOCKDN (1 << 9) 94 #define SPIBAR_DLOCK_PR2LOCKDN (1 << 10) 95 #define SPIBAR_DLOCK_PR3LOCKDN (1 << 11) 96 #define SPIBAR_DLOCK_PR4LOCKDN (1 << 12) 97 98 /* Maximum bytes of data that can fit in FDATAn (0x10) registers */ 99 #define SPIBAR_FDATA_FIFO_SIZE 0x40 100 101 /* Bit definitions for FDOC (0xb4) register */ 102 #define SPIBAR_FDOC_COMPONENT (1 << 12) 103 #define SPIBAR_FDOC_FDSI_1 (1 << 2) 104 105 /* Flash Descriptor Component Section - Component 0 Density Bit Settings */ 106 #define FLCOMP_C0DEN_MASK 0xf 107 #define FLCOMP_C0DEN_8MB 4 108 #define FLCOMP_C0DEN_16MB 5 109 #define FLCOMP_C0DEN_32MB 6 110 111 /* Bit definitions for FPRn (0x84 + (4 * n)) registers */ 112 #define SPIBAR_FPR_WPE (1 << 31) /* Flash Write protected */ 113 #define SPIBAR_FPR_MAX 5 114 115 /* Programmable values for OPMENU_LOWER(0xa8) & OPMENU_UPPER(0xac) register */ 116 #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ 117 #define SPI_OPTYPE_0 0x01 /* Write, no address */ 118 #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ 119 #define SPI_OPTYPE_1 0x03 /* Write, address required */ 120 #define SPI_OPMENU_2 0x03 /* READ: Read Data */ 121 #define SPI_OPTYPE_2 0x02 /* Read, address required */ 122 #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ 123 #define SPI_OPTYPE_3 0x00 /* Read, no address */ 124 #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ 125 #define SPI_OPTYPE_4 0x03 /* Write, address required */ 126 #define SPI_OPMENU_5 0x9f /* RDID: Read ID */ 127 #define SPI_OPTYPE_5 0x00 /* Read, no address */ 128 #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ 129 #define SPI_OPTYPE_6 0x03 /* Write, address required */ 130 #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ 131 #define SPI_OPTYPE_7 0x02 /* Read, address required */ 132 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ 133 (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) 134 #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ 135 (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) 136 #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ 137 (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ 138 (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ 139 (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) 140 #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ 141 142 /* 143 * Spi Flash Vendor Specific Component Capabilities 144 * for Component 0 (0xc4) register 145 */ 146 #define SPIBAR_SFDP0_VSCC0_VCL (1 << 30) 147 148 /* 149 * Register Offset of BIOS Vendor Specific Component Capabilities (VSCC) 150 * for Component 0 Register 151 */ 152 #define SPIBAR_SFDP0_VSCC0 0xc4 153 #define SPIBAR_VSCC0_VCL (1 << 30) 154 155 /* Bit definitions for PTINX (0xcc) register */ 156 #define SPIBAR_PTINX_COMP_0 (0 << 14) 157 #define SPIBAR_PTINX_COMP_1 (1 << 14) 158 #define SPIBAR_PTINX_HORD_SFDP (0 << 12) 159 #define SPIBAR_PTINX_HORD_PARAM (1 << 12) 160 #define SPIBAR_PTINX_HORD_JEDEC (2 << 12) 161 162 /* Register Offsets of BIOS Flash Program Registers */ 163 #define SPIBAR_RESET_LOCK 0xf0 164 #define SPIBAR_RESET_CTRL 0xf4 165 #define SPIBAR_RESET_DATA 0xf8 166 167 /* Programmable values of Bit0 (SSL) of Set STRAP MSG LOCK (0xF0) Register */ 168 #define SPIBAR_RESET_LOCK_DISABLE 0 /* Set_Strap Lock(SSL) Bit 0 = 0 */ 169 #define SPIBAR_RESET_LOCK_ENABLE 1 /* Set_Strap Lock(SSL) Bit 0 = 1 */ 170 171 /* Programmable values of Bit0(SSMS) of Set STRAP MSG Control (0xF4) Register*/ 172 #define SPIBAR_RESET_CTRL_SSMC 1 /* Set_Strap Mux Select(SSMS) Bit=1*/ 173 174 #define SPIBAR_HWSEQ_XFER_TIMEOUT_MS 5000 175 176 void *fast_spi_get_bar(void); 177 178 #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H */ 179