1 /*
2 * Copyright © 2016 Rob Clark <[email protected]>
3 * Copyright © 2018 Google, Inc.
4 * SPDX-License-Identifier: MIT
5 *
6 * Authors:
7 * Rob Clark <[email protected]>
8 */
9
10 #ifndef FD6_CONTEXT_H_
11 #define FD6_CONTEXT_H_
12
13 #include "util/u_upload_mgr.h"
14
15 #include "freedreno_context.h"
16 #include "freedreno_resource.h"
17
18 #include "ir3/ir3_shader.h"
19 #include "ir3/ir3_descriptor.h"
20
21 #include "a6xx.xml.h"
22
23 struct fd6_lrz_state {
24 union {
25 struct {
26 bool enable : 1;
27 bool write : 1;
28 bool test : 1;
29 bool z_bounds_enable : 1;
30 enum fd_lrz_direction direction : 2;
31
32 /* this comes from the fs program state, rather than zsa: */
33 enum a6xx_ztest_mode z_mode : 2;
34 };
35 uint32_t val : 8;
36 };
37 };
38
39 /**
40 * Bindless descriptor set state for a single descriptor set.
41 */
42 struct fd6_descriptor_set {
43 /**
44 * Pre-baked descriptor state, updated when image/SSBO is bound
45 */
46 uint32_t descriptor[IR3_BINDLESS_DESC_COUNT][FDL6_TEX_CONST_DWORDS];
47
48 /**
49 * The current seqn of the backed in resource, for detecting if the
50 * resource has been rebound
51 */
52 uint16_t seqno[IR3_BINDLESS_DESC_COUNT];
53
54 /**
55 * Current GPU copy of the desciptor set
56 */
57 struct fd_bo *bo;
58 };
59
60 static inline void
fd6_descriptor_set_invalidate(struct fd6_descriptor_set * set)61 fd6_descriptor_set_invalidate(struct fd6_descriptor_set *set)
62 {
63 if (!set->bo)
64 return;
65 fd_bo_del(set->bo);
66 set->bo = NULL;
67 }
68
69 struct fd6_context {
70 struct fd_context base;
71
72 /* Two buffers related to hw binning / visibility stream (VSC).
73 * Compared to previous generations
74 * (1) we cannot specify individual buffers per VSC, instead
75 * just a pitch and base address
76 * (2) there is a second smaller buffer.. we also stash
77 * VSC_BIN_SIZE at end of 2nd buffer.
78 */
79 struct fd_bo *vsc_draw_strm, *vsc_prim_strm;
80
81 unsigned vsc_draw_strm_pitch, vsc_prim_strm_pitch;
82
83 /* The 'control' mem BO is used for various housekeeping
84 * functions. See 'struct fd6_control'
85 */
86 struct fd_bo *control_mem;
87 uint32_t seqno;
88
89 /* pre-baked stateobj for stream-out disable: */
90 struct fd_ringbuffer *streamout_disable_stateobj;
91
92 /* pre-baked stateobj for sample-locations disable: */
93 struct fd_ringbuffer *sample_locations_disable_stateobj;
94
95 /* storage for ctx->last.key: */
96 struct ir3_shader_key last_key;
97
98 /* Is there current VS driver-param state set? */
99 bool has_dp_state;
100
101 /* cached stateobjs to avoid hashtable lookup when not dirty: */
102 const struct fd6_program_state *prog;
103
104 /* We expect to see a finite # of unique border-color entry values,
105 * which are a function of the color value and (to a limited degree)
106 * the border color format. These unique border-color entry values
107 * get populated into a global border-color buffer, and a hash-table
108 * is used to map to the matching entry in the table.
109 */
110 struct hash_table *bcolor_cache;
111 struct fd_bo *bcolor_mem;
112
113 struct util_idalloc tex_ids;
114 struct hash_table *tex_cache;
115 bool tex_cache_needs_invalidate;
116
117 /**
118 * Descriptor sets for 3d shader stages
119 */
120 struct fd6_descriptor_set descriptor_sets[5] dt;
121
122 /**
123 * Descriptor set for compute shaders
124 */
125 struct fd6_descriptor_set cs_descriptor_set dt;
126
127 struct {
128 /* previous lrz state, which is a function of multiple gallium
129 * stateobjs, but doesn't necessarily change as frequently:
130 */
131 struct fd6_lrz_state lrz;
132 } last;
133 };
134
135 static inline struct fd6_context *
fd6_context(struct fd_context * ctx)136 fd6_context(struct fd_context *ctx)
137 {
138 return (struct fd6_context *)ctx;
139 }
140
141 template <chip CHIP>
142 struct pipe_context *fd6_context_create(struct pipe_screen *pscreen, void *priv,
143 unsigned flags);
144
145 /* This struct defines the layout of the fd6_context::control buffer: */
146 struct fd6_control {
147 uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
148 uint32_t _pad0;
149 volatile uint32_t vsc_overflow;
150 uint32_t _pad1[5];
151
152 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
153 struct {
154 uint32_t offset;
155 uint32_t pad[7];
156 } flush_base[4];
157 };
158
159 #define control_ptr(fd6_ctx, member) \
160 (fd6_ctx)->control_mem, offsetof(struct fd6_control, member), 0, 0
161
162 static inline void
emit_marker6(struct fd_ringbuffer * ring,int scratch_idx)163 emit_marker6(struct fd_ringbuffer *ring, int scratch_idx)
164 {
165 extern int32_t marker_cnt;
166 unsigned reg = REG_A6XX_CP_SCRATCH_REG(scratch_idx);
167 if (__EMIT_MARKER) {
168 OUT_WFI5(ring);
169 OUT_PKT4(ring, reg, 1);
170 OUT_RING(ring, p_atomic_inc_return(&marker_cnt));
171 }
172 }
173
174 struct fd6_vertex_stateobj {
175 struct fd_vertex_stateobj base;
176 struct fd_ringbuffer *stateobj;
177 };
178
179 static inline struct fd6_vertex_stateobj *
fd6_vertex_stateobj(void * p)180 fd6_vertex_stateobj(void *p)
181 {
182 return (struct fd6_vertex_stateobj *)p;
183 }
184
185 #endif /* FD6_CONTEXT_H_ */
186