1 /***********************************************************************************************************************
2 * Copyright [2015-2017] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
3 *
4 * This file is part of Renesas SynergyTM Software Package (SSP)
5 *
6 * The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
7 * and/or its licensors ("Renesas") and subject to statutory and contractual protections.
8 *
9 * This file is subject to a Renesas SSP license agreement. Unless otherwise agreed in an SSP license agreement with
10 * Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
11 * or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
12 * MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
13 * "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
14 * PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
15 * CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
16 * CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
17 * included in this file may be subject to different terms.
18 **********************************************************************************************************************/
19
20 /**********************************************************************************************************************
21 * File Name : hw_cgc.h
22 * Description : Header file for hw_cgc.c
23 **********************************************************************************************************************/
24 #ifndef HW_CGC_H
25 #define HW_CGC_H
26
27 #include "bsp_cfg.h"
28 #include "bsp_clock_cfg.h"
29 #include "hw_cgc_private.h"
30 #include "../r_cgc_private.h"
31
32 /* Common macro for SSP header files. There is also a corresponding SSP_FOOTER macro at the end of this file. */
33 SSP_HEADER
34
35
36 /**********************************************************************************************************************
37 * Macro definitions
38 **********************************************************************************************************************/
39
40 #if BSP_FEATURE_HAS_CGC_PLL
41 #define CGC_CLOCK_NUM_CLOCKS ((uint8_t) CGC_CLOCK_PLL + 1U)
42 #else
43 #define CGC_CLOCK_NUM_CLOCKS ((uint8_t) CGC_CLOCK_SUBCLOCK + 1U)
44 #endif
45
46 /** PRC0 mask */
47 #define CGC_PRC0_MASK ((uint16_t) 0x0001)
48 /** PRC1 mask */
49 #define CGC_PRC1_MASK ((uint16_t) 0x0002)
50 /** Key code for writing PRCR register. */
51 #define CGC_PRCR_KEY ((uint16_t) 0xA500)
52 #define CGC_PLL_MAIN_OSC (0x00U) ///< PLL clock source register value for the main oscillator
53 #define CGC_PLL_HOCO (0x01U) ///< PLL clock source register value for the HOCO
54
55 #define CGC_LOCO_FREQ (32768U) ///< LOCO frequency is fixed at 32768 Hz
56 #define CGC_MOCO_FREQ (8000000U) ///< MOCO frequency is fixed at 8 MHz
57 #define CGC_SUBCLOCK_FREQ (32768U) ///< Subclock frequency is 32768 Hz
58 #define CGC_PLL_FREQ (0U) ///< The PLL frequency must be calculated.
59 #define CGC_IWDT_FREQ (15000U) ///< The IWDT frequency is fixed at 15 kHz
60 #define CGC_S124_LOW_V_MODE_FREQ (4000000U) ///< Max ICLK frequency while in Low Voltage Mode for S124
61
62 #define CGC_MAX_ZERO_WAIT_FREQ (32000000U)
63 #define CGC_MAX_MIDDLE_SPEED_FREQ (12000000U) ///< Maximum frequency for Middle Speed mode
64
65 #define CGC_CLOCKOUT_MAX (CGC_CLOCK_SUBCLOCK) ///< Highest enum value for CLKOUT clock source
66
67 #define CGC_SYSTEMS_CLOCKS_MAX (CGC_SYSTEM_CLOCKS_ICLK) ///< Highest enum value for system clock
68
69 #define CGC_HW_MAX_REGISTER_WAIT_COUNT (0xFFFFU)
70
71 /**********************************************************************************************************************
72 * Typedef definitions
73 **********************************************************************************************************************/
74
75 typedef union
76 {
77 __IO uint32_t sckdivcr_w; /*!< (@ 0x4001E020) System clock Division control register
78 * */
79 /*LDRA_INSPECTED 381 S Anonymous structures and unions are allowed in SSP code. */
80 struct
81 {
82 __IO uint32_t pckd : 3; /*!< [0..2] Peripheral Module Clock D (PCLKD) Select
83 * */
84 uint32_t : 1;
85 __IO uint32_t pckc : 3; /*!< [4..6] Peripheral Module Clock C (PCLKC) Select
86 * */
87 uint32_t : 1;
88 __IO uint32_t pckb : 3; /*!< [8..10] Peripheral Module Clock B (PCLKB) Select
89 * */
90 uint32_t : 1;
91 __IO uint32_t pcka : 3; /*!< [12..14] Peripheral Module Clock A (PCLKA) Select
92 * */
93 uint32_t : 1;
94 __IO uint32_t bck : 3; /*!< [16..18] External Bus Clock (BCLK) Select
95 * */
96 uint32_t : 5;
97 __IO uint32_t ick : 3; /*!< [24..26] System Clock (ICLK) Select
98 * */
99 uint32_t : 1;
100 __IO uint32_t fck : 3; /*!< [28..30] Flash IF Clock (FCLK) Select
101 * */
102 } sckdivcr_b; /*!< [31] BitSize
103 * */
104 } sckdivcr_clone_t;
105
106
107 /**********************************************************************************************************************
108 * Function Prototypes
109 **********************************************************************************************************************/
110 /*******************************************************************************************************************//**
111 @addtogroup CGC
112
113 @{
114 **********************************************************************************************************************/
115
116 /**********************************************************************************************************************
117 * Inline Functions
118 **********************************************************************************************************************/
119
120 /*******************************************************************************************************************//**
121 * @brief This function places the MCU in High Speed Mode
122 * @param[in] p_system_reg pointer to system register structure
123 * @retval None
124 **********************************************************************************************************************/
HW_CGC_SetHighSpeedMode(R_SYSTEM_Type * p_system_reg)125 __STATIC_INLINE void HW_CGC_SetHighSpeedMode (R_SYSTEM_Type * p_system_reg)
126 {
127 r_cgc_operating_hw_modeset(p_system_reg, CGC_HIGH_SPEED_MODE);
128 }
129
130 /*******************************************************************************************************************//**
131 * @brief This function places the MCU in Middle Speed Mode
132 * @param[in] p_system_reg pointer to system register structure
133 * @retval None
134 **********************************************************************************************************************/
135
HW_CGC_SetMiddleSpeedMode(R_SYSTEM_Type * p_system_reg)136 __STATIC_INLINE void HW_CGC_SetMiddleSpeedMode (R_SYSTEM_Type * p_system_reg)
137 {
138 r_cgc_operating_hw_modeset(p_system_reg, CGC_MIDDLE_SPEED_MODE);
139 }
140
141 /*******************************************************************************************************************//**
142 * @brief This function places the MCU in Low Voltage Mode
143 * @param[in] p_system_reg pointer to system register structure
144 * @retval None
145 **********************************************************************************************************************/
146
HW_CGC_SetLowVoltageMode(R_SYSTEM_Type * p_system_reg)147 __STATIC_INLINE void HW_CGC_SetLowVoltageMode (R_SYSTEM_Type * p_system_reg)
148 {
149 r_cgc_operating_hw_modeset(p_system_reg, CGC_LOW_VOLTAGE_MODE);
150 }
151
152 /*******************************************************************************************************************//**
153 * @brief This function places the MCU in Low Speed Mode
154 * @param[in] p_system_reg pointer to system register structure
155 * @retval None
156 **********************************************************************************************************************/
157
HW_CGC_SetLowSpeedMode(R_SYSTEM_Type * p_system_reg)158 __STATIC_INLINE void HW_CGC_SetLowSpeedMode (R_SYSTEM_Type * p_system_reg)
159 {
160 r_cgc_operating_hw_modeset(p_system_reg, CGC_LOW_SPEED_MODE);
161 }
162
163 /*******************************************************************************************************************//**
164 * @brief This function places the MCU in Sub-Osc Speed Mode
165 * @param[in] p_system_reg pointer to system register structure
166 * @retval None
167 **********************************************************************************************************************/
168
HW_CGC_SetSubOscSpeedMode(R_SYSTEM_Type * p_system_reg)169 __STATIC_INLINE void HW_CGC_SetSubOscSpeedMode (R_SYSTEM_Type * p_system_reg)
170 {
171 r_cgc_operating_hw_modeset(p_system_reg, CGC_SUBOSC_SPEED_MODE);
172 }
173
174
175 #if BSP_FEATURE_HAS_CGC_LCD_CLK
176 /*******************************************************************************************************************//**
177 * @brief This function configures the Segment LCD clock
178 * @param[in] p_system_reg pointer to system register structure
179 * @param[in] clock is the LCD clock source
180 * @retval none
181 **********************************************************************************************************************/
182
HW_CGC_LCDClockCfg(R_SYSTEM_Type * p_system_reg,uint8_t clock)183 __STATIC_INLINE void HW_CGC_LCDClockCfg (R_SYSTEM_Type * p_system_reg, uint8_t clock)
184 {
185 p_system_reg->SLCDSCKCR_b.LCDSCKSEL = clock & 0xFU;
186 }
187
188 /*******************************************************************************************************************//**
189 * @brief This function returns the Segment LCD clock configuration
190 * @param[in] p_system_reg pointer to system register structure
191 * @retval LCD clock configuration
192 **********************************************************************************************************************/
193
HW_CGC_LCDClockCfgGet(R_SYSTEM_Type * p_system_reg)194 __STATIC_INLINE uint8_t HW_CGC_LCDClockCfgGet (R_SYSTEM_Type * p_system_reg)
195 {
196 return p_system_reg->SLCDSCKCR_b.LCDSCKSEL;
197 }
198
199 /*******************************************************************************************************************//**
200 * @brief This function enables LCD Clock Out
201 * @param[in] p_system_reg pointer to system register structure
202 * @retval none
203 **********************************************************************************************************************/
204
HW_CGC_LCDClockEnable(R_SYSTEM_Type * p_system_reg)205 __STATIC_INLINE void HW_CGC_LCDClockEnable (R_SYSTEM_Type * p_system_reg)
206 {
207 p_system_reg->SLCDSCKCR_b.LCDSCKEN = 1U;
208 }
209
210 /*******************************************************************************************************************//**
211 * @brief This function disables LCD Clock Out
212 * @param[in] p_system_reg pointer to system register structure
213 * @retval none
214 **********************************************************************************************************************/
215
HW_CGC_LCDClockDisable(R_SYSTEM_Type * p_system_reg)216 __STATIC_INLINE void HW_CGC_LCDClockDisable (R_SYSTEM_Type * p_system_reg)
217 {
218 p_system_reg->SLCDSCKCR_b.LCDSCKEN = 0U;
219 }
220
221 /*******************************************************************************************************************//**
222 * @brief This function queries LCD clock to see if it is enabled.
223 * @param[in] p_system_reg pointer to system register structure
224 * @retval true if enabled, false if disabled
225 **********************************************************************************************************************/
226
HW_CGC_LCDClockIsEnabled(R_SYSTEM_Type * p_system_reg)227 __STATIC_INLINE bool HW_CGC_LCDClockIsEnabled (R_SYSTEM_Type * p_system_reg)
228 {
229 if (p_system_reg->SLCDSCKCR_b.LCDSCKEN == 1U)
230 {
231 return true;
232 }
233 else
234 {
235 return false;
236 }
237 }
238 #endif /* #if BSP_FEATURE_HAS_CGC_LCD_CLK */
239
240 #if BSP_FEATURE_HAS_CGC_SDADC_CLK
241 /*******************************************************************************************************************//**
242 * @brief This function configures the SDADC clock
243 * @param[in] p_system_reg pointer to system register structure
244 * @param[in] clock is the SDADC clock source
245 * @retval none
246 **********************************************************************************************************************/
247
HW_CGC_SDADCClockCfg(R_SYSTEM_Type * p_system_reg,uint8_t clock)248 __STATIC_INLINE void HW_CGC_SDADCClockCfg (R_SYSTEM_Type * p_system_reg, uint8_t clock)
249 {
250 if (clock == CGC_CLOCK_HOCO)
251 {
252 p_system_reg->SDADCCKCR_b.SDADCCKSEL = 1U;
253 }
254 else
255 {
256 p_system_reg->SDADCCKCR_b.SDADCCKSEL = 0U;
257 }
258 }
259
260 /*******************************************************************************************************************//**
261 * @brief This function returns the SDADC clock configuration
262 * @param[in] p_system_reg pointer to system register structure
263 * @retval SDADC clock configuration
264 **********************************************************************************************************************/
265
HW_CGC_SDADCClockCfgGet(R_SYSTEM_Type * p_system_reg)266 __STATIC_INLINE uint8_t HW_CGC_SDADCClockCfgGet (R_SYSTEM_Type * p_system_reg)
267 {
268 return p_system_reg->SDADCCKCR_b.SDADCCKSEL;
269 }
270
271 /*******************************************************************************************************************//**
272 * @brief This function enables SDADC Clock Out
273 * @param[in] p_system_reg pointer to system register structure
274 * @retval none
275 **********************************************************************************************************************/
276
HW_CGC_SDADCClockEnable(R_SYSTEM_Type * p_system_reg)277 __STATIC_INLINE void HW_CGC_SDADCClockEnable (R_SYSTEM_Type * p_system_reg)
278 {
279 p_system_reg->SDADCCKCR_b.SDADCCKEN = 1U;
280 }
281
282 /*******************************************************************************************************************//**
283 * @brief This function disables SDADC Clock Out
284 * @param[in] p_system_reg pointer to system register structure
285 * @retval none
286 **********************************************************************************************************************/
287
HW_CGC_SDADCClockDisable(R_SYSTEM_Type * p_system_reg)288 __STATIC_INLINE void HW_CGC_SDADCClockDisable (R_SYSTEM_Type * p_system_reg)
289 {
290 p_system_reg->SDADCCKCR_b.SDADCCKEN = 0U;
291 }
292
293 /*******************************************************************************************************************//**
294 * @brief This function queries SDADC clock to see if it is enabled.
295 * @param[in] p_system_reg pointer to system register structure
296 * @retval true if enabled, false if disabled
297 **********************************************************************************************************************/
298
HW_CGC_SDADCClockIsEnabled(R_SYSTEM_Type * p_system_reg)299 __STATIC_INLINE bool HW_CGC_SDADCClockIsEnabled (R_SYSTEM_Type * p_system_reg)
300 {
301 if (p_system_reg->SDADCCKCR_b.SDADCCKEN == 1U)
302 {
303 return true;
304 }
305 else
306 {
307 return false;
308 }
309 }
310 #endif /* BSP_FEATURE_HAS_CGC_SDADC_CLK */
311
312
313 /*******************************************************************************************************************//**
314 * @brief This function locks CGC registers
315 * @retval none
316 **********************************************************************************************************************/
HW_CGC_HardwareLock(void)317 __STATIC_INLINE void HW_CGC_HardwareLock (void)
318 {
319 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC);
320 }
321
322 /*******************************************************************************************************************//**
323 * @brief This function unlocks CGC registers
324 * @retval none
325 **********************************************************************************************************************/
326
HW_CGC_HardwareUnLock(void)327 __STATIC_INLINE void HW_CGC_HardwareUnLock (void)
328 {
329 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC);
330 }
331
332 /*******************************************************************************************************************//**
333 * @brief This function locks CGC registers
334 * @retval none
335 **********************************************************************************************************************/
HW_CGC_LPMHardwareLock(void)336 __STATIC_INLINE void HW_CGC_LPMHardwareLock (void)
337 {
338 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
339 }
340
341 /*******************************************************************************************************************//**
342 * @brief This function unlocks CGC registers
343 * @retval none
344 **********************************************************************************************************************/
345
HW_CGC_LPMHardwareUnLock(void)346 __STATIC_INLINE void HW_CGC_LPMHardwareUnLock (void)
347 {
348 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
349 }
350
351
352 /*******************************************************************************************************************//**
353 * @brief This function checks that the clock is available in the hardware
354 * @param[in] clock Check clock to see if it is valid
355 * @retval true if clock available, false if not
356 **********************************************************************************************************************/
357
HW_CGC_ClockSourceValidCheck(cgc_clock_t clock)358 __STATIC_INLINE bool HW_CGC_ClockSourceValidCheck (cgc_clock_t clock)
359 {
360 return (clock < CGC_CLOCK_NUM_CLOCKS);
361 }
362
363 /*******************************************************************************************************************//**
364 * @brief This function returns the system clock source
365 * @param[in] p_system_reg pointer to system register structure
366 * @retval the enum of the current system clock
367 **********************************************************************************************************************/
368
HW_CGC_ClockSourceGet(R_SYSTEM_Type * p_system_reg)369 __STATIC_INLINE cgc_clock_t HW_CGC_ClockSourceGet (R_SYSTEM_Type * p_system_reg)
370 {
371 /* Get the system clock source */
372 return (cgc_clock_t) p_system_reg->SCKSCR_b.CKSEL;
373 }
374
375
376 /*******************************************************************************************************************//**
377 * @brief This function returns the status of the stop detection function
378 * @param[in] p_system_reg pointer to system register structure
379 * @retval true if detected, false if not detected
380 **********************************************************************************************************************/
HW_CGC_OscStopDetectEnabledGet(R_SYSTEM_Type * p_system_reg)381 __STATIC_INLINE bool HW_CGC_OscStopDetectEnabledGet (R_SYSTEM_Type * p_system_reg)
382 {
383 if (p_system_reg->OSTDCR_b.OSTDE == 1U) // is stop detection enabled?
384 {
385 return true; // Function enabled.
386 }
387 return false; // Function not enabled.
388
389 }
390 /*******************************************************************************************************************//**
391 * @brief This function returns the status of the stop detection function
392 * @param[in] p_system_reg pointer to system register structure
393 * @retval true if detected, false if not detected
394 **********************************************************************************************************************/
395
HW_CGC_OscStopDetectGet(R_SYSTEM_Type * p_system_reg)396 __STATIC_INLINE bool HW_CGC_OscStopDetectGet (R_SYSTEM_Type * p_system_reg)
397 {
398 /* oscillator stop detected */
399 if (p_system_reg->OSTDSR_b.OSTDF == 1U)
400 {
401 return true; // stop detected
402 }
403
404 return false; // no stop detected
405 }
406
407 #if BSP_FEATURE_HAS_CGC_EXTERNAL_BUS
408 /*******************************************************************************************************************//**
409 * @brief This function configures the BusClock Out divider
410 * @param[in] p_system_reg pointer to system register structure
411 * @param[in] divider is the bus clock out divider
412 * @retval none
413 **********************************************************************************************************************/
414
HW_CGC_BusClockOutCfg(R_SYSTEM_Type * p_system_reg,cgc_bclockout_dividers_t divider)415 __STATIC_INLINE void HW_CGC_BusClockOutCfg (R_SYSTEM_Type * p_system_reg, cgc_bclockout_dividers_t divider)
416 {
417 /* */
418 HW_CGC_HardwareUnLock();
419 p_system_reg->BCKCR_b.BCLKDIV = divider; // set external bus clock output divider
420 HW_CGC_HardwareLock();
421 }
422
423 /*******************************************************************************************************************//**
424 * @brief This function enables BusClockOut
425 * @param[in] p_system_reg pointer to system register structure
426 * @retval none
427 **********************************************************************************************************************/
428
HW_CGC_BusClockOutEnable(R_SYSTEM_Type * p_system_reg)429 __STATIC_INLINE void HW_CGC_BusClockOutEnable (R_SYSTEM_Type * p_system_reg)
430 {
431 /* */
432 HW_CGC_HardwareUnLock();
433 p_system_reg->EBCKOCR_b.EBCKOEN = 1U; // enable bus clock output
434 HW_CGC_HardwareLock();
435 }
436
437 /*******************************************************************************************************************//**
438 * @brief This function disables BusClockOut
439 * @param[in] p_system_reg pointer to system register structure
440 * @retval none
441 **********************************************************************************************************************/
442
HW_CGC_BusClockOutDisable(R_SYSTEM_Type * p_system_reg)443 __STATIC_INLINE void HW_CGC_BusClockOutDisable (R_SYSTEM_Type * p_system_reg)
444 {
445 /* */
446 HW_CGC_HardwareUnLock();
447 p_system_reg->EBCKOCR_b.EBCKOEN = 0U; // disable bus clock output (fixed high level)
448 HW_CGC_HardwareLock();
449 }
450 #endif /* BSP_FEATURE_HAS_CGC_EXTERNAL_BUS */
451
452 #if BSP_FEATURE_HAS_CGC_SDRAM_CLK
453 /*******************************************************************************************************************//**
454 * @brief This function enables SDRAM ClockOut
455 * @param[in] p_system_reg pointer to system register structure
456 * @retval none
457 **********************************************************************************************************************/
HW_CGC_SDRAMClockOutEnable(R_SYSTEM_Type * p_system_reg)458 __STATIC_INLINE void HW_CGC_SDRAMClockOutEnable (R_SYSTEM_Type * p_system_reg)
459 {
460 HW_CGC_HardwareUnLock();
461 p_system_reg->SDCKOCR_b.SDCKOEN = 1U; // enable SDRAM output
462 HW_CGC_HardwareLock();
463 }
464
465 /*******************************************************************************************************************//**
466 * @brief This function disables SDRAM ClockOut
467 * @param[in] p_system_reg pointer to system register structure
468 * @retval none
469 **********************************************************************************************************************/
470
HW_CGC_SDRAMClockOutDisable(R_SYSTEM_Type * p_system_reg)471 __STATIC_INLINE void HW_CGC_SDRAMClockOutDisable (R_SYSTEM_Type * p_system_reg)
472 {
473 HW_CGC_HardwareUnLock();
474 p_system_reg->SDCKOCR_b.SDCKOEN = 0U; // disable SDRAM output (fixed high level)
475 HW_CGC_HardwareLock();
476 }
477 #endif /* BSP_FEATURE_HAS_CGC_SDRAM_CLK */
478
479
480
481 #if BSP_FEATURE_HAS_CGC_USB_CLK
482 /*******************************************************************************************************************//**
483 * @brief This function configures the USB clock divider
484 * @param[in] p_system_reg pointer to system register structure
485 * @param[in] divider is the USB clock divider
486 * @retval none
487 **********************************************************************************************************************/
488
HW_CGC_USBClockCfg(R_SYSTEM_Type * p_system_reg,cgc_usb_clock_div_t divider)489 __STATIC_INLINE void HW_CGC_USBClockCfg (R_SYSTEM_Type * p_system_reg, cgc_usb_clock_div_t divider)
490 {
491 HW_CGC_HardwareUnLock();
492 p_system_reg->SCKDIVCR2_b.UCK = divider; // set USB divider
493 HW_CGC_HardwareLock();
494 }
495 #endif /* BSP_FEATURE_HAS_CGC_USB_CLK */
496 /*******************************************************************************************************************//**
497 * @} (end addtogroup CGC)
498 **********************************************************************************************************************/
499
500 /* Common macro for SSP header files. There is also a corresponding SSP_HEADER macro at the top of this file. */
501 SSP_FOOTER
502 #endif // ifndef HW_CGC_H
503