1 /** 2 ****************************************************************************** 3 * File Name : hw_conf.h 4 * Description : Hardware configuration file for BLE 5 * middleWare. 6 ****************************************************************************** 7 * This notice applies to any and all portions of this file 8 * that are not between comment pairs USER CODE BEGIN and 9 * USER CODE END. Other portions of this file, whether 10 * inserted by the user or by software development tools 11 * are owned by their respective copyright owners. 12 * 13 * Copyright (c) 2018 STMicroelectronics International N.V. 14 * All rights reserved. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted, provided that the following conditions are met: 18 * 19 * 1. Redistribution of source code must retain the above copyright notice, 20 * this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright notice, 22 * this list of conditions and the following disclaimer in the documentation 23 * and/or other materials provided with the distribution. 24 * 3. Neither the name of STMicroelectronics nor the names of other 25 * contributors to this software may be used to endorse or promote products 26 * derived from this software without specific written permission. 27 * 4. This software, including modifications and/or derivative works of this 28 * software, must execute solely and exclusively on microcontroller or 29 * microprocessor devices manufactured by or for STMicroelectronics. 30 * 5. Redistribution and use of this software other than as permitted under 31 * this license is void and will automatically terminate your rights under 32 * this license. 33 * 34 * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 35 * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 37 * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY 38 * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 39 * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 41 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 42 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 43 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 44 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 45 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 * 47 ****************************************************************************** 48 */ 49 50 /* Define to prevent recursive inclusion -------------------------------------*/ 51 #ifndef __HW_CONF_H 52 #define __HW_CONF_H 53 54 /****************************************************************************** 55 * Semaphores 56 * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+ 57 *****************************************************************************/ 58 /* Index of the semaphore used to manage the entry Stop Mode procedure */ 59 #define CFG_HW_ENTRY_STOP_MODE_SEMID 4 60 61 /* Index of the semaphore used to access the RCC */ 62 #define CFG_HW_RCC_SEMID 3 63 64 /* Index of the semaphore used to access the FLASH */ 65 #define CFG_HW_FLASH_SEMID 2 66 67 /* Index of the semaphore used to access the PKA */ 68 #define CFG_HW_PKA_SEMID 1 69 70 /* Index of the semaphore used to access the RNG */ 71 #define CFG_HW_RNG_SEMID 0 72 73 /****************************************************************************** 74 * HW TIMER SERVER 75 *****************************************************************************/ 76 /** 77 * The user may define the maximum number of virtual timers supported. 78 * It shall not exceed 255 79 */ 80 #define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER 6 81 82 /** 83 * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the 84 * wakeup timer. 85 * This setting is the preemptpriority part of the NVIC. 86 */ 87 #define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO 3 88 89 /** 90 * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the 91 * wakeup timer. 92 * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported 93 * on the CPU, the setting is ignored 94 */ 95 #define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO 0 96 97 /** 98 * Define a critical section in the Timer server 99 * The Timer server does not support the API to be nested 100 * The Application shall either: 101 * a) Ensure this will never happen 102 * b) Define the critical section 103 * The default implementations is masking all interrupts using the PRIMASK bit 104 * The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro 105 * TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set 106 * to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI 107 * register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall 108 * re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer 109 * API are called when the TIMER critical section is entered 110 */ 111 #define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION 1 112 113 /** 114 * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt 115 * is generated by the Hardware and the time when the RTC interrupt handler is called. This time is measured in 116 * number of RTCCLK ticks. 117 * A relaxed timing would be 10ms 118 * When the value is too short, the timerserver will not be able to count properly and all timeout may be random. 119 * When the value is too long, the device may wake up more often than the most optimal configuration. However, the 120 * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly 121 * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system 122 * as this will have marginal impact on low power mode 123 */ 124 #define CFG_HW_TS_RTC_HANDLER_MAX_DELAY ( 10 * (LSI_VALUE/1000) ) 125 126 /** 127 * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler 128 * It shall be type of IRQn_Type 129 */ 130 #define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID RTC_WKUP_IRQn 131 132 /****************************************************************************** 133 * HW UART 134 *****************************************************************************/ 135 136 #define CFG_HW_LPUART1_ENABLED 0 137 #define CFG_HW_LPUART1_DMA_TX_SUPPORTED 0 138 139 #define CFG_HW_USART1_ENABLED 0 140 #define CFG_HW_USART1_DMA_TX_SUPPORTED 0 141 142 #endif /*__HW_CONF_H */ 143 144 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 145