1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_BLOCK_I2C_PAD_DEF_H 4 #define AMD_BLOCK_I2C_PAD_DEF_H 5 6 #include <types.h> 7 8 /* MISC_I2Cx_PAD_CTRL and MISC_I23Cx_PAD_CTRL are in the same place, but have different bit 9 definitions. Which one is present depends on the SoC. */ 10 #define MISC_I2C0_PAD_CTRL 0xd8 11 #define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) 12 13 #define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 14 #define I2C_PAD_CTRL_NG_NORMAL 0xc 15 #define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) 16 #define I2C_PAD_CTRL_RX_SHIFT 4 17 #define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) 18 #define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) 19 #define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) 20 #define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) 21 #define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8)) 22 #define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 23 #define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) 24 #define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) 25 #define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) 26 #define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) 27 #define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ 28 #define I2C_PAD_CTRL_CAP_DOWN BIT(12) 29 #define I2C_PAD_CTRL_CAP_UP BIT(13) 30 #define I2C_PAD_CTRL_RES_DOWN BIT(14) 31 #define I2C_PAD_CTRL_RES_UP BIT(15) 32 #define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) 33 #define I2C_PAD_CTRL_SPARE0 BIT(17) 34 #define I2C_PAD_CTRL_SPARE1 BIT(18) 35 /* The following bits are reserved in Picasso and Cezanne */ 36 #define I2C_PAD_CTRL_PD_EN BIT(19) 37 #define I2C_PAD_CTRL_COMP_SEL BIT(20) 38 #define I2C_PAD_CTRL_RES_BIAS_EN BIT(21) 39 40 #endif /* AMD_BLOCK_I2C_PAD_DEF_H */ 41