1 /*============================================================================== 2 Copyright(c) 2017 Intel Corporation 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files(the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and / or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included 12 in all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 OTHER DEALINGS IN THE SOFTWARE. 21 ============================================================================ 22 ** 23 ** File Name : igfxfmid.h 24 ** 25 ** Abastract : Family IDs for device abstraction 26 ** 27 ** Authors : Ken Stevens 28 ** 29 ** Environment : Win9x and WinNT builds. 30 ** 31 ** Items in File : Family IDs for Intel Graphics Controllers 32 ** 33 ** ---------------------------------------------------------------------- */ 34 #ifndef __IGFXFMID_H__ 35 #define __IGFXFMID_H__ 36 37 typedef enum { 38 IGFX_UNKNOWN = 0, 39 IGFX_GRANTSDALE_G, 40 IGFX_ALVISO_G, 41 IGFX_LAKEPORT_G, 42 IGFX_CALISTOGA_G, 43 IGFX_BROADWATER_G, 44 IGFX_CRESTLINE_G, 45 IGFX_BEARLAKE_G, 46 IGFX_CANTIGA_G, 47 IGFX_CEDARVIEW_G, 48 IGFX_EAGLELAKE_G, 49 IGFX_IRONLAKE_G, 50 IGFX_GT, 51 IGFX_IVYBRIDGE, 52 IGFX_HASWELL, 53 IGFX_VALLEYVIEW, 54 IGFX_BROADWELL, 55 IGFX_CHERRYVIEW, 56 IGFX_SKYLAKE, 57 IGFX_KABYLAKE, 58 IGFX_COFFEELAKE, 59 IGFX_WILLOWVIEW, 60 IGFX_BROXTON, 61 IGFX_GEMINILAKE, 62 IGFX_CANNONLAKE, 63 IGFX_ICELAKE, 64 IGFX_ICELAKE_LP, 65 IGFX_LAKEFIELD, 66 IGFX_JASPERLAKE, 67 IGFX_ELKHARTLAKE =IGFX_JASPERLAKE, 68 69 IGFX_TIGERLAKE_LP, 70 IGFX_ROCKETLAKE, 71 IGFX_ALDERLAKE_S, 72 IGFX_ALDERLAKE_P, 73 IGFX_ALDERLAKE_N, 74 IGFX_DG1 = 1210, 75 IGFX_XE_HP_SDV = 1250, 76 IGFX_DG2 = 1270, 77 IGFX_PVC = 1271, 78 IGFX_METEORLAKE = 1272, 79 IGFX_ARROWLAKE = 1273, 80 IGFX_BMG = 1274, 81 IGFX_LUNARLAKE = 1275, 82 83 IGFX_MAX_PRODUCT, 84 IGFX_GENNEXT = 0x7ffffffe, 85 PRODUCT_FAMILY_FORCE_ULONG = 0x7fffffff 86 } PRODUCT_FAMILY; 87 88 typedef enum { 89 PCH_UNKNOWN = 0, 90 PCH_IBX, // Ibexpeak 91 PCH_CPT, // Cougarpoint, 92 PCH_CPTR, // Cougarpoint Refresh, 93 PCH_PPT, // Panther Point 94 PCH_LPT, // Lynx Point 95 PCH_LPTR, // Lynx Point Refresh 96 PCH_WPT, // Wildcat point 97 PCH_SPT, // 98 PCH_KBP, // Kabylake PCH 99 PCH_CNP_LP, // Cannonlake LP PCH 100 PCH_CNP_H, // Cannonlake Halo PCH 101 PCH_ICP_LP, // ICL LP PCH 102 PCH_ICP_N, // ICL N PCH 103 PCH_LKF, // LKF PCH 104 PCH_TGL_LP, // TGL LP PCH 105 PCH_CMP_LP, // CML LP PCH 106 PCH_CMP_H, // CML Halo PCH 107 PCH_CMP_V, // CML V PCH 108 PCH_JSP_N, // JSL N PCH Device IDs for JSL+ Rev02 109 PCH_ADL_S, // ADL_S PCH 110 PCH_ADL_P, // ADL_P PCH 111 PCH_TGL_H, // TGL H PCH 112 PCH_ADL_N, // ADL_N PCHDL 113 PCH_MTL, // MTL PCH 114 PCH_ARL, // ARL PCH 115 116 PCH_PRODUCT_FAMILY_FORCE_ULONG = 0x7fffffff 117 } PCH_PRODUCT_FAMILY; 118 119 typedef enum { 120 IGFX_UNKNOWN_CORE = 0, 121 IGFX_GEN3_CORE = 1, //Gen3 Family 122 IGFX_GEN3_5_CORE = 2, //Gen3.5 Family 123 IGFX_GEN4_CORE = 3, //Gen4 Family 124 IGFX_GEN4_5_CORE = 4, //Gen4.5 Family 125 IGFX_GEN5_CORE = 5, //Gen5 Family 126 IGFX_GEN5_5_CORE = 6, //Gen5.5 Family 127 IGFX_GEN5_75_CORE = 7, //Gen5.75 Family 128 IGFX_GEN6_CORE = 8, //Gen6 Family 129 IGFX_GEN7_CORE = 9, //Gen7 Family 130 IGFX_GEN7_5_CORE = 10, //Gen7.5 Family 131 IGFX_GEN8_CORE = 11, //Gen8 Family 132 IGFX_GEN9_CORE = 12, //Gen9 Family 133 IGFX_GEN10_CORE = 13, //Gen10 Family 134 IGFX_GEN10LP_CORE = 14, //Gen10 LP Family 135 IGFX_GEN11_CORE = 15, //Gen11 Family 136 IGFX_GEN11LP_CORE = 16, //Gen11 LP Family 137 IGFX_GEN12_CORE = 17, //Gen12 Family 138 IGFX_GEN12LP_CORE = 18, //Gen12 LP Family 139 IGFX_XE_HP_CORE = 0x0c05, //XE_HP family 140 IGFX_XE_HPG_CORE = 0x0c07, // XE_HPG Family 141 IGFX_XE_HPC_CORE = 0x0c08, // XE_HPC Family 142 IGFX_XE2_LPG_CORE = 0x0c09, // XE2_LPG Family 143 IGFX_XE2_HPG_CORE = IGFX_XE2_LPG_CORE, //XE2_HPG Family 144 145 //Please add new GENs BEFORE THIS ! 146 IGFX_MAX_CORE, 147 148 IGFX_GENNEXT_CORE = 0x7ffffffe, //GenNext 149 GFXCORE_FAMILY_FORCE_ULONG = 0x7fffffff 150 } GFXCORE_FAMILY; 151 152 typedef enum { 153 IGFX_SKU_NONE = 0, // IGFX_SKU_UNKNOWN defined in \opengl\source\desktop\ail\ailgl_profiles.h 154 IGFX_SKU_ULX = 1, 155 IGFX_SKU_ULT = 2, 156 IGFX_SKU_T = 3, 157 IGFX_SKU_ALL = 0xff 158 } PLATFORM_SKU; 159 160 typedef enum __GTTYPE 161 { 162 GTTYPE_GT1 = 0x0, 163 GTTYPE_GT2, 164 GTTYPE_GT2_FUSED_TO_GT1, 165 GTTYPE_GT2_FUSED_TO_GT1_6, //IVB 166 GTTYPE_GTL, // HSW 167 GTTYPE_GTM, // HSW 168 GTTYPE_GTH, // HSW 169 GTTYPE_GT1_5,//HSW 170 GTTYPE_GT1_75,//HSW 171 GTTYPE_GT3,//BDW 172 GTTYPE_GT4,//BDW 173 GTTYPE_GT0,//BDW 174 GTTYPE_GTA,// BXT 175 GTTYPE_GTC,// BXT 176 GTTYPE_GTX, // BXT 177 GTTYPE_GT2_5,//CNL 178 GTTYPE_GT3_5,//SKL 179 GTTYPE_GT0_5,//CNL 180 GTTYPE_UNDEFINED,//Always at the end. 181 }GTTYPE, *PGTTYPE; 182 183 ///////////////////////////////////////////////////////////////// 184 // 185 // Platform types which are used during Sku/Wa initialization. 186 // 187 #ifndef _COMMON_PPA 188 typedef enum { 189 PLATFORM_NONE = 0x00, 190 PLATFORM_DESKTOP = 0x01, 191 PLATFORM_MOBILE = 0x02, 192 PLATFORM_TABLET = 0X03, 193 PLATFORM_ALL = 0xff, // flag used for applying any feature/WA for All platform types 194 } PLATFORM_TYPE; 195 #endif 196 typedef struct PLATFORM_STR { 197 PRODUCT_FAMILY eProductFamily; 198 PCH_PRODUCT_FAMILY ePCHProductFamily; 199 GFXCORE_FAMILY eDisplayCoreFamily; 200 GFXCORE_FAMILY eRenderCoreFamily; 201 #ifndef _COMMON_PPA 202 PLATFORM_TYPE ePlatformType; 203 #endif 204 205 unsigned short usDeviceID; 206 unsigned short usRevId; 207 unsigned short usDeviceID_PCH; 208 unsigned short usRevId_PCH; 209 // GT Type 210 // Note: Is valid only till Gen9. From Gen10 SKUs are not identified by any GT flags. 'GT_SYSTEM_INFO' should be used instead. 211 GTTYPE eGTType; 212 213 } PLATFORM; 214 215 // add enums at the end 216 typedef enum __SKUIDTYPE 217 { 218 SKU_FULL_TYPE = 0x0, 219 SKU_VALUE_TYPE, 220 SKU_PLUS_FULL_TYPE, 221 SKU_PLUS_VALUE_TYPE, 222 SKU_T_TYPE, 223 SKU_PLUS_T_TYPE, 224 SKU_P_TYPE, 225 SKU_PLUS_P_TYPE, 226 SKU_SMALL_TYPE, 227 SKU_LIGHT_TYPE, 228 SKU_N_TYPE 229 }SKUIDTYPE, *PSKUIDTYPE; 230 231 typedef enum __CPUTYPE 232 { 233 CPU_UNDEFINED = 0x0, 234 CPU_CORE_I3, 235 CPU_CORE_I5, 236 CPU_CORE_I7, 237 CPU_PENTIUM, 238 CPU_CELERON, 239 CPU_CORE, 240 CPU_VPRO, 241 CPU_SUPER_SKU, 242 CPU_ATOM, 243 CPU_CORE1, 244 CPU_CORE2, 245 CPU_WS, 246 CPU_SERVER, 247 CPU_CORE_I5_I7, 248 CPU_COREX1_4, 249 CPU_ULX_PENTIUM, 250 CPU_MB_WORKSTATION, 251 CPU_DT_WORKSTATION, 252 CPU_M3, 253 CPU_M5, 254 CPU_M7, 255 CPU_MEDIA_SERVER //Added for KBL 256 }CPUTYPE, *PCPUTYPE; 257 258 // the code below convert platform real revision number to pre-defined revision number, the revision will be set as follow 259 // REVISION_A0 - this will include all incarnations for A stepping in all packages types A = {A0} 260 // REVISION_A1 - this will include all incarnations for A stepping in all packages types A = {A1} 261 // REVISION_A3 - this will include all incarnations for A stepping in all packages types A = {A3,...,A7} 262 // REVISION_B - this will include all incarnations for B stepping in all packages types B = {B0,B1,..,B7} 263 // REVISION_C - this will include all incarnations for C stepping in all packages types C = {C0,C1,..,C7} 264 // REVISION_D - this will include all incarnations for C stepping in all packages types C = {D0,D1} 265 // REVISION_K - this will include all incarnations for K stepping in all packages types K = {K0,K1,..,K7} 266 typedef enum __REVID 267 { 268 REVISION_A0 = 0, 269 REVISION_A1, //1 270 REVISION_A3,//2 271 REVISION_B,//3 272 REVISION_C,//4 273 REVISION_D,//5 274 REVISION_K//6 275 }REVID, *PREVID; 276 277 typedef enum __NATIVEGTTYPE 278 { 279 NATIVEGTTYPE_HSW_UNDEFINED = 0x00, 280 NATIVEGTTYPE_HSW_GT1 = 0x01, 281 NATIVEGTTYPE_HSW_GT2 = 0x02, 282 NATIVEGTTYPE_HSW_GT3 = 0x03, 283 }NATIVEGTTYPE; 284 285 // Following macros return true/false depending on the current PCH family 286 #define PCH_IS_PRODUCT(p, r) ( (p).ePCHProductFamily == r ) 287 #define PCH_GET_CURRENT_PRODUCT(p) ( (p).ePCHProductFamily ) 288 289 // These macros return true/false depending on current product/core family. 290 #define GFX_IS_PRODUCT(p, r) ( (p).eProductFamily == r ) 291 #define GFX_IS_DISPLAYCORE(p, d) ( (p).eDisplayCoreFamily == d ) 292 #define GFX_IS_RENDERCORE(p, r) ( (p).eRenderCoreFamily == r ) 293 // These macros return the current product/core family enum. 294 // Relational compares (</>) should not be done when using GFX_GET_CURRENT_PRODUCT 295 // macro. There are no relationships between the PRODUCT_FAMILY enum values. 296 #define GFX_GET_CURRENT_PRODUCT(p) ( (p).eProductFamily ) 297 #define GFX_GET_CURRENT_DISPLAYCORE(p) ( (p).eDisplayCoreFamily ) 298 #define GFX_GET_CURRENT_RENDERCORE(p) ( (p).eRenderCoreFamily ) 299 300 // This macro returns true if the product family is discrete 301 #define GFX_IS_DISCRETE_PRODUCT(pf) ( ( pf == IGFX_DG1 ) || \ 302 ( pf == IGFX_DG2 ) || \ 303 ( pf == IGFX_XE_HP_SDV ) || \ 304 ( pf == IGFX_BMG ) ) 305 306 #define GFX_IS_DISCRETE_FAMILY(p) GFX_IS_DISCRETE_PRODUCT(GFX_GET_CURRENT_PRODUCT(p)) 307 308 #define GFX_IS_INTEGRATED_PRODUCT(pf) (!GFX_IS_DISCRETE_PRODUCT(pf)) 309 310 #define GFX_IS_INTEGRATED_FAMILY(p) (!GFX_IS_DISCRETE_FAMILY(p)) 311 312 313 // These macros return true/false depending on the current render family. 314 #define GFX_IS_NAPA_RENDER_FAMILY(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN3_CORE ) || \ 315 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN3_5_CORE ) ) 316 317 #define GFX_IS_GEN_RENDER_FAMILY(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN4_CORE ) || \ 318 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN4_5_CORE ) || \ 319 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN5_CORE ) || \ 320 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN5_5_CORE ) || \ 321 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN5_75_CORE ) || \ 322 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN6_CORE ) || \ 323 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_CORE ) || \ 324 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_5_CORE ) || \ 325 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN8_CORE ) || \ 326 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN9_CORE ) || \ 327 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN10_CORE ) || \ 328 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 329 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN12_CORE ) || \ 330 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 331 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 332 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 333 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE2_HPG_CORE ) || \ 334 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 335 336 #define GFX_IS_GEN_5_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN5_CORE ) || \ 337 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN5_5_CORE ) || \ 338 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN5_75_CORE ) || \ 339 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN6_CORE ) || \ 340 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_CORE ) || \ 341 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_5_CORE ) || \ 342 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN8_CORE ) || \ 343 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN9_CORE ) || \ 344 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN10_CORE ) || \ 345 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 346 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN12_CORE ) || \ 347 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 348 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 349 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 350 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE2_HPG_CORE ) || \ 351 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 352 353 #define GFX_IS_GEN_5_75_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN5_75_CORE ) || \ 354 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN6_CORE ) || \ 355 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_CORE ) || \ 356 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_5_CORE ) || \ 357 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN8_CORE ) || \ 358 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN9_CORE ) || \ 359 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN10_CORE ) || \ 360 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 361 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN12_CORE ) || \ 362 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 363 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 364 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 365 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE2_HPG_CORE ) || \ 366 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 367 368 #define GFX_IS_GEN_6_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN6_CORE ) || \ 369 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_CORE ) || \ 370 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_5_CORE ) || \ 371 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN8_CORE ) || \ 372 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN9_CORE ) || \ 373 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN10_CORE ) || \ 374 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 375 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 376 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 377 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 378 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE2_HPG_CORE ) || \ 379 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 380 381 #define GFX_IS_GEN_7_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_CORE ) || \ 382 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_5_CORE ) || \ 383 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN8_CORE ) || \ 384 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN9_CORE ) || \ 385 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN10_CORE ) || \ 386 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 387 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN12_CORE ) || \ 388 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 389 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 390 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 391 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE2_HPG_CORE ) || \ 392 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 393 394 #define GFX_IS_GEN_7_5_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN7_5_CORE ) || \ 395 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN8_CORE ) || \ 396 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN9_CORE ) || \ 397 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN10_CORE ) || \ 398 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 399 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN12_CORE ) || \ 400 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 401 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 402 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 403 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 404 405 #define GFX_IS_GEN_8_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN8_CORE ) || \ 406 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN9_CORE ) || \ 407 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN10_CORE ) || \ 408 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 409 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN12_CORE ) || \ 410 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 411 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 412 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 413 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 414 415 #define GFX_IS_GEN_8_CHV_OR_LATER(p) ( ( GFX_GET_CURRENT_PRODUCT(p) == IGFX_CHERRYVIEW ) || \ 416 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN9_CORE ) || \ 417 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN10_CORE ) || \ 418 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 419 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN12_CORE ) || \ 420 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 421 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 422 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 423 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 424 425 #define GFX_IS_GEN_9_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN9_CORE ) || \ 426 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN10_CORE ) || \ 427 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 428 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN12_CORE ) || \ 429 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 430 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 431 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 432 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 433 434 #define GFX_IS_GEN_10_OR_LATER(p) (( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN10_CORE ) || \ 435 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 436 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN12_CORE ) || \ 437 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 438 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 439 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 440 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 441 442 #define GFX_IS_GEN_11_OR_LATER(p) (( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN11_CORE ) || \ 443 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GEN12_CORE ) || \ 444 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HP_CORE ) || \ 445 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPG_CORE ) || \ 446 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_XE_HPC_CORE ) || \ 447 ( GFX_GET_CURRENT_RENDERCORE(p) == IGFX_GENNEXT_CORE ) ) 448 #define GFX_IS_GEN_12_OR_LATER(p) (( GFX_GET_CURRENT_RENDERCORE(p) >= IGFX_GEN12_CORE )) 449 #define GFX_IS_ATOM_PRODUCT_FAMILY(p) ( GFX_IS_PRODUCT(p, IGFX_VALLEYVIEW) || \ 450 GFX_IS_PRODUCT(p, IGFX_CHERRYVIEW) || \ 451 GFX_IS_PRODUCT(p, IGFX_BROXTON) ) 452 453 /////////////////////////////////////////////////////////////////// 454 // 455 // macros for comparing Graphics family and products 456 // 457 /////////////////////////////////////////////////////////////////// 458 #define GFX_IS_FAMILY_EQUAL_OR_ABOVE(family1, family2) ((family1)>=(family2) ? true : false) 459 #define GFX_IS_FAMILY_EQUAL_OR_BELOW(family1, family2) ((family1)<=(family2) ? true : false) 460 #define GFX_IS_FAMILY_BELOW(family1, family2) ((family1)<(family2) ? true : false) 461 #define GFX_IS_PRODUCT_EQUAL_OR_ABOVE(product1, product2) ((product1)>=(product2) ? true : false) 462 #define GFX_IS_PRODUCT_EQUAL_OR_BELOW(product1, product2) ((product1)<=(product2) ? true : false) 463 #define GFX_IS_PRODUCT_BELOW(product1, product2) ((product1) <(product2) ? true : false) 464 465 //Feature ID: Graphics PRD PC11.0 - Brookdale-G Support 466 //Description: Move device and vendor ID's to igfxfmid.h. 467 // Add #include "igfxfmid.h". 468 //Other Files Modified: dispconf.c, kcconfig.c, kchmisc.c, kchsys.c, 469 // driver.h, igfxfmid.h, imdefs.h, kchialm.h, kchname.h, softbios.h, 470 // swbios.h, vddcomm.h, vidmini.h 471 472 #define INTEL_VENDOR_ID 0x8086 // Intel Corporation 473 474 //Device IDs 475 #define UNKNOWN_DEVICE_ID 0xFFFF // Unknown device 476 #define IALM_DEVICE0_ID_M 0x3575 477 #define IALM_DEVICE0_ID_MG 0x3578 478 #define IALM_DEVICE1_ID 0x3576 479 #define IALM_DEVICE_ID 0x3577 // Almador Base 480 #define BROOKDALE_G_DEVICE_ID 0x2562 // Brookdale_G 481 #define IMGM_DEVICE_ID 0x3582 // MontaraGM Base 482 #define IMGM_DEVICE0_ID 0x3580 483 #define ISDG_DEVICE0_ID 0x2570 // Springdale-G Device 0 ID 484 #define ISDG_DEVICE1_ID 0x2571 // Springdale-G Device 1 ID 485 #define ISDG_DEVICE2_ID 0x2572 // Springdale-G Device 2 ID 486 #define ISDG_DEVICE_ID ISDG_DEVICE2_ID // Springdale-G Graphics Controller Device ID 487 #define IGDG_DEVICE_F0_ID 0x2582 // Grantsdale-G graphics function 0 ID 488 #define IGDG_DEVICE_F1_ID 0x2782 // Grantsdale-G graphics function 1 ID 489 #define IALG_DEVICE_F0_ID 0x2592 // Alviso-G , function 0 490 #define IALG_DEVICE_F1_ID 0x2792 // Alviso-G , function 1 491 492 #define ILPG_DEVICE_F0_ID 0x2772 // Lakeport-G graphics function 0 ID 493 #define ILPG_DEVICE_F1_ID 0x2776 // Lakeport-G graphics function 1 ID 494 495 #define ICLG_DEVICE_F0_ID 0x27A2 // Calistoga-G graphics function 0 ID 496 #define ICLG_DEVICE_F1_ID 0x27A6 // Calistoga-G graphics function 1 ID 497 #define ICLG_GME_DEVICE_F0_ID 0x27AE // Calistoga-G graphics function 0 ID for GME SKU 498 499 #define IBWG_DEVICE_F0_ID 0x2982 // Broadwater-G graphics function 0 ID 500 #define IBWG_DEVICE_F1_ID 0x2983 // Broadwater-G graphics function 1 ID 501 502 #define IBWG_GQ_DEVICE_F0_ID 0x2992 // Broadwater-GQ graphics function 0 ID 503 #define IBWG_GQ_DEVICE_F1_ID 0x2993 // Broadwater-GQ graphics function 1 ID 504 505 #define IBWG_GC_DEVICE_F0_ID 0x29A2 // Broadwater-GC graphics function 0 ID 506 #define IBWG_GC_DEVICE_F1_ID 0x29A3 // Broadwater-GC graphics function 1 ID 507 508 #define IBWG_GV_DEVICE_F0_ID 0x2972 // Broadwater-GL/GZ graphics function 0 ID 509 #define IBWG_GV_DEVICE_F1_ID 0x2973 // Broadwater-GL/GZ graphics function 1 ID 510 511 #define ICRL_DEVICE_F0_ID 0x2A02 // Crestline-G graphics function 0 ID 512 #define ICRL_DEVICE_F1_ID 0x2A03 // Crestline-G graphics function 1 ID 513 #define ICRL_GME_DEVICE_F0_ID 0x2A12 // Crestline-G graphics function 0 ID for GME SKU 514 #define ICRL_GME_DEVICE_F1_ID 0x2A13 // Crestline-G graphics function 1 ID for GME SKU 515 516 #define IBLK_GBA_DEVICE_F0_ID 0x29C2 // BearLake-GBA graphics function 0 ID 517 #define IBLK_GBA_DEVICE_F1_ID 0x29C3 // BearLake-GBA graphics function 1 ID 518 519 #define IBLK_GBB_DEVICE_F0_ID 0x29B2 // BearLake-GBB Corporate skew graphics function 0 ID 520 #define IBLK_GBB_DEVICE_F1_ID 0x29B3 // BearLake-GBB Corporate skew graphics function 1 ID 521 522 #define IBLK_GBC_DEVICE_F0_ID 0x29D2 // BearLake-GBC graphics function 0 ID 523 #define IBLK_GBC_DEVICE_F1_ID 0x29D3 // BearLake-GBC graphics function 1 ID 524 525 #define ICTG_DEVICE_F0_ID 0x2A42 // Cantiga-G graphics function 0 ID 526 #define ICTG_DEVICE_F1_ID 0x2A43 // Cantiga-G graphics function 1 ID 527 528 #define ICDV_DEVICE_F0_ID 0x0BE0 // CDV graphics function 0 ID 529 #define ICDV_DEVICE_F0_ID_MASK 0xFFF0 // Mask of Penwell_D graphics function 0 ID. Bits [3:0] 530 // are used to identify SKU from B1 QS 531 532 #define IELK_DEVICE_SUPER_SKU_F0_ID 0x2E02 // EagleLake-G graphics function 0 ID for Super SKU 533 #define IELK_DEVICE_SUPER_SKU_F1_ID 0x2E03 // EagleLake-G graphics function 1 ID for Super SKU 534 535 #define IELK_DEVICE_Q45_Q43_SKU_F0_ID 0x2E12 // EagleLake-G graphics function 0 ID for Q45 and Q43 SKUs 536 #define IELK_DEVICE_Q45_Q43_SKU_F1_ID 0x2E13 // EagleLake-G graphics function 1 ID for Q45 and Q43 SKUs 537 538 #define IELK_DEVICE_G45_G43_P45_SKU_F0_ID 0x2E22 // EagleLake-G graphics function 0 ID for G45, G43 and P45 SKUs 539 #define IELK_DEVICE_G45_G43_P45_SKU_F1_ID 0x2E23 // EagleLake-G graphics function 1 ID for G45, G43 and P45 SKUs 540 541 #define IELK_DEVICE_G41_SKU_F0_ID 0x2E32 // EagleLake-G graphics function 0 ID for G41 SKU 542 #define IELK_DEVICE_G41_SKU_F1_ID 0x2E33 // EagleLake-G graphics function 1 ID for G41 SKU 543 544 #define IELK_DEVICE_F0_ID 0x2E02 // EagleLake-G graphics function 0 ID 545 #define IELK_DEVICE_F1_ID 0x2E03 // EagleLake-G graphics function 1 ID 546 547 #define IELK_DEVICE_Q45_F0_ID 0x2E12 // EagleLake-G graphics Corporate function 0 ID 548 #define IELK_DEVICE_Q45_F1_ID 0x2E13 // EagleLake-G graphics Corporate function 1 ID 549 550 #define IELK_DEVICE_Q43_F0_ID 0x2E22 // EagleLake-G graphics Corporate function 0 ID 551 #define IELK_DEVICE_Q43_F1_ID 0x2E23 // EagleLake-G graphics Corporate function 1 ID 552 553 #define IELK_DEVICE_G45_F0_ID 0x2E32 // EagleLake-G graphics function 0 ID 554 #define IELK_DEVICE_G45_F1_ID 0x2E33 // EagleLake-G graphics function 1 ID 555 556 #define IELK_DEVICE_G43_F0_ID 0x2E42 // EagleLake-G graphics function 0 ID 557 #define IELK_DEVICE_G43_F1_ID 0x2E43 // EagleLake-G graphics function 1 ID 558 559 #define IELK_DEVICE_B43_SKU_F0_ID 0x2E42 // EagleLake-G graphics function 0 ID 560 #define IELK_DEVICE_B43_SKU_F1_ID 0x2E43 // EagleLake-G graphics function 1 ID 561 562 #define IELK_DEVICE_G41_F0_ID 0x2E52 // EagleLake-G graphics function 0 ID 563 #define IELK_DEVICE_G41_F1_ID 0x2E53 // EagleLake-G graphics function 1 ID 564 565 #define IELK_DEVICE_P45_F0_ID 0x2E62 // EagleLake-G graphics function 0 ID 566 #define IELK_DEVICE_P45_F1_ID 0x2E63 // EagleLake-G graphics function 1 ID 567 568 #define IELK_DEVICE_P43_F0_ID 0x2E72 // EagleLake-G graphics function 0 ID 569 #define IELK_DEVICE_P43_F1_ID 0x2E73 // EagleLake-G graphics function 1 ID 570 571 #define IELK_DEVICE_B43_UPGRD_F0_ID 0x2E92 // EagleLake-G graphics function 0 ID 572 #define IELK_DEVICE_B43_UPGRD_F1_ID 0x2E93 // EagleLake-G graphics function 0 ID 573 574 #define IILK_DESK_DEVICE_F0_ID 0x0042 // IronLake-G Desktop graphics function 0 ID 575 #define IILK_MOBL_DEVICE_F0_ID 0x0046 // IronLake-G Mobile graphics function 0 ID 576 577 #define IGT_DESK_DEVICE_GT1_ID 0x0102 // GT / SandyBridge Desktop GT1 ID 578 #define IGT_MOBL_DEVICE_GT1_ID 0x0106 // GT / SandyBridge Mobile GT1 ID 579 #define IGT_DESK_SERVER_DEVICE_ID 0x010A // GT / SandyBridge Server ID 580 #define IGT_DESK_DEVICE_GT2_ID 0x0112 // GT / SandyBridge Desktop GT2 ID 581 #define IGT_MOBL_DEVICE_GT2_ID 0x0116 // GT / SandyBridge Mobile GT2 ID 582 #define IGT_DESK_DEVICE_GT_PLUS_ID 0x0122 // GT / SandyBridge Desktop GT2+ ID 583 #define IGT_MOBL_DEVICE_GT_PLUS_ID 0x0126 // GT / SandyBridge Mobile GT2+ ID 584 #define IGT_DESK_VERSATILE_ACCELERATION_MODE_ID 0x010B //GT / SandyBridge Versatile Acceleration Mode. Desk/Mobl?? 585 586 //ivb issue366162 587 #define IIVB_DESK_DEVICE_F0_ID 0x0162 // IVB Desktop graphics function 0 ID 588 #define IIVB_DESK_SERVER_DEVICE_ID 0x016A // IVB Server graphics function 0 ID 589 #define IIVB_MOBL_DEVICE_F0_ID 0x0166 // IVB Mobile graphics function 0 ID 590 591 #define IIVB_GT1_DESK_DEVICE_F0_ID 0x0152 // IVB Desktop graphics function 0 ID 592 #define IIVB_GT1_DESK_SERVER_DEVICE_ID 0x015A // IVB Server graphics function 0 ID 593 #define IIVB_GT1_MOBL_DEVICE_F0_ID 0x0156 // IVB Mobile graphics function 0 ID 594 595 //ivb placeholder 596 #define IIVB_GT2p_DESK_DEVICE_F0_ID 0x0172 597 #define IIVB_GT2p_MOBL_DEVICE_F0_ID 0x0176 598 599 #define IIVB_GT16_DESK_DEVICE_F0_ID 0x0182 600 #define IIVB_GT16_MOBL_DEVICE_F0_ID 0x0186 601 602 #define IIVB_GT2_XEON_DEVICE_F0_ID 0x016A 603 604 //HSW TEMP 605 #define IHSW_GTH_DESK_DEVICE_F0_ID 0x0090 // HSW Desktop graphics function 0 ID 606 #define IHSW_GTM_DESK_DEVICE_F0_ID 0x0091 607 #define IHSW_GTL_DESK_DEVICE_F0_ID 0x0092 608 #define IHSW_DESK_DEV_F0_ID 0x0C02 // HSW Desktop Device ID 609 #define IHSW_MOBL_DEV_F0_ID 0x0C06 // HSW Mobile Device ID 610 #define IHSW_DESK_DEV_F0_M_ID 0x0C12 // HSW Desktop Device ID GT - M SKU. 611 #define IHSW_MOBL_DEV_F0_M_ID 0x0C16 // HSW Mobile Device ID GT - M SKU. 612 #define IHSW_DESK_DEV_F0_H_ID 0x0C22 // HSW Desktop Device ID GT - H SKU. 613 #define IHSW_MOBL_DEV_F0_H_ID 0x0C26 // HSW Mobile Device ID GT - H SKU. 614 #define IHSW_VA_DEV_F0_ID 0x0C0B // HSW Mobile Device ID GT - H SKU. 615 616 617 #define IHSW_MOBL_DEVICE_F0_ID 0x0094 // Not used currently 618 619 //HSW - client 620 #define IHSW_CL_DESK_GT1_DEV_ID 0x402 //CLIENT Desktop - GT1 621 #define IHSW_CL_MOBL_GT1_DEV_ID 0x406 //CLIENT Mobile - GT1 622 #define IHSW_CL_SERV_GT1_DEV_ID 0x40A //CLIENT Server - GT1 623 #define IHSW_CL_DESK_GT2_DEV_ID 0x412 624 #define IHSW_CL_MOBL_GT2_DEV_ID 0x416 625 #define IHSW_CL_WS_GT2_DEV_ID 0x41B // Use for WS GT2 SKU, not confirmed 626 #define IHSW_CL_SERV_GT2_DEV_ID 0x41A 627 #define IHSW_CL_MRKT_GT1_5_DEV_ID 0x41E // Use for GT1.5w/12EUs AKA GT2.12 628 629 //HSW - ULT 630 631 #define IHSW_ULT_MOBL_GT1_DEV_ID 0xA06 632 #define IHSW_ULT_MOBL_GT2_DEV_ID 0xA16 //Mob ULT GT1.5 and GT2 633 #define IHSW_ULT_MOBL_GT3_DEV_ID 0xA26 634 #define IHSW_ULT_MRKT_GT3_DEV_ID 0xA2E 635 636 // HSW - ULX 637 638 #define IHSW_ULX_MOBL_GT1_DEV_ID 0xA0E 639 #define IHSW_ULX_MOBL_GT2_DEV_ID 0xA1E //Mob ULX GT1.5 and GT2 640 641 //HSW - CRW 642 643 #define IHSW_CRW_DESK_GT2_DEV_ID 0xD12 644 #define IHSW_CRW_MOBL_GT2_DEV_ID 0xD16 645 #define IHSW_CRW_DESK_GT3_DEV_ID 0xD22 646 #define IHSW_CRW_MOBL_GT3_DEV_ID 0xD26 647 #define IHSW_CRW_SERV_GT3_DEV_ID 0xD2A 648 649 //VLV device ids 650 #define IVLV_DESK_DEVICE_F0_ID 0x0F32 651 #define IVLV_MOBL_DEVICE_F0_ID 0x0F30 // VLV Mobile graphics function 0 ID 652 //VLV Plus device ids 653 #define IVLV_PLUS_DESK_DEVICE_F0_ID 0x0F33 654 #define IVLV_PLUS_MOBL_DEVICE_F0_ID 0x0F31 // VLV Plus Mobile graphics function 0 ID 655 656 //CHV device ids 657 #define ICHV_MOBL_DEVICE_F0_ID 0x22B0 // CHV TABLET i.e CHT 658 #define ICHV_PLUS_MOBL_DEVICE_F0_ID 0x22B1 // Essential i.e Braswell 659 #define ICHV_DESK_DEVICE_F0_ID 0x22B2 // Reserved 660 #define ICHV_PLUS_DESK_DEVICE_F0_ID 0x22B3 // Reserved 661 662 //BDW device ids 663 #define IBDW_GT1_HALO_MOBL_DEVICE_F0_ID 0x1602 664 #define IBDW_GT1_ULT_MOBL_DEVICE_F0_ID 0x1606 665 #define IBDW_GT1_RSVD_DEVICE_F0_ID 0x160B 666 #define IBDW_GT1_SERV_DEVICE_F0_ID 0x160A 667 #define IBDW_GT1_WRK_DEVICE_F0_ID 0x160D 668 #define IBDW_GT1_ULX_DEVICE_F0_ID 0x160E 669 #define IBDW_GT2_HALO_MOBL_DEVICE_F0_ID 0x1612 670 #define IBDW_GT2_ULT_MOBL_DEVICE_F0_ID 0x1616 671 #define IBDW_GT2_RSVD_DEVICE_F0_ID 0x161B 672 #define IBDW_GT2_SERV_DEVICE_F0_ID 0x161A 673 #define IBDW_GT2_WRK_DEVICE_F0_ID 0x161D 674 #define IBDW_GT2_ULX_DEVICE_F0_ID 0x161E 675 #define IBDW_GT3_HALO_MOBL_DEVICE_F0_ID 0x1622 676 #define IBDW_GT3_ULT_MOBL_DEVICE_F0_ID 0x1626 677 #define IBDW_GT3_ULT25W_MOBL_DEVICE_F0_ID 0x162B //This is actually 28w 678 #define IBDW_GT3_SERV_DEVICE_F0_ID 0x162A 679 #define IBDW_GT3_WRK_DEVICE_F0_ID 0x162D 680 #define IBDW_GT3_ULX_DEVICE_F0_ID 0x162E 681 #define IBDW_RSVD_MRKT_DEVICE_F0_ID 0x1632 682 #define IBDW_RSVD_ULT_MOBL_DEVICE_F0_ID 0x1636 683 #define IBDW_RSVD_HALO_MOBL_DEVICE_F0_ID 0x163B 684 #define IBDW_RSVD_SERV_DEVICE_F0_ID 0x163A 685 #define IBDW_RSVD_WRK_DEVICE_F0_ID 0x163D 686 #define IBDW_RSVD_ULX_DEVICE_F0_ID 0x163E 687 688 //skl placeholder 689 690 #define ISKL_GT4_DT_DEVICE_F0_ID 0x1932 691 #define ISKL_GT2_DT_DEVICE_F0_ID 0x1912 // Used on actual Silicon 692 693 #define ISKL_GT1_DT_DEVICE_F0_ID 0x1902 694 695 696 #define ISKL_GT2_ULT_DEVICE_F0_ID 0x1916 697 #define ISKL_GT2F_ULT_DEVICE_F0_ID 0x1921 698 #define ISKL_GT3e_ULT_DEVICE_F0_ID_540 0x1926 699 #define ISKL_GT3e_ULT_DEVICE_F0_ID_550 0x1927 700 701 #define ISKL_GT2_ULX_DEVICE_F0_ID 0x191E 702 #define ISKL_GT1_ULT_DEVICE_F0_ID 0x1906 703 #define ISKL_GT3_MEDIA_SERV_DEVICE_F0_ID 0x192D 704 #define ISKL_GT1_5_ULT_DEVICE_F0_ID 0x1913 705 706 #define ISKL_GT3_ULT_DEVICE_F0_ID 0x1923 707 708 #define ISKL_GT2_HALO_MOBL_DEVICE_F0_ID 0x191B 709 710 #define ISKL_GT4_HALO_MOBL_DEVICE_F0_ID 0x193B 711 #define ISKL_GT4_SERV_DEVICE_F0_ID 0x193A 712 #define ISKL_GT2_WRK_DEVICE_F0_ID 0x191D 713 #define ISKL_GT4_WRK_DEVICE_F0_ID 0x193D 714 715 716 #define ISKL_GT0_DESK_DEVICE_F0_ID 0x0900 717 #define ISKL_GT1_DESK_DEVICE_F0_ID 0x0901 718 #define ISKL_GT2_DESK_DEVICE_F0_ID 0x0902 719 #define ISKL_GT3_DESK_DEVICE_F0_ID 0x0903 720 #define ISKL_GT4_DESK_DEVICE_F0_ID 0x0904 721 #define ISKL_GT1_ULX_DEVICE_F0_ID 0x190E 722 //SKL strings to be be deleted in future 723 724 #define ISKL_GT1_HALO_MOBL_DEVICE_F0_ID 0x190B 725 #define ISKL_GT1_SERV_DEVICE_F0_ID 0x190A 726 #define ISKL_GT1_5_ULX_DEVICE_F0_ID 0x1915 727 #define ISKL_GT1_5_DT_DEVICE_F0_ID 0x1917 728 #define ISKL_GT2_SERV_DEVICE_F0_ID 0x191A 729 #define ISKL_LP_DEVICE_F0_ID 0x9905 730 #define ISKL_GT3_HALO_MOBL_DEVICE_F0_ID 0x192B 731 #define ISKL_GT3_SERV_DEVICE_F0_ID 0x192A 732 #define ISKL_GT0_MOBL_DEVICE_F0_ID 0xFFFF 733 734 735 736 737 738 // KabyLake Device ids 739 #define IKBL_GT1_ULT_DEVICE_F0_ID 0x5906 740 #define IKBL_GT1_5_ULT_DEVICE_F0_ID 0x5913 741 #define IKBL_GT2_ULT_DEVICE_F0_ID 0x5916 742 #define IKBL_GT2F_ULT_DEVICE_F0_ID 0x5921 743 #define IKBL_GT2_R_ULX_DEVICE_F0_ID 0x591C 744 #define IKBL_GT3_15W_ULT_DEVICE_F0_ID 0x5926 745 //#define IKBL_GT3E_ULT_DEVICE_F0_ID 0x5926 746 #define IKBL_GT1_ULX_DEVICE_F0_ID 0x590E 747 #define IKBL_GT1_5_ULX_DEVICE_F0_ID 0x5915 748 #define IKBL_GT2_ULX_DEVICE_F0_ID 0x591E 749 #define IKBL_GT1_DT_DEVICE_F0_ID 0x5902 750 #define IKBL_GT2_R_ULT_DEVICE_F0_ID 0x5917 751 #define IKBL_GT2_DT_DEVICE_F0_ID 0x5912 752 #define IKBL_GT1_HALO_DEVICE_F0_ID 0x590B 753 #define IKBL_GT1F_HALO_DEVICE_F0_ID 0x5908 754 #define IKBL_GT2_HALO_DEVICE_F0_ID 0x591B 755 #define IKBL_GT4_HALO_DEVICE_F0_ID 0x593B 756 #define IKBL_GT1_SERV_DEVICE_F0_ID 0x590A 757 #define IKBL_GT2_SERV_DEVICE_F0_ID 0x591A 758 #define IKBL_GT2_WRK_DEVICE_F0_ID 0x591D 759 #define IKBL_GT3_ULT_DEVICE_F0_ID 0x5923 760 #define IKBL_GT3_28W_ULT_DEVICE_F0_ID 0x5927 761 //keeping the below ids as its been used in linux . need to be removed once removed from linux files. 762 #define IKBL_GT4_DT_DEVICE_F0_ID 0x5932 763 #define IKBL_GT3_HALO_DEVICE_F0_ID 0x592B 764 #define IKBL_GT3_SERV_DEVICE_F0_ID 0x592A 765 #define IKBL_GT4_SERV_DEVICE_F0_ID 0x593A 766 #define IKBL_GT4_WRK_DEVICE_F0_ID 0x593D 767 768 //GLK Device ids 769 #define IGLK_GT2_ULT_18EU_DEVICE_F0_ID 0x3184 770 #define IGLK_GT2_ULT_12EU_DEVICE_F0_ID 0x3185 771 772 //GWL 773 #define IGWL_GT1_MOB_DEVICE_F0_ID 0xFF0F //For Pre-Si, temp 774 775 #define IBXT_A_DEVICE_F0_ID 0x9906 776 #define IBXT_C_DEVICE_F0_ID 0x9907 777 #define IBXT_X_DEVICE_F0_ID 0x9908 778 779 //BXT BIOS programmed Silicon ids 780 #define IBXT_GT_3x6_DEVICE_ID 0x0A84 781 #define IBXT_PRO_3x6_DEVICE_ID 0x1A84 //18EU 782 #define IBXT_PRO_12EU_3x6_DEVICE_ID 0x1A85 //12 EU 783 #define IBXT_P_3x6_DEVICE_ID 0x5A84 //18EU APL 784 #define IBXT_P_12EU_3x6_DEVICE_ID 0x5A85 //12EU APL 785 786 #define ICNL_3x8_DESK_DEVICE_F0_ID 0x0A01 787 #define ICNL_5x8_DESK_DEVICE_F0_ID 0x0A02 788 #define ICNL_9x8_DESK_DEVICE_F0_ID 0x0A05 789 #define ICNL_13x8_DESK_DEVICE_F0_ID 0x0A07 790 791 // CNL Si device ids 792 #define ICNL_5x8_ULX_DEVICE_F0_ID 0x5A51 //GT2 793 #define ICNL_5x8_ULT_DEVICE_F0_ID 0x5A52 //GT2 794 #define ICNL_4x8_ULT_DEVICE_F0_ID 0x5A5A //GT1.5 795 #define ICNL_3x8_ULT_DEVICE_F0_ID 0x5A42 //GT1 796 #define ICNL_2x8_ULT_DEVICE_F0_ID 0x5A4A //GT0.5 797 #define ICNL_9x8_ULT_DEVICE_F0_ID 0x5A62 798 #define ICNL_9x8_SUPERSKU_DEVICE_F0_ID 0x5A60 799 #define ICNL_5x8_SUPERSKU_DEVICE_F0_ID 0x5A50 //GT2 800 #define ICNL_1x6_5x8_SUPERSKU_DEVICE_F0_ID 0x5A40 //GTx 801 #define ICNL_5x8_HALO_DEVICE_F0_ID 0x5A54 //GT2 802 #define ICNL_3x8_HALO_DEVICE_F0_ID 0x5A44 //GT1 803 #define ICNL_5x8_DESKTOP_DEVICE_F0_ID 0x5A55 804 #define ICNL_3x8_DESKTOP_DEVICE_F0_ID 0x5A45 805 #define ICNL_4x8_ULX_DEVICE_F0_ID 0x5A59 //GT1.5 806 #define ICNL_3x8_ULX_DEVICE_F0_ID 0x5A41 //GT1 807 #define ICNL_2x8_ULX_DEVICE_F0_ID 0x5A49 //GT0.5 808 #define ICNL_4x8_HALO_DEVICE_F0_ID 0x5A5C //GT1.5 809 #define ICNL_2x8_HALO_DEVICE_F0_ID 0x5A4C //GT0.5 810 811 //CFL 812 #define ICFL_GT1_DT_DEVICE_F0_ID 0x3E90 813 #define ICFL_GT2_DT_DEVICE_F0_ID 0x3E92 814 815 #define ICFL_GT1_S61_DT_DEVICE_F0_ID 0x3E90 816 #define ICFL_GT1_S41_DT_DEVICE_F0_ID 0x3E93 817 #define ICFL_GT2_S62_DT_DEVICE_F0_ID 0x3E92 818 #define ICFL_GT2_HALO_DEVICE_F0_ID 0x3E9B 819 #define ICFL_GT2_SERV_DEVICE_F0_ID 0x3E96 820 #define ICFL_GT2_HALO_WS_DEVICE_F0_ID 0x3E94 821 #define ICFL_GT2_S42_DT_DEVICE_F0_ID 0x3E91 822 #define ICFL_GT3_ULT_15W_DEVICE_F0_ID 0x3EA6 823 #define ICFL_GT3_ULT_15W_42EU_DEVICE_F0_ID 0x3EA7 824 #define ICFL_GT3_ULT_28W_DEVICE_F0_ID 0x3EA8 825 #define ICFL_GT3_ULT_DEVICE_F0_ID 0x3EA5 826 #define ICFL_HALO_DEVICE_F0_ID 0x3E95 827 #define ICFL_GT2_S8_S2_DT_DEVICE_F0_ID 0x3E98 828 #define ICFL_GT1_S6_S4_S2_F1F_DT_DEVICE_F0_ID 0x3E99 829 #define ICFL_GT2_S82_S6F2_DT_DEVICE_F0_ID 0x3E9A 830 #define ICFL_GT2_U42F_U2F2_ULT_DEVICE_F0_ID 0x3EA0 831 #define ICFL_GT1_U41F_U2F1F_ULT_DEVICE_F0_ID 0x3EA1 832 #define ICFL_GT3_U43_ULT_DEVICE_F0_ID 0x3EA2 833 #define ICFL_GT2_U42F_U2F1F_ULT_DEVICE_F0_ID 0x3EA3 834 #define ICFL_GT1_41F_2F1F_ULT_DEVICE_F0_ID 0x3EA4 835 #define ICFL_GT2_U42F_U2F2F_ULT_DEVICE_F0_ID 0x3EA9 836 837 //CML- continue to follow CFL Macro 838 #define ICFL_GT2_ULT_DEVICE_V0_ID 0x9B41 839 #define ICFL_GT1_ULT_DEVICE_V0_ID 0x9B21 840 #define ICFL_GT2_ULT_DEVICE_A0_ID 0x9BCA 841 #define ICFL_GT1_ULT_DEVICE_A0_ID 0x9BAA 842 #define ICFL_GT2_ULT_DEVICE_S0_ID 0x9BCB 843 #define ICFL_GT1_ULT_DEVICE_S0_ID 0x9BAB 844 #define ICFL_GT2_ULT_DEVICE_K0_ID 0x9BCC 845 #define ICFL_GT1_ULT_DEVICE_K0_ID 0x9BAC 846 #define ICFL_GT2_ULX_DEVICE_S0_ID 0x9BC0 847 #define ICFL_GT1_ULX_DEVICE_S0_ID 0x9BA0 848 #define ICFL_GT2_DT_DEVICE_P0_ID 0x9BC5 849 #define ICFL_GT1_DT_DEVICE_P0_ID 0x9BA5 850 #define ICFL_GT2_DT_DEVICE_G0_ID 0x9BC8 851 #define ICFL_GT1_DT_DEVICE_G0_ID 0x9BA8 852 #define ICFL_GT2_WKS_DEVICE_P0_ID 0x9BC6 853 #define ICFL_GT2_WKS_DEVICE_G0_ID 0x9BE6 854 #define ICFL_GT2_HALO_DEVICE_15_ID 0x9BC4 855 #define ICFL_GT1_HALO_DEVICE_16_ID 0x9BA4 856 #define ICFL_GT2_HALO_DEVICE_17_ID 0x9BC2 857 #define ICFL_GT1_HALO_DEVICE_18_ID 0x9BA2 858 859 860 861 862 // PCH related definitions 863 #define PCH_IBX_DESK_DEVICE_FULL_ID 0x3B00 864 #define PCH_IBX_DESK_DEVICE_P55_ID 0x3B02 865 #define PCH_IBX_DESK_DEVICE_H55_ID 0x3B06 866 #define PCH_IBX_DESK_DEVICE_H57_ID 0x3B08 867 #define PCH_IBX_DESK_DEVICE_Q57_ID 0x3B0A 868 869 #define PCH_IBX_MOBL_DEVICE_FULL_ID 0x3B01 870 #define PCH_IBX_MOBL_DEVICE_PM55_ID 0x3B03 871 #define PCH_IBX_MOBL_DEVICE_QM57_ID 0x3B07 872 #define PCH_IBX_MOBL_DEVICE_HM55_ID 0x3B09 873 #define PCH_IBX_MOBL_DEVICE_HM57_ID 0x3B0B 874 #define PCH_IBX_MOBL_DEVICE_SFF_FULL_ID 0x3B0D 875 876 #define PCH_IBX_DEVICE_QS57_ID 0x3B0F 877 #define PCH_IBX_DEVICE_3400_ID 0x3B12 878 #define PCH_IBX_DEVICE_3420_ID 0x3B14 879 #define PCH_IBX_DEVICE_3450_ID 0x3B16 880 881 #define PCH_CPT_UNFUSED_PART_DEV_ID 0x1C40 882 #define PCH_CPT_DESKTOP_SUPER_SKU_DEV_ID 0x1C42 883 #define PCH_CPT_MOBL_SUPER_SKU_DEV_ID 0x1C43 884 #define PCH_CPT_DESKTOP_DH_SKU_DEV_ID 0x1C44 885 #define PCH_CPT_DESKTOP_DO_SKU_DEV_ID 0x1C46 886 #define PCH_CPT_MOBL_DO_SKU_DEV_ID 0x1C47 887 #define PCH_CPT_DESKTOP_R_SKU_DEV_ID 0x1C48 888 #define PCH_CPT_MOBL_ENHANCED_SKU_DEV_ID 0x1C49 889 #define PCH_CPT_DESKTOP_BASE_SKU_DEV_ID 0x1C4A 890 #define PCH_CPT_MOBL_BASE_SKU_DEV_ID 0x1C4B 891 #define PCH_CPT_Q65_SKU_DEV_ID 0x1C4C 892 #define PCH_CPT_QS67_SKU_DEV_ID 0x1C4D 893 #define PCH_CPT_Q67_SKU_DEV_ID 0x1C4E 894 #define PCH_CPT_QM67_SKU_DEV_ID 0x1C4F 895 #define PCH_CPT_B65_SKU_DEV_ID 0x1C50 896 #define PCH_CPT_ESSENTIAL_SKU_DEV_ID 0x1C52 897 #define PCH_CPT_STANDARD_SKU_DEV_ID 0x1C54 898 #define PCH_CPT_ADVANCED_SKU_DEV_ID 0x1C56 899 #define PCH_CPT_B65_SKU_LEVEL_III_DEV_ID 0x1C58 900 #define PCH_CPT_HM67_SKU_LEVEL_III_DEV_ID 0x1C59 901 #define PCH_CPT_Q67_SKU_LEVEL_I_DEV_ID 0x1C5A 902 #define PCH_CPT_H61_SKU_LEVEL_I_DEV_ID 0x1C5C 903 904 // CPT Refresh Device IDs.. 905 #define PCH_CPT_REF_RSVD1_DEV_ID 0x1CC0 //Reserved for future use 906 #define PCH_CPT_REF_MOB_SFF_SUPER_DEV_ID 0x1CC1 907 #define PCH_CPT_REF_MOB_SUPER_DEV_ID 0x1CC2 908 #define PCH_CPT_REF_RSVD2_DEV_ID 0x1CC3 //Reserved for future use 909 #define PCH_CPT_REF_QM77_DEV_ID 0x1CC4 910 #define PCH_CPT_REF_QS77_DEV_ID 0x1CC5 911 #define PCH_CPT_REF_HM77_DEV_ID 0x1CC6 912 #define PCH_CPT_REF_UM77_DEV_ID 0x1CC7 913 #define PCH_CPT_REF_HM75_DEV_ID 0x1CC8 914 #define PCH_CPT_REF_HM75_RAID_RST_DEV_ID 0x1CC9 915 #define PCH_CPT_REF_UM77_RAID_RST_DEV_ID 0x1CCA 916 #define PCH_CPT_REF_HM77_MNG_DEV_ID 0x1CCB 917 #define PCH_CPT_REF_RSVD3_DEV_ID 0x1CCC 918 #define PCH_CPT_REF_RSVD4_DEV_ID 0x1CCD 919 #define PCH_CPT_REF_RSVD5_DEV_ID 0x1CCE 920 #define PCH_CPT_REF_RSVD6_DEV_ID 0x1CCF 921 #define PCH_CPT_REF_RSVD7_DEV_ID 0x1CD0 922 #define PCH_CPT_REF_RSVD8_DEV_ID 0x1CD1 923 #define PCH_CPT_REF_RSVD9_DEV_ID 0x1CD2 924 #define PCH_CPT_REF_RSVD10_DEV_ID 0x1CD3 925 #define PCH_CPT_REF_RSVD11_DEV_ID 0x1CD4 926 #define PCH_CPT_REF_RSVD12_DEV_ID 0x1CD5 927 #define PCH_CPT_REF_RSVD13_DEV_ID 0x1CD6 928 #define PCH_CPT_REF_RSVD14_DEV_ID 0x1CD7 929 #define PCH_CPT_REF_RSVD15_DEV_ID 0x1CD8 930 #define PCH_CPT_REF_RSVD16_DEV_ID 0x1CD9 931 #define PCH_CPT_REF_RSVD17_DEV_ID 0x1CDA 932 #define PCH_CPT_REF_RSVD18_DEV_ID 0x1CDB 933 #define PCH_CPT_REF_RSVD19_DEV_ID 0x1CDC 934 #define PCH_CPT_REF_RSVD20_DEV_ID 0x1CDD 935 #define PCH_CPT_REF_RSVD21_DEV_ID 0x1CDE 936 #define PCH_CPT_REF_RSVD22_DEV_ID 0x1CDF 937 938 939 940 //PPT Device IDs.. 941 #define PCH_PPT_DEV_ID 0x1E40 942 #define PCH_PPT_DESK_SUPER_DEV_ID 0x1E41 943 #define PCH_PPT_MOB_SUPER_DEV_ID 0x1E42 944 #define PCH_PPT_MOB_SFF_SUPER_DEV_ID 0x1E43 945 #define PCH_PPT_Z7x_DEV_ID 0x1E44 946 #define PCH_PPT_H71_DEV_ID 0x1E45 947 #define PCH_PPT_P77_DEV_ID 0x1E46 948 #define PCH_PPT_Q77_DEV_ID 0x1E47 949 #define PCH_PPT_Q75_DEV_ID 0x1E48 950 #define PCH_PPT_B75_DEV_ID 0x1E49 951 #define PCH_PPT_H77_DEV_ID 0x1E4A 952 #define PCH_PPT_B75_MNG_DEV_ID 0x1E4B 953 #define PCH_PPT_B75_RAID_RST_DEV_ID 0x1E4C 954 #define PCH_PPT_B75_RAID_RST_MNG_DEV_ID 0x1E4D 955 #define PCH_PPT_H77_RST_DEV_ID 0x1E4E 956 #define PCH_PPT_P77_RST_DEV_ID 0x1E4F 957 #define PCH_PPT_Q77_RST_DEV_ID 0x1E50 958 #define PCH_PPT_H71_RAID_RST_DEV_ID 0x1E51 959 #define PCH_PPT_Q75_RAID_RST_DEV_ID 0x1E52 960 #define PCH_PPT_SERVER_DEV_ID 0x1E53 961 #define PCH_PPT_RSVD1_DEV_ID 0x1E54 962 #define PCH_PPT_QM78_DEV_ID 0x1E55 963 #define PCH_PPT_QS78_DEV_ID 0x1E56 964 #define PCH_PPT_HM78_DEV_ID 0x1E57 965 #define PCH_PPT_UM78_DEV_ID 0x1E58 966 #define PCH_PPT_HM76_DEV_ID 0x1E59 967 #define PCH_PPT_HM76_RAID_RST_DEV_ID 0x1E5A 968 #define PCH_PPT_UM78_RAID_RST_DEV_ID 0x1E5B 969 #define PCH_PPT_HM78_MNG_DEV_ID 0x1E5C 970 #define PCH_PPT_DEV_RSVD2_USB1_ID 0x1E5D 971 #define PCH_PPT_DEV_RSVD3_USB2_ID 0x1E5E 972 #define PCH_PPT_DEV_RSVD4_ID 0x1E5F 973 974 //define LPT device ids 975 #define PCH_LPT_DEV_ID 0x8C40 976 #define PCH_LPT_DESK_SUPER_DEV_ID 0x8C41 977 #define PCH_LPT_MOB_SUPER_DEV_ID 0x8C42 978 #define PCH_LPT_DEV_RSVD1_ID 0x8C43 979 #define PCH_LPT_Z87_DEV_ID 0x8C44 980 #define PCH_LPT_DEV_RSVD2_ID 0x8C45 981 #define PCH_LPT_Z85_DEV_ID 0x8C46 982 #define PCH_LPT_DEV_RSVD3_ID 0x8C47 983 #define PCH_LPT_DEV_RSVD4_ID 0x8C48 984 #define PCH_LPT_HM86_DEV_ID 0x8C49 985 #define PCH_LPT_H87DEV_ID 0x8C4A 986 #define PCH_LPT_HM87_DEV_ID 0x8C4B 987 #define PCH_LPT_Q85_DEV_ID 0x8C4C 988 #define PCH_LPT_DEV_RSVD5_ID 0x8C4D 989 #define PCH_LPT_Q87_DEV_ID 0x8C4E 990 #define PCH_LPT_QM87_DEV_ID 0x8C4F 991 #define PCH_LPT_B85_DEV_ID 0x8C50 992 #define PCH_LPT_DEV_RSVD6_ID 0x8C51 993 #define PCH_LPT_SERVER_ESS_DEV_ID 0x8C52 994 #define PCH_LPT_DEV_RSVD7_ID 0x8C53 995 #define PCH_LPT_SERVER_STD_DEV_ID 0x8C54 996 #define PCH_LPT_DEV_RSVD8_ID 0x8C55 997 #define PCH_LPT_SERVER_ADV_DEV_ID 0x8C56 998 #define PCH_LPT_DEV_RSVD9_ID 0x8C57 999 #define PCH_LPT_WS_DEV_ID 0x8C58 1000 #define PCH_LPT_DEV_RSVD10_ID 0x8C59 1001 #define PCH_LPT_DEV_RSVD11_ID 0x8C5A 1002 #define PCH_LPT_DEV_RSVD12_ID 0x8C5B 1003 #define PCH_LPT_H81_DEV_ID 0x8C5C 1004 #define PCH_LPT_DEV_RSVD13_ID 0x8C5D 1005 #define PCH_LPT_DEV_RSVD14_ID 0x8C5E 1006 #define PCH_LPT_DEV_RSVD15_ID 0x8C5F 1007 #define PCH_LPT_MOB_FFE_DEV_ID 0x8CC1 // D31:F0 - LPC Controller (Mobile Full Featured Engineering Sample) 1008 #define PCH_LPT_DESK_FFE_DEV_ID 0X8CC2 // D31:F0 - LPC Controller (Desktop Full Featured Engineering Sample) 1009 #define PCH_LPT_HM97_DEV_ID 0X8CC3 // D31:F0 - LPC Controller (HM97 SKU) 1010 #define PCH_LPT_Z97_DEV_ID 0X8CC4 // D31:F0 - LPC Controller (Z97 SKU) 1011 #define PCH_LPT_QM97_DEV_ID 0X8CC5 // D31:F0 - LPC Controller (QM97 SKU) 1012 #define PCH_LPT_H97_DEV_ID 0X8CC6 // D31:F0 - LPC Controller (H97 SKU) 1013 1014 #define PCH_LPT_LP_DEV_UNFUSED_ID 0x9C40 1015 #define PCH_LPT_LP_DEV_SUPER_ID 0x9C41 1016 #define PCH_LPT_LP_DEV_PREMIUM_ID 0x9C43 1017 #define PCH_LPT_LP_DEV_MAINSTREAM_ID 0x9C45 1018 #define PCH_LPT_LP_DEV_VALUE_ID 0x9C47 1019 1020 //define WPT device ids 1021 #define PCH_WPT_DEV_SIM_ID 0x99FF 1022 #define PCH_WPT_LPC_DEV_UNFUSED_ID 0x9CC0 // for BDW P0, D31:F0 - LPC Controller (Unfused part) 1023 #define PCH_WPT_LPC_DEV_SUPER_HSW_ID 0x9CC1 // for BDW P0, D31:F0 - LPC Controller (Super SKU) w/ HSW 1024 #define PCH_WPT_LPC_DEV_SUPER_BDW_U_CPU_ID 0x9CC2 // for BDW P0, D31:F0 - LPC Controller (Super SKU) w/ BDW U CPU 1025 #define PCH_WPT_LPC_DEV_PREMIUM_BDW_U_CPU_ID 0x9CC3 // for BDW P0, D31:F0 - LPC Controller (Premimum SKU) w/ BDW U CPU 1026 #define PCH_WPT_LPC_DEV_BASE_BDW_U_CPU_ID 0x9CC5 // for BDW P0, D31:F0 - LPC Controller (Base SKU) w/ BDW U CPU 1027 #define PCH_WPT_LPC_DEV_SUPER_BDW_Y_CPU_ID 0x9CC6 // for BDW P0, D31:F0 - LPC Controller (Super SKU) w/ BDW Y CPU 1028 #define PCH_WPT_LPC_DEV_PREMIUM_BDW_Y_CPU_ID 0x9CC7 // for BDW P0, D31:F0 - LPC Controller (Premimum SKU) w/ BDW Y CPU 1029 #define PCH_WPT_LPC_DEV_BASE_BDW_Y_CPU_ID 0x9CC9 // for BDW P0, D31:F0 - LPC Controller (Base SKU) w/ BDW Y CPU 1030 #define PCH_WPT_LPC_DEV_PERFORMANCE_ID 0x9CCB // for BDW P0, D31:F0 - LPC Controller (Performance SKU) 1031 1032 //define SPT LP device ids 1033 #define PCH_SPT_DEV_SIM_ID 0x99EF 1034 #define PCH_SPT_LPC_DEV_UNFUSED_ID 0x9D40 // (SPT-LP) Unfused 1035 #define PCH_SPT_LPC_DEV_SUPER_U_ID 0x9D41 // (SPT-LP) Super SKU(Unlocked) 1036 #define PCH_SPT_LPC_DEV_SUPER_L_ID 0x9D42 // (SPT-LP) Super SKU(locked) 1037 #define PCH_SPT_LPC_DEV_BASE_SKL_U_ID 0x9D43 // (SPT-LP) Base Consumer/Corp SKL-U 1038 #define PCH_SPT_LPC_DEV_P1_ID 0x9D44 // (SPT-LP) Placeholder, yet to be finalized 1039 #define PCH_SPT_LPC_DEV_P2_ID 0x9D45 // (SPT-LP) Placeholder, yet to be finalized 1040 #define PCH_SPT_LPC_DEV_PREMIUM_SKL_Y_ID 0x9D46 // (SPT-LP) Premium Consumer/Corp SKL-Y 1041 #define PCH_SPT_LPC_DEV_P3_ID 0x9D47 // (SPT-LP) Placeholder, yet to be finalized 1042 #define PCH_SPT_LPC_DEV_PREMIUM_SKL_U_ID 0x9D48 // (SPT-LP) Premium Consumer/Corp SKL-U, yet to be finalized 1043 #define PCH_SPT_DEV_PREMIUM_KBL_Y_ID 0x9D4B // (PCH-SPT) Premium Consumer/Corp KBL-Y 1044 #define PCH_SPT_DEV_PREMIUM_KBL_U_ID 0x9D4E // (PCH-SPT) Premium Consumer/Corp KBL-U 1045 1046 #define PCH_SPT_LPC_DEV_KBL_SUPERSKU_UNLOCKED_ID 0x9D51 // (SPT-LP) Super SKU Unlocked 1047 #define PCH_SPT_LPC_DEV_KBL_SUPERSKU_LOCKED_ID 0x9D52 // (SPT-LP) Super SKU locked 1048 #define PCH_SPT_LPC_DEV_PREMIUM_KBL_Y_ID 0x9D56 // (SPT-LP) Premium Consumer/Corp KBL-Y 1049 #define PCH_SPT_LPC_DEV_PREMIUM_KBL_U_ID 0x9D58 // (SPT-LP) (SPT-LP) Premium Consumer/Corp KBL-Y 1050 #define PCH_SPT_LPC_DEV_KBL_BASE_ID 0x9D53 // (SPT-LP) Base Consumer/Corp KBL-U 1051 1052 #define PCH_SPT_LPC_DEV_P4_ID 0x9D49 // (SPT-LP) Placeholder, yet to be finalized 1053 #define PCH_SPT_LPC_DEV_P5_ID 0x9D50 // (SPT-LP) Placeholder, yet to be finalized 1054 #define PCH_SPT_LPC_DEV_P6_ID 0x9D54 // (SPT-LP) Placeholder, yet to be finalized 1055 #define PCH_SPT_LPC_DEV_P7_ID 0x9D55 // (SPT-LP) Placeholder, yet to be finalized 1056 #define PCH_SPT_LPC_DEV_P8_ID 0x9D57 // (SPT-LP) Placeholder, yet to be finalized 1057 #define PCH_SPT_LPC_DEV_P9_ID 0x9D59 // (SPT-LP) Placeholder, yet to be finalized 1058 #define PCH_SPT_LPC_DEV_PA_ID 0x9D5A // (SPT-LP) Placeholder, yet to be finalized 1059 #define PCH_SPT_LPC_DEV_PB_ID 0x9D5B // (SPT-LP) Placeholder, yet to be finalized 1060 #define PCH_SPT_LPC_DEV_PC_ID 0x9D5C // (SPT-LP) Placeholder, yet to be finalized 1061 #define PCH_SPT_LPC_DEV_PD_ID 0x9D5D // (SPT-LP) Placeholder, yet to be finalized 1062 #define PCH_SPT_LPC_DEV_PE_ID 0x9D5E // (SPT-LP) Placeholder, yet to be finalized 1063 #define PCH_SPT_LPC_DEV_PF_ID 0x9D5F // (SPT-LP) Placeholder, yet to be finalized 1064 1065 1066 //define SPT Halo Device ids 1067 #define PCH_SPT_HALO_DEV_UNFUSED_ID 0xA140 // (SPT-H) Unfused 1068 #define PCH_SPT_CLIENT_UNLOCKED_ID 0xA141 // (SPT-H) SuperSKU Client UnLocked 1069 #define PCH_SPT_CLIENT_LOCKED_ID 0xA142 // (SPT-H) SuperSKU Client Locked 1070 #define PCH_SPT_HALO_DEV_H110_ID 0xA143 // (SPT-H) H110 SKU 1071 #define PCH_SPT_HALO_DEV_H170_ID 0xA144 // (SPT-H) H170 SKU 1072 #define PCH_SPT_HALO_DEV_Z170_ID 0xA145 // (SPT-H) Z170 SKU 1073 #define PCH_SPT_HALO_DEV_Q170_ID 0xA146 // (SPT-H) Q170 SKU 1074 #define PCH_SPT_HALO_DEV_Q150_ID 0xA147 // (SPT-H) Q150 SKU 1075 #define PCH_SPT_HALO_DEV_B150_ID 0xA148 // (SPT-H) B150 SKU 1076 #define PCH_SPT_HALO_DEV_C236_ID 0xA149 // (SPT-H) C236 SKU 1077 #define PCH_SPT_HALO_DEV_C232_ID 0xA14A // (SPT-H) C232 SKU 1078 #define PCH_SPT_SERVER_UNLOCKED_ID 0xA14B // (SPT-H) Super SKU Server Unlocked 1079 #define PCH_SPT_SERVER_LOCKED_ID 0xA14C // (SPT-H) Super SKU Server locked 1080 #define PCH_SPT_HALO_DEV_QM170_ID 0xA14D // (SPT-H) QM170 SKU 1081 #define PCH_SPT_HALO_DEV_HM170_ID 0xA14E // (SPT-H) HM170 SKU 1082 #define PCH_SPT_HALO_DEV_QMS170_ID 0xA14F // (SPT-H) QMS170 SKU 1083 #define PCH_SPT_HALO_DEV_CM236_ID 0xA150 // (SPT-H) CM236 SKU 1084 #define PCH_SPT_HALO_DEV_QMS180_ID 0xA151 // SPT-H QMS180 SKU 1085 #define PCH_SPT_HALO_DEV_HM172_ID 0xA152 // SPT-H HM172 SKU 1086 #define PCH_SPT_HALO_DEV_QM172_ID 0xA153 // SPT-H QM172 SKU 1087 #define PCH_SPT_HALO_DEV_CM238_ID 0xA154 // SPT-H CM238 SKU 1088 #define PCH_SPT_HALO_DEV_P1_ID 0xA155 // Placeholder, yet to be finalized 1089 #define PCH_SPT_HALO_DEV_P2_ID 0xA156 // Placeholder, yet to be finalized 1090 #define PCH_SPT_HALO_DEV_P3_ID 0xA157 // Placeholder, yet to be finalized 1091 #define PCH_SPT_HALO_DEV_P4_ID 0xA158 // Placeholder, yet to be finalized 1092 #define PCH_SPT_HALO_DEV_P5_ID 0xA159 // Placeholder, yet to be finalized 1093 #define PCH_SPT_HALO_DEV_P6_ID 0xA15A // Placeholder, yet to be finalized 1094 #define PCH_SPT_HALO_DEV_P7_ID 0xA15B // Placeholder, yet to be finalized 1095 #define PCH_SPT_HALO_DEV_P8_ID 0xA15C // Placeholder, yet to be finalized 1096 #define PCH_SPT_HALO_DEV_P9_ID 0xA15D // Placeholder, yet to be finalized 1097 #define PCH_SPT_HALO_DEV_PA_ID 0xA15E // Placeholder, yet to be finalized 1098 #define PCH_SPT_HALO_DEV_PB_ID 0xA15F // Placeholder, yet to be finalized 1099 1100 1101 1102 1103 //define KBP Halo Device Ids 1104 #define PCH_KBP_HALO_DEV_P1_ID 0xA280 1105 #define PCH_KBP_HALO_DEV_P2_ID 0xA281 1106 #define PCH_KBP_HALO_DEV_P3_ID 0xA282 1107 #define PCH_KBP_HALO_DEV_P4_ID 0xA283 1108 #define PCH_KBP_HALO_DEV_P5_ID 0xA284 1109 #define PCH_KBP_HALO_DEV_P6_ID 0xA285 1110 #define PCH_KBP_HALO_DEV_P7_ID 0xA286 1111 #define PCH_KBP_HALO_DEV_P8_ID 0xA287 1112 #define PCH_KBP_HALO_DEV_P9_ID 0xA288 1113 #define PCH_KBP_HALO_DEV_PA_ID 0xA289 1114 #define PCH_KBP_HALO_DEV_PB_ID 0xA28A 1115 #define PCH_KBP_HALO_DEV_PC_ID 0xA28B 1116 #define PCH_KBP_HALO_DEV_PD_ID 0xA28C 1117 #define PCH_KBP_HALO_DEV_PE_ID 0xA28D 1118 #define PCH_KBP_HALO_DEV_PF_ID 0xA28E 1119 #define PCH_KBP_HALO_DEV_P10_ID 0xA28F 1120 #define PCH_KBP_HALO_DEV_P11_ID 0xA290 1121 #define PCH_KBP_HALO_DEV_P12_ID 0xA291 1122 #define PCH_KBP_HALO_DEV_P13_ID 0xA292 1123 #define PCH_KBP_HALO_DEV_P14_ID 0xA293 1124 #define PCH_KBP_HALO_DEV_P15_ID 0xA294 1125 #define PCH_KBP_HALO_DEV_P16_ID 0xA295 1126 #define PCH_KBP_HALO_DEV_P17_ID 0xA296 1127 #define PCH_KBP_HALO_DEV_P18_ID 0xA297 1128 #define PCH_KBP_HALO_DEV_P19_ID 0xA298 1129 #define PCH_KBP_HALO_DEV_P1A_ID 0xA299 1130 #define PCH_KBP_HALO_DEV_P1B_ID 0xA29A 1131 #define PCH_KBP_HALO_DEV_P1C_ID 0xA29B 1132 #define PCH_KBP_HALO_DEV_P1D_ID 0xA29C 1133 #define PCH_KBP_HALO_DEV_P1E_ID 0xA29D 1134 #define PCH_KBP_HALO_DEV_P1F_ID 0xA29E 1135 #define PCH_KBP_HALO_DEV_P20_ID 0xA29F 1136 1137 #define PCH_KBP_HALO_ES_SUPER_SKU_CLIENT 0xA2C0 1138 #define PCH_KBP_HALO_ES_SUPER_SKU_SERVER 0xA2CE 1139 #define PCH_KBP_SUPERSKU_CLIENT_ID 0xA2C1 1140 #define PCH_KBP_S_DEV_P0_ID 0xA2C2 1141 #define PCH_KBP_S_DEV_P1_ID 0xA2C3 1142 #define PCH_KBP_S_H270_ID 0xA2C4 1143 #define PCH_KBP_S_Z270_ID 0xA2C5 1144 #define PCH_KBP_S_Q270_ID 0xA2C6 1145 #define PCH_KBP_S_Q250_ID 0xA2C7 1146 #define PCH_KBP_S_B250_ID 0xA2C8 1147 #define PCH_KBP_S_DEV_P2_ID 0xA2C9 1148 #define PCH_KBP_S_DEV_P3_ID 0xA2CA 1149 #define PCH_KBP_S_DEV_P4_ID 0xA2CB 1150 #define PCH_KBP_S_DEV_P5_ID 0xA2CC 1151 #define PCH_KBP_S_DEV_P6_ID 0xA2CD 1152 #define PCH_KBP_SUPERSKU_SERVER_ID 0xA2CF 1153 1154 1155 1156 //define CNL LP PCH Device Ids 1157 #define PCH_CNP_LP_DEV_P1_ID 0x9D80 1158 #define PCH_CNP_LP_DEV_P2_ID 0x9D81 1159 #define PCH_CNP_LP_DEV_P3_ID 0x9D82 1160 #define PCH_CNP_LP_DEV_P4_ID 0x9D83 1161 #define PCH_CNP_LP_DEV_P5_ID 0x9D84 1162 #define PCH_CNP_LP_DEV_P6_ID 0x9D85 1163 #define PCH_CNP_LP_DEV_P7_ID 0x9D86 1164 #define PCH_CNP_LP_DEV_P8_ID 0x9D87 1165 #define PCH_CNP_LP_DEV_P9_ID 0x9D88 1166 #define PCH_CNP_LP_DEV_PA_ID 0x9D89 1167 #define PCH_CNP_LP_DEV_PB_ID 0x9D8A 1168 #define PCH_CNP_LP_DEV_PC_ID 0x9D8B 1169 #define PCH_CNP_LP_DEV_PD_ID 0x9D8C 1170 #define PCH_CNP_LP_DEV_PE_ID 0x9D8D 1171 #define PCH_CNP_LP_DEV_PF_ID 0x9D8E 1172 #define PCH_CNP_LP_DEV_P10_ID 0x9D8F 1173 #define PCH_CNP_LP_DEV_P11_ID 0x9D90 1174 #define PCH_CNP_LP_DEV_P12_ID 0x9D91 1175 #define PCH_CNP_LP_DEV_P13_ID 0x9D92 1176 #define PCH_CNP_LP_DEV_P14_ID 0x9D93 1177 #define PCH_CNP_LP_DEV_P15_ID 0x9D94 1178 #define PCH_CNP_LP_DEV_P16_ID 0x9D95 1179 #define PCH_CNP_LP_DEV_P17_ID 0x9D96 1180 #define PCH_CNP_LP_DEV_P18_ID 0x9D97 1181 #define PCH_CNP_LP_DEV_P19_ID 0x9D98 1182 #define PCH_CNP_LP_DEV_P1A_ID 0x9D99 1183 #define PCH_CNP_LP_DEV_P1B_ID 0x9D9A 1184 #define PCH_CNP_LP_DEV_P1C_ID 0x9D9B 1185 #define PCH_CNP_LP_DEV_P1D_ID 0x9D9C 1186 #define PCH_CNP_LP_DEV_P1E_ID 0x9D9D 1187 #define PCH_CNP_LP_DEV_P1F_ID 0x9D9E 1188 #define PCH_CNP_LP_DEV_P20_ID 0x9D9F 1189 1190 //define CNL Halo PCH Device Ids 1191 #define PCH_CNP_HALO_DEV_P1_ID 0xA300 1192 #define PCH_CNP_HALO_DEV_P2_ID 0xA301 1193 #define PCH_CNP_HALO_DEV_P3_ID 0xA302 1194 #define PCH_CNP_HALO_DEV_P4_ID 0xA303 1195 #define PCH_CNP_HALO_DEV_P5_ID 0xA304 1196 #define PCH_CNP_HALO_DEV_P6_ID 0xA305 1197 #define PCH_CNP_HALO_DEV_P7_ID 0xA306 1198 #define PCH_CNP_HALO_DEV_P8_ID 0xA307 1199 #define PCH_CNP_HALO_DEV_P9_ID 0xA308 1200 #define PCH_CNP_HALO_DEV_PA_ID 0xA309 1201 #define PCH_CNP_HALO_DEV_PB_ID 0xA30A 1202 #define PCH_CNP_HALO_DEV_PC_ID 0xA30B 1203 #define PCH_CNP_HALO_DEV_PD_ID 0xA30C 1204 #define PCH_CNP_HALO_DEV_PE_ID 0xA30D 1205 #define PCH_CNP_HALO_DEV_PF_ID 0xA30E 1206 #define PCH_CNP_HALO_DEV_P10_ID 0xA30F 1207 #define PCH_CNP_HALO_DEV_P11_ID 0xA310 1208 #define PCH_CNP_HALO_DEV_P12_ID 0xA311 1209 #define PCH_CNP_HALO_DEV_P13_ID 0xA312 1210 #define PCH_CNP_HALO_DEV_P14_ID 0xA313 1211 #define PCH_CNP_HALO_DEV_P15_ID 0xA314 1212 #define PCH_CNP_HALO_DEV_P16_ID 0xA315 1213 #define PCH_CNP_HALO_DEV_P17_ID 0xA316 1214 #define PCH_CNP_HALO_DEV_P18_ID 0xA317 1215 #define PCH_CNP_HALO_DEV_P19_ID 0xA318 1216 #define PCH_CNP_HALO_DEV_P1A_ID 0xA319 1217 #define PCH_CNP_HALO_DEV_P1B_ID 0xA31A 1218 #define PCH_CNP_HALO_DEV_P1C_ID 0xA31B 1219 #define PCH_CNP_HALO_DEV_P1D_ID 0xA31C 1220 #define PCH_CNP_HALO_DEV_P1E_ID 0xA31D 1221 #define PCH_CNP_HALO_DEV_P1F_ID 0xA31E 1222 #define PCH_CNP_HALO_DEV_P20_ID 0xA31F 1223 1224 //GEN11LP 1225 #define IICL_LP_GT1_MOB_DEVICE_F0_ID 0xFF05 1226 #define IICL_LP_1x8x8_SUPERSKU_DEVICE_F0_ID 0x8A50 1227 #define IICL_LP_1x8x8_ULX_DEVICE_F0_ID 0x8A51 1228 #define IICL_LP_1x6x8_ULX_DEVICE_F0_ID 0x8A5C 1229 #define IICL_LP_1x4x8_ULX_DEVICE_F0_ID 0x8A5D 1230 #define IICL_LP_1x8x8_ULT_DEVICE_F0_ID 0x8A52 1231 #define IICL_LP_1x6x8_ULT_DEVICE_F0_ID 0x8A5A 1232 #define IICL_LP_1x4x8_ULT_DEVICE_F0_ID 0x8A5B 1233 #define IICL_LP_0x0x0_ULT_DEVICE_A0_ID 0x8A70 1234 #define IICL_LP_1x1x8_ULT_DEVICE_A0_ID 0x8A71 1235 #define IICL_LP_1x4x8_LOW_MEDIA_ULT_DEVICE_F0_ID 0x8A56 1236 #define IICL_LP_1x4x8_LOW_MEDIA_ULX_DEVICE_F0_ID 0x8A58 1237 1238 //TGL LP 1239 #define IGEN12LP_GT1_MOB_DEVICE_F0_ID 0xFF20 1240 #define ITGL_LP_1x6x16_UNKNOWN_SKU_F0_ID_5 0x9A49 // Remove this once newer enums are merged in OpenCL. Added this to avoid build failure with Linux/OpenCL. 1241 #define ITGL_LP_1x6x16_ULT_15W_DEVICE_F0_ID 0x9A49 // Mobile - U42 - 15W 1242 #define ITGL_LP_1x6x16_ULX_5_2W_DEVICE_F0_ID 0x9A40 // Mobile - Y42 - 5.2W 1243 #define ITGL_LP_1x6x16_ULT_12W_DEVICE_F0_ID 0x9A59 // Mobile - U42 - 12W 1244 #define ITGL_LP_1x2x16_HALO_45W_DEVICE_F0_ID 0x9A60 // Halo - H81 - 45W 1245 #define ITGL_LP_1x2x16_DESK_65W_DEVICE_F0_ID 0x9A68 // Desktop - S81 - 35W/65W/95W 1246 #define ITGL_LP_1x2x16_HALO_WS_45W_DEVICE_F0_ID 0x9A70 // Mobile WS - H81 - 45W 1247 #define ITGL_LP_1x2x16_DESK_WS_65W_DEVICE_F0_ID 0x9A78 // Desktop WS- S81 - 35W/65W/95W 1248 #define ITGL_LP_GT0_ULT_DEVICE_F0_ID 0x9A7F // GT0 - No GFX, Display Only 1249 1250 #define DEV_ID_0205 0x0205 1251 #define DEV_ID_020A 0x020A 1252 //Internal Validation Sku's Only 1253 #define DEV_ID_0201 0x0201 1254 #define DEV_ID_0202 0x0202 1255 #define DEV_ID_0203 0x0203 1256 #define DEV_ID_0204 0x0204 1257 #define DEV_ID_0206 0x0206 1258 #define DEV_ID_0207 0x0207 1259 #define DEV_ID_0208 0x0208 1260 #define DEV_ID_0209 0x0209 1261 #define DEV_ID_020B 0x020B 1262 #define DEV_ID_020C 0x020C 1263 #define DEV_ID_020D 0x020D 1264 #define DEV_ID_020E 0x020E 1265 #define DEV_ID_020F 0x020F 1266 #define DEV_ID_0210 0x0210 1267 1268 #define DEV_ID_FF20 0xFF20 1269 #define DEV_ID_9A49 0x9A49 1270 #define DEV_ID_9A40 0x9A40 1271 #define DEV_ID_9A59 0x9A59 1272 #define DEV_ID_9A60 0x9A60 1273 #define DEV_ID_9A68 0x9A68 1274 #define DEV_ID_9A70 0x9A70 1275 #define DEV_ID_9A78 0x9A78 1276 #define DEV_ID_9A7F 0x9A7F 1277 1278 #define DEV_ID_4905 0x4905 1279 #define DEV_ID_4906 0x4906 1280 #define DEV_ID_4907 0x4907 1281 1282 // Rocketlake 1283 #define DEV_ID_4C80 0x4C80 1284 #define DEV_ID_4C8A 0x4C8A 1285 #define DEV_ID_4C8B 0x4C8B 1286 #define DEV_ID_4C8C 0x4C8C 1287 #define DEV_ID_4C90 0x4C90 1288 #define DEV_ID_4C9A 0x4C9A 1289 1290 //LKF 1291 #define ILKF_1x8x8_DESK_DEVICE_F0_ID 0x9840 1292 #define ILKF_GT0_DESK_DEVICE_A0_ID 0x9850 1293 #define ILKF_1x6x8_DESK_DEVICE_F0_ID 0x9841 1294 #define ILKF_1x4x8_DESK_DEVICE_F0_ID 0x9842 1295 1296 //JSL 1297 #define IJSL_1x4x8_DEVICE_A0_ID 0x4500 1298 1299 //EHL 1300 #define IEHL_1x4x8_SUPERSKU_DEVICE_A0_ID 0x4500 1301 #define IEHL_1x2x4_DEVICE_A0_ID 0x4541 1302 #define IEHL_1x4x4_DEVICE_A0_ID 0x4551 1303 #define IEHL_1x4x8_DEVICE_A0_ID 0x4571 1304 1305 #define DEV_ID_4500 0x4500 1306 #define DEV_ID_4541 0x4541 1307 #define DEV_ID_4551 0x4551 1308 #define DEV_ID_4571 0x4571 1309 #define DEV_ID_4555 0x4555 1310 1311 //JSL+ Rev02 1312 #define IJSL_1x4x4_DEVICE_B0_ID 0x4E51 1313 #define IJSL_1x4x6_DEVICE_B0_ID 0x4E61 1314 #define IJSL_1x4x8_DEVICE_B0_ID 0x4E71 1315 1316 #define DEV_ID_4E51 0x4E51 1317 #define DEV_ID_4E61 0x4E61 1318 #define DEV_ID_4E71 0x4E71 1319 #define DEV_ID_4E55 0x4E55 1320 1321 //ADL-S PCH Device IDs 1322 #define DEV_ID_4680 0x4680 1323 #define DEV_ID_4681 0x4681 1324 #define DEV_ID_4682 0x4682 1325 #define DEV_ID_4683 0x4683 1326 #define DEV_ID_4690 0x4690 1327 #define DEV_ID_4691 0x4691 1328 #define DEV_ID_4692 0x4692 1329 #define DEV_ID_4693 0x4693 1330 #define DEV_ID_4698 0x4698 1331 #define DEV_ID_4699 0x4699 1332 1333 // ADL-P 1334 #define DEV_ID_46A0 0x46A0 1335 #define DEV_ID_46A1 0x46A1 1336 #define DEV_ID_46A2 0x46A2 1337 #define DEV_ID_46A3 0x46A3 1338 #define DEV_ID_46A6 0x46A6 1339 #define DEV_ID_46A8 0x46A8 1340 #define DEV_ID_46AA 0x46AA 1341 #define DEV_ID_4626 0x4626 1342 #define DEV_ID_4628 0x4628 1343 #define DEV_ID_462A 0x462A 1344 #define DEV_ID_46B0 0x46B0 1345 #define DEV_ID_46B1 0x46B1 1346 #define DEV_ID_46B2 0x46B2 1347 #define DEV_ID_46B3 0x46B3 1348 #define DEV_ID_46C0 0x46C0 1349 #define DEV_ID_46C1 0x46C1 1350 #define DEV_ID_46C2 0x46C2 1351 #define DEV_ID_46C3 0x46C3 1352 1353 //ICL PCH LP Device IDs 1354 #define ICP_LP_RESERVED_FUSE_ID 0x3480 1355 #define ICP_LP_U_SUPER_SKU_ID 0x3481 1356 #define ICP_LP_U_PREMIUM_ID 0x3482 1357 #define ICP_LP_U_MAINSTREAM_ID 0x3483 1358 #define ICL_LP_UNKNOWN_SKU_ID_1 0x3484 1359 #define ICL_LP_UNKNOWN_SKU_ID_2 0x3485 1360 #define ICP_LP_Y_SUPER_SKU_ID 0x3486 1361 #define ICP_LP_Y_PREMIUM_ID 0x3487 1362 #define ICL_LP_UNKNOWN_SKU_ID_3 0x3488 1363 #define ICL_LP_UNKNOWN_SKU_ID_4 0x3489 1364 #define ICL_LP_UNKNOWN_SKU_ID_5 0x348A 1365 #define ICL_LP_UNKNOWN_SKU_ID_6 0x348B 1366 #define ICL_LP_UNKNOWN_SKU_ID_7 0x348C 1367 #define ICL_LP_UNKNOWN_SKU_ID_8 0x348D 1368 #define ICL_LP_UNKNOWN_SKU_ID_9 0x348E 1369 #define ICL_LP_UNKNOWN_SKU_ID_10 0x348F 1370 #define ICL_LP_UNKNOWN_SKU_ID_11 0x3490 1371 #define ICL_LP_UNKNOWN_SKU_ID_12 0x3491 1372 #define ICL_LP_UNKNOWN_SKU_ID_13 0x3492 1373 #define ICL_LP_UNKNOWN_SKU_ID_14 0x3493 1374 #define ICL_LP_UNKNOWN_SKU_ID_15 0x3494 1375 #define ICL_LP_UNKNOWN_SKU_ID_16 0x3495 1376 #define ICL_LP_UNKNOWN_SKU_ID_17 0x3496 1377 #define ICL_LP_UNKNOWN_SKU_ID_18 0x3497 1378 #define ICL_LP_UNKNOWN_SKU_ID_19 0x3498 1379 #define ICL_LP_UNKNOWN_SKU_ID_20 0x3499 1380 #define ICL_LP_UNKNOWN_SKU_ID_21 0x349A 1381 #define ICL_LP_UNKNOWN_SKU_ID_22 0x349B 1382 #define ICL_LP_UNKNOWN_SKU_ID_23 0x349C 1383 #define ICL_LP_UNKNOWN_SKU_ID_24 0x349D 1384 #define ICL_LP_UNKNOWN_SKU_ID_25 0x349E 1385 #define ICL_LP_UNKNOWN_SKU_ID_26 0x349F 1386 1387 // JSL N PCH Device IDs for JSL+ Rev02 1388 #define PCH_JSP_N_UNKNOWN_SKU_ID_1 0x4D80 1389 #define PCH_JSP_N_UNKNOWN_SKU_ID_2 0x4D81 1390 #define PCH_JSP_N_UNKNOWN_SKU_ID_3 0x4D82 1391 #define PCH_JSP_N_UNKNOWN_SKU_ID_4 0x4D83 1392 #define PCH_JSP_N_UNKNOWN_SKU_ID_5 0x4D84 1393 #define PCH_JSP_N_UNKNOWN_SKU_ID_6 0x4D85 1394 #define PCH_JSP_N_UNKNOWN_SKU_ID_7 0x4D86 1395 #define PCH_JSP_N_UNKNOWN_SKU_ID_8 0x4D87 1396 #define PCH_JSP_N_UNKNOWN_SKU_ID_9 0x4D88 1397 #define PCH_JSP_N_UNKNOWN_SKU_ID_10 0x4D89 1398 #define PCH_JSP_N_UNKNOWN_SKU_ID_11 0x4D8A 1399 #define PCH_JSP_N_UNKNOWN_SKU_ID_12 0x4D8B 1400 #define PCH_JSP_N_UNKNOWN_SKU_ID_13 0x4D8C 1401 #define PCH_JSP_N_UNKNOWN_SKU_ID_14 0x4D8D 1402 #define PCH_JSP_N_UNKNOWN_SKU_ID_15 0x4D8E 1403 #define PCH_JSP_N_UNKNOWN_SKU_ID_16 0x4D8F 1404 #define PCH_JSP_N_UNKNOWN_SKU_ID_17 0x4D90 1405 #define PCH_JSP_N_UNKNOWN_SKU_ID_18 0x4D91 1406 #define PCH_JSP_N_UNKNOWN_SKU_ID_19 0x4D92 1407 #define PCH_JSP_N_UNKNOWN_SKU_ID_20 0x4D93 1408 #define PCH_JSP_N_UNKNOWN_SKU_ID_21 0x4D94 1409 #define PCH_JSP_N_UNKNOWN_SKU_ID_22 0x4D95 1410 #define PCH_JSP_N_UNKNOWN_SKU_ID_23 0x4D96 1411 #define PCH_JSP_N_UNKNOWN_SKU_ID_24 0x4D97 1412 #define PCH_JSP_N_UNKNOWN_SKU_ID_25 0x4D98 1413 #define PCH_JSP_N_UNKNOWN_SKU_ID_26 0x4D99 1414 #define PCH_JSP_N_UNKNOWN_SKU_ID_27 0x4D9A 1415 #define PCH_JSP_N_UNKNOWN_SKU_ID_28 0x4D9B 1416 #define PCH_JSP_N_UNKNOWN_SKU_ID_29 0x4D9C 1417 #define PCH_JSP_N_UNKNOWN_SKU_ID_30 0x4D9D 1418 #define PCH_JSP_N_UNKNOWN_SKU_ID_31 0x4D9E 1419 #define PCH_JSP_N_UNKNOWN_SKU_ID_32 0x4D9F 1420 1421 // LKF-PCH Device IDs 1422 #define PCH_LKF_UNFUSED_SKU_ID 0x9880 1423 #define PCH_LKF_SUPER_SKU_ID 0x9881 1424 // TGL_LP PCH Device ID range 0xA080-0xA09F 1425 #define PCH_TGL_LP_UNKNOWN_SKU_ID_1 0xA080 1426 #define PCH_TGL_LP_UNKNOWN_SKU_ID_2 0xA081 1427 #define PCH_TGL_LP_UNKNOWN_SKU_ID_3 0xA082 1428 #define PCH_TGL_LP_UNKNOWN_SKU_ID_4 0xA083 1429 #define PCH_TGL_LP_UNKNOWN_SKU_ID_5 0xA084 1430 #define PCH_TGL_LP_UNKNOWN_SKU_ID_6 0xA085 1431 #define PCH_TGL_LP_UNKNOWN_SKU_ID_7 0xA086 1432 #define PCH_TGL_LP_UNKNOWN_SKU_ID_8 0xA087 1433 #define PCH_TGL_LP_UNKNOWN_SKU_ID_9 0xA088 1434 #define PCH_TGL_LP_UNKNOWN_SKU_ID_10 0xA089 1435 #define PCH_TGL_LP_UNKNOWN_SKU_ID_11 0xA08A 1436 #define PCH_TGL_LP_UNKNOWN_SKU_ID_12 0xA08B 1437 #define PCH_TGL_LP_UNKNOWN_SKU_ID_13 0xA08C 1438 #define PCH_TGL_LP_UNKNOWN_SKU_ID_14 0xA08D 1439 #define PCH_TGL_LP_UNKNOWN_SKU_ID_15 0xA08E 1440 #define PCH_TGL_LP_UNKNOWN_SKU_ID_16 0xA08F 1441 #define PCH_TGL_LP_UNKNOWN_SKU_ID_17 0xA090 1442 #define PCH_TGL_LP_UNKNOWN_SKU_ID_18 0xA091 1443 #define PCH_TGL_LP_UNKNOWN_SKU_ID_19 0xA092 1444 #define PCH_TGL_LP_UNKNOWN_SKU_ID_20 0xA093 1445 #define PCH_TGL_LP_UNKNOWN_SKU_ID_21 0xA094 1446 #define PCH_TGL_LP_UNKNOWN_SKU_ID_22 0xA095 1447 #define PCH_TGL_LP_UNKNOWN_SKU_ID_23 0xA096 1448 #define PCH_TGL_LP_UNKNOWN_SKU_ID_24 0xA097 1449 #define PCH_TGL_LP_UNKNOWN_SKU_ID_25 0xA098 1450 #define PCH_TGL_LP_UNKNOWN_SKU_ID_26 0xA099 1451 #define PCH_TGL_LP_UNKNOWN_SKU_ID_27 0xA09A 1452 #define PCH_TGL_LP_UNKNOWN_SKU_ID_28 0xA09B 1453 #define PCH_TGL_LP_UNKNOWN_SKU_ID_29 0xA09C 1454 #define PCH_TGL_LP_UNKNOWN_SKU_ID_30 0xA09D 1455 #define PCH_TGL_LP_UNKNOWN_SKU_ID_31 0xA09E 1456 #define PCH_TGL_LP_UNKNOWN_SKU_ID_32 0xA09F 1457 1458 //define CML LP PCH Device Ids 1459 #define PCH_CMP_LP_DEV_P1_ID 0x0280 1460 #define PCH_CMP_LP_DEV_P2_ID 0x0281 1461 #define PCH_CMP_LP_DEV_P3_ID 0x0282 1462 #define PCH_CMP_LP_DEV_P4_ID 0x0283 1463 #define PCH_CMP_LP_DEV_P5_ID 0x0284 1464 #define PCH_CMP_LP_DEV_P6_ID 0x0285 1465 #define PCH_CMP_LP_DEV_P7_ID 0x0286 1466 #define PCH_CMP_LP_DEV_P8_ID 0x0287 1467 #define PCH_CMP_LP_DEV_P9_ID 0x0288 1468 #define PCH_CMP_LP_DEV_P10_ID 0x0289 1469 #define PCH_CMP_LP_DEV_P11_ID 0x028A 1470 #define PCH_CMP_LP_DEV_P12_ID 0x028B 1471 #define PCH_CMP_LP_DEV_P13_ID 0x028C 1472 #define PCH_CMP_LP_DEV_P14_ID 0x028D 1473 #define PCH_CMP_LP_DEV_P15_ID 0x028E 1474 #define PCH_CMP_LP_DEV_P16_ID 0x028F 1475 #define PCH_CMP_LP_DEV_P17_ID 0x0290 1476 #define PCH_CMP_LP_DEV_P18_ID 0x0291 1477 #define PCH_CMP_LP_DEV_P19_ID 0x0292 1478 #define PCH_CMP_LP_DEV_P20_ID 0x0293 1479 #define PCH_CMP_LP_DEV_P21_ID 0x0294 1480 #define PCH_CMP_LP_DEV_P22_ID 0x0295 1481 #define PCH_CMP_LP_DEV_P23_ID 0x0296 1482 #define PCH_CMP_LP_DEV_P24_ID 0x0297 1483 #define PCH_CMP_LP_DEV_P25_ID 0x0298 1484 #define PCH_CMP_LP_DEV_P26_ID 0x0299 1485 #define PCH_CMP_LP_DEV_P27_ID 0x029A 1486 #define PCH_CMP_LP_DEV_P28_ID 0x029B 1487 #define PCH_CMP_LP_DEV_P29_ID 0x029C 1488 #define PCH_CMP_LP_DEV_P30_ID 0x029D 1489 #define PCH_CMP_LP_DEV_P31_ID 0x029E 1490 #define PCH_CMP_LP_DEV_P32_ID 0x029F 1491 1492 // TGL_H PCH Device ID range 0x4380-0x439F 1493 #define PCH_TGL_H_UNKNOWN_SKU_ID_1 0x4380 1494 #define PCH_TGL_H_UNKNOWN_SKU_ID_2 0x4381 1495 #define PCH_TGL_H_UNKNOWN_SKU_ID_3 0x4382 1496 #define PCH_TGL_H_UNKNOWN_SKU_ID_4 0x4383 1497 #define PCH_TGL_H_UNKNOWN_SKU_ID_5 0x4384 1498 #define PCH_TGL_H_UNKNOWN_SKU_ID_6 0x4385 1499 #define PCH_TGL_H_UNKNOWN_SKU_ID_7 0x4386 1500 #define PCH_TGL_H_UNKNOWN_SKU_ID_8 0x4387 1501 #define PCH_TGL_H_UNKNOWN_SKU_ID_9 0x4388 1502 #define PCH_TGL_H_UNKNOWN_SKU_ID_10 0x4389 1503 #define PCH_TGL_H_UNKNOWN_SKU_ID_11 0x438A 1504 #define PCH_TGL_H_UNKNOWN_SKU_ID_12 0x438B 1505 #define PCH_TGL_H_UNKNOWN_SKU_ID_13 0x438C 1506 #define PCH_TGL_H_UNKNOWN_SKU_ID_14 0x438D 1507 #define PCH_TGL_H_UNKNOWN_SKU_ID_15 0x438E 1508 #define PCH_TGL_H_UNKNOWN_SKU_ID_16 0x438F 1509 #define PCH_TGL_H_UNKNOWN_SKU_ID_17 0x4390 1510 #define PCH_TGL_H_UNKNOWN_SKU_ID_18 0x4391 1511 #define PCH_TGL_H_UNKNOWN_SKU_ID_19 0x4392 1512 #define PCH_TGL_H_UNKNOWN_SKU_ID_20 0x4393 1513 #define PCH_TGL_H_UNKNOWN_SKU_ID_21 0x4394 1514 #define PCH_TGL_H_UNKNOWN_SKU_ID_22 0x4395 1515 #define PCH_TGL_H_UNKNOWN_SKU_ID_23 0x4396 1516 #define PCH_TGL_H_UNKNOWN_SKU_ID_24 0x4397 1517 #define PCH_TGL_H_UNKNOWN_SKU_ID_25 0x4398 1518 #define PCH_TGL_H_UNKNOWN_SKU_ID_26 0x4399 1519 #define PCH_TGL_H_UNKNOWN_SKU_ID_27 0x439A 1520 #define PCH_TGL_H_UNKNOWN_SKU_ID_28 0x439B 1521 #define PCH_TGL_H_UNKNOWN_SKU_ID_29 0x439C 1522 #define PCH_TGL_H_UNKNOWN_SKU_ID_30 0x439D 1523 #define PCH_TGL_H_UNKNOWN_SKU_ID_31 0x439E 1524 #define PCH_TGL_H_UNKNOWN_SKU_ID_32 0x439F 1525 1526 //define CML H PCH Device Ids 1527 #define PCH_CMP_H_DEV_P1_ID 0x0680 1528 #define PCH_CMP_H_DEV_P2_ID 0x0681 1529 #define PCH_CMP_H_DEV_P3_ID 0x0682 1530 #define PCH_CMP_H_DEV_P4_ID 0x0683 1531 #define PCH_CMP_H_DEV_P5_ID 0x0684 1532 #define PCH_CMP_H_DEV_P6_ID 0x0685 1533 #define PCH_CMP_H_DEV_P7_ID 0x0686 1534 #define PCH_CMP_H_DEV_P8_ID 0x0687 1535 #define PCH_CMP_H_DEV_P9_ID 0x0688 1536 #define PCH_CMP_H_DEV_P10_ID 0x0689 1537 #define PCH_CMP_H_DEV_P11_ID 0x068A 1538 #define PCH_CMP_H_DEV_P12_ID 0x068B 1539 #define PCH_CMP_H_DEV_P13_ID 0x068C 1540 #define PCH_CMP_H_DEV_P14_ID 0x068D 1541 #define PCH_CMP_H_DEV_P15_ID 0x068E 1542 #define PCH_CMP_H_DEV_P16_ID 0x068F 1543 #define PCH_CMP_H_DEV_P17_ID 0x0690 1544 #define PCH_CMP_H_DEV_P18_ID 0x0691 1545 #define PCH_CMP_H_DEV_P19_ID 0x0692 1546 #define PCH_CMP_H_DEV_P20_ID 0x0693 1547 #define PCH_CMP_H_DEV_P21_ID 0x0694 1548 #define PCH_CMP_H_DEV_P22_ID 0x0695 1549 #define PCH_CMP_H_DEV_P23_ID 0x0696 1550 #define PCH_CMP_H_DEV_P24_ID 0x0697 1551 #define PCH_CMP_H_DEV_P25_ID 0x0698 1552 #define PCH_CMP_H_DEV_P26_ID 0x0699 1553 #define PCH_CMP_H_DEV_P27_ID 0x069A 1554 #define PCH_CMP_H_DEV_P28_ID 0x069B 1555 #define PCH_CMP_H_DEV_P29_ID 0x069C 1556 #define PCH_CMP_H_DEV_P30_ID 0x069D 1557 #define PCH_CMP_H_DEV_P31_ID 0x069E 1558 #define PCH_CMP_H_DEV_P32_ID 0x069F 1559 1560 //define CML V PCH Device Ids 1561 #define PCH_CMP_V_DEV_P65_ID 0xA3C0 1562 #define PCH_CMP_V_DEV_P66_ID 0xA3C1 1563 #define PCH_CMP_V_DEV_P67_ID 0xA3C2 1564 #define PCH_CMP_V_DEV_P68_ID 0xA3C3 1565 #define PCH_CMP_V_DEV_P69_ID 0xA3C4 1566 #define PCH_CMP_V_DEV_P70_ID 0xA3C5 1567 #define PCH_CMP_V_DEV_P71_ID 0xA3C6 1568 #define PCH_CMP_V_DEV_P72_ID 0xA3C7 1569 #define PCH_CMP_V_DEV_P73_ID 0xA3C8 1570 #define PCH_CMP_V_DEV_P74_ID 0xA3C9 1571 #define PCH_CMP_V_DEV_P75_ID 0xA3CA 1572 #define PCH_CMP_V_DEV_P76_ID 0xA3CB 1573 #define PCH_CMP_V_DEV_P77_ID 0xA3CC 1574 #define PCH_CMP_V_DEV_P78_ID 0xA3CD 1575 #define PCH_CMP_V_DEV_P79_ID 0xA3CE 1576 #define PCH_CMP_V_DEV_P80_ID 0xA3CF 1577 #define PCH_CMP_V_DEV_P81_ID 0xA3D0 1578 #define PCH_CMP_V_DEV_P82_ID 0xA3D1 1579 #define PCH_CMP_V_DEV_P83_ID 0xA3D2 1580 #define PCH_CMP_V_DEV_P84_ID 0xA3D3 1581 #define PCH_CMP_V_DEV_P85_ID 0xA3D4 1582 #define PCH_CMP_V_DEV_P86_ID 0xA3D5 1583 #define PCH_CMP_V_DEV_P87_ID 0xA3D6 1584 #define PCH_CMP_V_DEV_P88_ID 0xA3D7 1585 #define PCH_CMP_V_DEV_P89_ID 0xA3D8 1586 #define PCH_CMP_V_DEV_P90_ID 0xA3D9 1587 #define PCH_CMP_V_DEV_P91_ID 0xA3DA 1588 #define PCH_CMP_V_DEV_P92_ID 0xA3DB 1589 #define PCH_CMP_V_DEV_P93_ID 0xA3DC 1590 #define PCH_CMP_V_DEV_P94_ID 0xA3DD 1591 #define PCH_CMP_V_DEV_P95_ID 0xA3DE 1592 #define PCH_CMP_V_DEV_P96_ID 0xA3DF 1593 1594 // ADL_S PCH Device ID range 1595 #define DEV_ID_7A80 0x7A80 1596 #define DEV_ID_7A81 0x7A81 1597 #define DEV_ID_7A82 0x7A82 1598 #define DEV_ID_7A83 0x7A83 1599 #define DEV_ID_7A84 0x7A84 1600 #define DEV_ID_7A85 0x7A85 1601 #define DEV_ID_7A86 0x7A86 1602 #define DEV_ID_7A87 0x7A87 1603 #define DEV_ID_7A88 0x7A88 1604 #define DEV_ID_7A89 0x7A89 1605 #define DEV_ID_7A8A 0x7A8A 1606 #define DEV_ID_7A8B 0x7A8B 1607 #define DEV_ID_7A8C 0x7A8C 1608 #define DEV_ID_7A8D 0x7A8D 1609 #define DEV_ID_7A8E 0x7A8E 1610 #define DEV_ID_7A8F 0x7A8F 1611 #define DEV_ID_7A90 0x7A90 1612 #define DEV_ID_7A91 0x7A91 1613 #define DEV_ID_7A92 0x7A92 1614 #define DEV_ID_7A93 0x7A93 1615 #define DEV_ID_7A94 0x7A94 1616 #define DEV_ID_7A95 0x7A95 1617 #define DEV_ID_7A96 0x7A96 1618 #define DEV_ID_7A97 0x7A97 1619 #define DEV_ID_7A98 0x7A98 1620 #define DEV_ID_7A99 0x7A99 1621 #define DEV_ID_7A9A 0x7A9A 1622 #define DEV_ID_7A9B 0x7A9B 1623 #define DEV_ID_7A9C 0x7A9C 1624 #define DEV_ID_7A9D 0x7A9D 1625 #define DEV_ID_7A9E 0x7A9E 1626 #define DEV_ID_7A9F 0x7A9F 1627 1628 // ADL_P PCH Device ID range 1629 #define PCH_DEV_ID_5180 0x5180 1630 #define PCH_DEV_ID_5181 0x5181 1631 #define PCH_DEV_ID_5182 0x5182 1632 #define PCH_DEV_ID_5183 0x5183 1633 #define PCH_DEV_ID_5184 0x5184 1634 #define PCH_DEV_ID_5185 0x5185 1635 #define PCH_DEV_ID_5186 0x5186 1636 #define PCH_DEV_ID_5187 0x5187 1637 #define PCH_DEV_ID_5188 0x5188 1638 #define PCH_DEV_ID_5189 0x5189 1639 #define PCH_DEV_ID_518A 0x518A 1640 #define PCH_DEV_ID_518B 0x518B 1641 #define PCH_DEV_ID_518C 0x518C 1642 #define PCH_DEV_ID_518D 0x518D 1643 #define PCH_DEV_ID_518E 0x518E 1644 #define PCH_DEV_ID_518F 0x518F 1645 #define PCH_DEV_ID_5190 0x5190 1646 #define PCH_DEV_ID_5191 0x5191 1647 #define PCH_DEV_ID_5192 0x5192 1648 #define PCH_DEV_ID_5193 0x5193 1649 #define PCH_DEV_ID_5194 0x5194 1650 #define PCH_DEV_ID_5195 0x5195 1651 #define PCH_DEV_ID_5196 0x5196 1652 #define PCH_DEV_ID_5197 0x5197 1653 #define PCH_DEV_ID_5198 0x5198 1654 #define PCH_DEV_ID_5199 0x5199 1655 #define PCH_DEV_ID_519A 0x519A 1656 #define PCH_DEV_ID_519B 0x519B 1657 #define PCH_DEV_ID_519C 0x519C 1658 #define PCH_DEV_ID_519D 0x519D 1659 #define PCH_DEV_ID_519E 0x519E 1660 #define PCH_DEV_ID_519F 0x519F 1661 1662 // ADL_N PCH Device ID range 1663 #define PCH_DEV_ID_5480 0x5480 1664 #define PCH_DEV_ID_5481 0x5481 1665 #define PCH_DEV_ID_5482 0x5482 1666 #define PCH_DEV_ID_5483 0x5483 1667 #define PCH_DEV_ID_5484 0x5484 1668 #define PCH_DEV_ID_5485 0x5485 1669 #define PCH_DEV_ID_5486 0x5486 1670 #define PCH_DEV_ID_5487 0x5487 1671 #define PCH_DEV_ID_5488 0x5488 1672 #define PCH_DEV_ID_5489 0x5489 1673 #define PCH_DEV_ID_548A 0x548A 1674 #define PCH_DEV_ID_548B 0x548B 1675 #define PCH_DEV_ID_548C 0x548C 1676 #define PCH_DEV_ID_548D 0x548D 1677 #define PCH_DEV_ID_548E 0x548E 1678 #define PCH_DEV_ID_548F 0x548F 1679 #define PCH_DEV_ID_5490 0x5490 1680 #define PCH_DEV_ID_5491 0x5491 1681 #define PCH_DEV_ID_5492 0x5492 1682 #define PCH_DEV_ID_5493 0x5493 1683 #define PCH_DEV_ID_5494 0x5494 1684 #define PCH_DEV_ID_5495 0x5495 1685 #define PCH_DEV_ID_5496 0x5496 1686 #define PCH_DEV_ID_5497 0x5497 1687 #define PCH_DEV_ID_5498 0x5498 1688 #define PCH_DEV_ID_5499 0x5499 1689 #define PCH_DEV_ID_549A 0x549A 1690 #define PCH_DEV_ID_549B 0x549B 1691 #define PCH_DEV_ID_549C 0x549C 1692 #define PCH_DEV_ID_549D 0x549D 1693 #define PCH_DEV_ID_549E 0x549E 1694 #define PCH_DEV_ID_549F 0x549F 1695 #define PCH_DEV_ID_54A0 0x54A0 1696 #define PCH_DEV_ID_54A1 0x54A1 1697 #define PCH_DEV_ID_54A2 0x54A2 1698 #define PCH_DEV_ID_54A3 0x54A3 1699 #define PCH_DEV_ID_54A4 0x54A4 1700 #define PCH_DEV_ID_15FB 0x15FB 1701 #define PCH_DEV_ID_15FC 0x15FC 1702 #define PCH_DEV_ID_54A6 0x54A6 1703 #define PCH_DEV_ID_54A7 0x54A7 1704 #define PCH_DEV_ID_54A8 0x54A8 1705 #define PCH_DEV_ID_54A9 0x54A9 1706 #define PCH_DEV_ID_54AA 0x54AA 1707 #define PCH_DEV_ID_54AB 0x54AB 1708 #define PCH_DEV_ID_54AC 0x54AC 1709 #define PCH_DEV_ID_54AD 0x54AD 1710 #define PCH_DEV_ID_54AE 0x54AE 1711 #define PCH_DEV_ID_54AF 0x54AF 1712 #define PCH_DEV_ID_54B0 0x54B0 1713 #define PCH_DEV_ID_54B1 0x54B1 1714 #define PCH_DEV_ID_54B2 0x54B2 1715 #define PCH_DEV_ID_54B3 0x54B3 1716 #define PCH_DEV_ID_54B4 0x54B4 1717 #define PCH_DEV_ID_54B5 0x54B5 1718 #define PCH_DEV_ID_54B6 0x54B6 1719 #define PCH_DEV_ID_54B7 0x54B7 1720 #define PCH_DEV_ID_54B8 0x54B8 1721 #define PCH_DEV_ID_54B9 0x54B9 1722 #define PCH_DEV_ID_54BA 0x54BA 1723 #define PCH_DEV_ID_54BB 0x54BB 1724 #define PCH_DEV_ID_54BC 0x54BC 1725 #define PCH_DEV_ID_54BD 0x54BD 1726 #define PCH_DEV_ID_54BE 0x54BE 1727 #define PCH_DEV_ID_54BF 0x54BF 1728 #define PCH_DEV_ID_54C4 0x54C4 1729 #define PCH_DEV_ID_54C5 0x54C5 1730 #define PCH_DEV_ID_54C6 0x54C6 1731 #define PCH_DEV_ID_54C7 0x54C7 1732 #define PCH_DEV_ID_54C8 0x54C8 1733 #define PCH_DEV_ID_54C9 0x54C9 1734 #define PCH_DEV_ID_54CA 0x54CA 1735 #define PCH_DEV_ID_54CB 0x54CB 1736 #define PCH_DEV_ID_54CC 0x54CC 1737 #define PCH_DEV_ID_54CD 0x54CD 1738 #define PCH_DEV_ID_54CE 0x54CE 1739 #define PCH_DEV_ID_54CF 0x54CF 1740 #define PCH_DEV_ID_54D0 0x54D0 1741 #define PCH_DEV_ID_54D1 0x54D1 1742 #define PCH_DEV_ID_54D2 0x54D2 1743 #define PCH_DEV_ID_54D3 0x54D3 1744 #define PCH_DEV_ID_54D4 0x54D4 1745 #define PCH_DEV_ID_54D6 0x54D6 1746 #define PCH_DEV_ID_54D7 0x54D7 1747 #define PCH_DEV_ID_282A 0x282A 1748 #define PCH_DEV_ID_54D8 0x54D8 1749 #define PCH_DEV_ID_54D9 0x54D9 1750 #define PCH_DEV_ID_54DA 0x54DA 1751 #define PCH_DEV_ID_54DB 0x54DB 1752 #define PCH_DEV_ID_54DC 0x54DC 1753 #define PCH_DEV_ID_54DD 0x54DD 1754 #define PCH_DEV_ID_54DE 0x54DE 1755 #define PCH_DEV_ID_54DF 0x54DF 1756 #define PCH_DEV_ID_54E0 0x54E0 1757 #define PCH_DEV_ID_54E1 0x54E1 1758 #define PCH_DEV_ID_54E2 0x54E2 1759 #define PCH_DEV_ID_54E3 0x54E3 1760 #define PCH_DEV_ID_54E4 0x54E4 1761 #define PCH_DEV_ID_54E5 0x54E5 1762 #define PCH_DEV_ID_54E6 0x54E6 1763 #define PCH_DEV_ID_54E7 0x54E7 1764 #define PCH_DEV_ID_54E8 0x54E8 1765 #define PCH_DEV_ID_54E9 0x54E9 1766 #define PCH_DEV_ID_54EA 0x54EA 1767 #define PCH_DEV_ID_54EB 0x54EB 1768 #define PCH_DEV_ID_54ED 0x54ED 1769 #define PCH_DEV_ID_54EE 0x54EE 1770 #define PCH_DEV_ID_54EF 0x54EF 1771 #define PCH_DEV_ID_54F0 0x54F0 1772 #define PCH_DEV_ID_54F1 0x54F1 1773 #define PCH_DEV_ID_54F2 0x54F2 1774 #define PCH_DEV_ID_54F3 0x54F3 1775 #define PCH_DEV_ID_54F4 0x54F4 1776 #define PCH_DEV_ID_54F5 0x54F5 1777 #define PCH_DEV_ID_54F6 0x54F6 1778 #define PCH_DEV_ID_54F7 0x54F7 1779 #define PCH_DEV_ID_54F9 0x54F9 1780 #define PCH_DEV_ID_54FA 0x54FA 1781 #define PCH_DEV_ID_54FB 0x54FB 1782 #define PCH_DEV_ID_54FC 0x54FC 1783 #define PCH_DEV_ID_54FD 0x54FD 1784 #define PCH_DEV_ID_54FE 0x54FE 1785 #define PCH_DEV_ID_54FF 0x54FF 1786 1787 // MTL PCH Dev IDs 1788 #define PCH_DEV_ID_7E00 0x7E00 1789 #define PCH_DEV_ID_7E01 0x7E01 1790 #define PCH_DEV_ID_7E02 0x7E02 1791 #define PCH_DEV_ID_7E03 0x7E03 1792 #define PCH_DEV_ID_7E04 0x7E04 1793 #define PCH_DEV_ID_7E05 0x7E05 1794 #define PCH_DEV_ID_7E06 0x7E06 1795 #define PCH_DEV_ID_7E07 0x7E07 1796 #define PCH_DEV_ID_7E08 0x7E08 1797 #define PCH_DEV_ID_7E09 0x7E09 1798 #define PCH_DEV_ID_7E0A 0x7E0A 1799 #define PCH_DEV_ID_7E0B 0x7E0B 1800 #define PCH_DEV_ID_7E0C 0x7E0C 1801 #define PCH_DEV_ID_7E0D 0x7E0D 1802 #define PCH_DEV_ID_7E0E 0x7E0E 1803 #define PCH_DEV_ID_7E0F 0x7E0F 1804 #define PCH_DEV_ID_7E10 0x7E10 1805 #define PCH_DEV_ID_7E11 0x7E11 1806 #define PCH_DEV_ID_7E12 0x7E12 1807 #define PCH_DEV_ID_7E13 0x7E13 1808 #define PCH_DEV_ID_7E14 0x7E14 1809 #define PCH_DEV_ID_7E15 0x7E15 1810 #define PCH_DEV_ID_7E16 0x7E16 1811 #define PCH_DEV_ID_7E17 0x7E17 1812 #define PCH_DEV_ID_7E18 0x7E18 1813 #define PCH_DEV_ID_7E19 0x7E19 1814 #define PCH_DEV_ID_7E1A 0x7E1A 1815 #define PCH_DEV_ID_7E1B 0x7E1B 1816 #define PCH_DEV_ID_7E1C 0x7E1C 1817 #define PCH_DEV_ID_7E1D 0x7E1D 1818 #define PCH_DEV_ID_7E1E 0x7E1E 1819 #define PCH_DEV_ID_7E1F 0x7E1F 1820 1821 #define PCH_DEV_ID_AE00 0xAE00 1822 #define PCH_DEV_ID_AE01 0xAE01 1823 #define PCH_DEV_ID_AE02 0xAE02 1824 #define PCH_DEV_ID_AE03 0xAE03 1825 #define PCH_DEV_ID_AE04 0xAE04 1826 #define PCH_DEV_ID_AE05 0xAE05 1827 #define PCH_DEV_ID_AE06 0xAE06 1828 #define PCH_DEV_ID_AE07 0xAE07 1829 #define PCH_DEV_ID_AE08 0xAE08 1830 #define PCH_DEV_ID_AE09 0xAE09 1831 #define PCH_DEV_ID_AE0A 0xAE0A 1832 #define PCH_DEV_ID_AE0B 0xAE0B 1833 #define PCH_DEV_ID_AE0C 0xAE0C 1834 #define PCH_DEV_ID_AE0D 0xAE0D 1835 #define PCH_DEV_ID_AE0E 0xAE0E 1836 #define PCH_DEV_ID_AE0F 0xAE0F 1837 #define PCH_DEV_ID_AE10 0xAE10 1838 #define PCH_DEV_ID_AE11 0xAE11 1839 #define PCH_DEV_ID_AE12 0xAE12 1840 #define PCH_DEV_ID_AE13 0xAE13 1841 #define PCH_DEV_ID_AE14 0xAE14 1842 #define PCH_DEV_ID_AE15 0xAE15 1843 #define PCH_DEV_ID_AE16 0xAE16 1844 #define PCH_DEV_ID_AE17 0xAE17 1845 #define PCH_DEV_ID_AE18 0xAE18 1846 #define PCH_DEV_ID_AE19 0xAE19 1847 #define PCH_DEV_ID_AE1A 0xAE1A 1848 #define PCH_DEV_ID_AE1B 0xAE1B 1849 #define PCH_DEV_ID_AE1C 0xAE1C 1850 #define PCH_DEV_ID_AE1D 0xAE1D 1851 #define PCH_DEV_ID_AE1E 0xAE1E 1852 #define PCH_DEV_ID_AE1F 0xAE1F 1853 1854 // ARL PCH Dev IDs 1855 #define PCH_DEV_ID_7700 0x7700 1856 #define PCH_DEV_ID_7701 0x7701 1857 #define PCH_DEV_ID_7702 0x7702 1858 #define PCH_DEV_ID_7703 0x7703 1859 #define PCH_DEV_ID_7704 0x7704 1860 #define PCH_DEV_ID_7705 0x7705 1861 #define PCH_DEV_ID_7706 0x7706 1862 #define PCH_DEV_ID_7707 0x7707 1863 #define PCH_DEV_ID_7708 0x7708 1864 #define PCH_DEV_ID_7709 0x7709 1865 #define PCH_DEV_ID_770A 0x770A 1866 #define PCH_DEV_ID_770B 0x770B 1867 #define PCH_DEV_ID_770C 0x770C 1868 #define PCH_DEV_ID_770D 0x770D 1869 #define PCH_DEV_ID_770E 0x770E 1870 #define PCH_DEV_ID_770F 0x770F 1871 #define PCH_DEV_ID_7710 0x7710 1872 #define PCH_DEV_ID_7711 0x7711 1873 #define PCH_DEV_ID_7712 0x7712 1874 #define PCH_DEV_ID_7713 0x7713 1875 #define PCH_DEV_ID_7714 0x7714 1876 #define PCH_DEV_ID_7715 0x7715 1877 #define PCH_DEV_ID_7716 0x7716 1878 #define PCH_DEV_ID_7717 0x7717 1879 #define PCH_DEV_ID_7718 0x7718 1880 #define PCH_DEV_ID_7719 0x7719 1881 #define PCH_DEV_ID_771A 0x771A 1882 #define PCH_DEV_ID_771B 0x771B 1883 #define PCH_DEV_ID_771C 0x771C 1884 #define PCH_DEV_ID_771D 0x771D 1885 #define PCH_DEV_ID_771E 0x771E 1886 #define PCH_DEV_ID_771F 0x771F 1887 1888 //PVC Device ID 1889 #define DEV_ID_0BD0 0x0BD0 1890 #define DEV_ID_0BD5 0x0BD5 1891 #define DEV_ID_0BD6 0x0BD6 1892 #define DEV_ID_0BD7 0x0BD7 1893 #define DEV_ID_0BD8 0x0BD8 1894 #define DEV_ID_0BD9 0x0BD9 1895 #define DEV_ID_0BDA 0x0BDA 1896 #define DEV_ID_0BDB 0x0BDB 1897 #define DEV_ID_0B69 0x0B69 1898 #define DEV_ID_0B6E 0x0B6E 1899 #define DEV_ID_0BD4 0x0BD4 1900 1901 // Macro to identify PVC device ID 1902 #define GFX_IS_XT_CONFIG(d) ((d == DEV_ID_0BD5) || \ 1903 (d == DEV_ID_0BD6) || \ 1904 (d == DEV_ID_0BD7) || \ 1905 (d == DEV_ID_0BD8) || \ 1906 (d == DEV_ID_0BD9) || \ 1907 (d == DEV_ID_0BDA) || \ 1908 (d == DEV_ID_0BDB) || \ 1909 (d == DEV_ID_0B69) || \ 1910 (d == DEV_ID_0B6E) || \ 1911 (d == DEV_ID_0BD4)) 1912 1913 //DG2 Device IDs 1914 #define DEV_ID_4F80 0x4F80 1915 #define DEV_ID_4F81 0x4F81 1916 #define DEV_ID_4F82 0x4F82 1917 #define DEV_ID_4F83 0x4F83 1918 #define DEV_ID_4F84 0x4F84 1919 #define DEV_ID_4F85 0x4F85 1920 #define DEV_ID_4F86 0x4F86 1921 #define DEV_ID_4F87 0x4F87 1922 #define DEV_ID_4F88 0x4F88 1923 #define DEV_ID_5690 0x5690 1924 #define DEV_ID_5691 0x5691 1925 #define DEV_ID_5692 0x5692 1926 #define DEV_ID_5693 0x5693 1927 #define DEV_ID_5694 0x5694 1928 #define DEV_ID_5695 0x5695 1929 #define DEV_ID_5696 0x5696 1930 #define DEV_ID_5697 0x5697 1931 #define DEV_ID_5698 0x5698 1932 #define DEV_ID_56A0 0x56A0 1933 #define DEV_ID_56A1 0x56A1 1934 #define DEV_ID_56A2 0x56A2 1935 #define DEV_ID_56A3 0x56A3 1936 #define DEV_ID_56A4 0x56A4 1937 #define DEV_ID_56A5 0x56A5 1938 #define DEV_ID_56A6 0x56A6 1939 #define DEV_ID_56B0 0x56B0 1940 #define DEV_ID_56B1 0x56B1 1941 #define DEV_ID_56B2 0x56B2 1942 #define DEV_ID_56B3 0x56B3 1943 #define DEV_ID_56BA 0x56BA 1944 #define DEV_ID_56BB 0x56BB 1945 #define DEV_ID_56BC 0x56BC 1946 #define DEV_ID_56BD 0x56BD 1947 #define DEV_ID_56BE 0x56BE 1948 #define DEV_ID_56BF 0x56BF 1949 #define DEV_ID_56C0 0x56C0 1950 #define DEV_ID_56C1 0x56C1 1951 #define DEV_ID_56C2 0x56C2 1952 1953 // RPL-P/U 1954 #define DEV_ID_A7A0 0xA7A0 1955 #define DEV_ID_A7A1 0xA7A1 1956 #define DEV_ID_A7A8 0xA7A8 1957 #define DEV_ID_A7A9 0xA7A9 1958 #define DEV_ID_A720 0xA720 1959 #define DEV_ID_A721 0xA721 1960 #define DEV_ID_A7AA 0xA7AA 1961 #define DEV_ID_A7AB 0xA7AB 1962 #define DEV_ID_A7AC 0xA7AC 1963 #define DEV_ID_A7AD 0xA7AD 1964 1965 // ADL-N 1966 #define DEV_ID_46D0 0x46D0 1967 #define DEV_ID_46D1 0x46D1 1968 #define DEV_ID_46D2 0x46D2 1969 #define DEV_ID_46D3 0x46D3 1970 #define DEV_ID_46D4 0x46D4 1971 1972 // MTL 1973 #define DEV_ID_7D40 0x7D40 1974 #define DEV_ID_7D45 0x7D45 1975 #define DEV_ID_7D55 0x7D55 1976 #define DEV_ID_7D57 0x7D57 1977 #define DEV_ID_7D60 0x7D60 1978 #define DEV_ID_7DD5 0x7DD5 1979 #define DEV_ID_7DD7 0x7DD7 1980 1981 // ARL-S 1982 #define DEV_ID_7D67 0x7D67 1983 1984 // ARL-H 1985 #define DEV_ID_7D41 0x7D41 1986 #define DEV_ID_7D51 0x7D51 1987 #define DEV_ID_7DD1 0x7DD1 1988 1989 // LNL 1990 #define DEV_ID_64A0 0x64A0 1991 #define DEV_ID_6420 0x6420 1992 #define DEV_ID_64B0 0x64B0 1993 1994 //BMG 1995 #define DEV_ID_E202 0xE202 1996 #define DEV_ID_E20B 0xE20B 1997 #define DEV_ID_E20C 0xE20C 1998 #define DEV_ID_E20D 0xE20D 1999 #define DEV_ID_E212 0xE212 2000 2001 #define MGM_HAS 0 2002 2003 //#define SDG_HAS 1 //Reserve place for Springdale-G HAS 2004 //#define SDG_SUPPORT 1 //Springdale G build switch 2005 2006 // Macro to identify DG2 device IDs 2007 #define GFX_IS_DG2_G11_CONFIG(d) ( ( d == DEV_ID_56A5 ) || \ 2008 ( d == DEV_ID_56A6 ) || \ 2009 ( d == DEV_ID_5693 ) || \ 2010 ( d == DEV_ID_5694 ) || \ 2011 ( d == DEV_ID_5695 ) || \ 2012 ( d == DEV_ID_56B0 ) || \ 2013 ( d == DEV_ID_56B1 ) || \ 2014 ( d == DEV_ID_56BA ) || \ 2015 ( d == DEV_ID_56BB ) || \ 2016 ( d == DEV_ID_56BC ) || \ 2017 ( d == DEV_ID_56BD ) || \ 2018 ( d == DEV_ID_56C1 ) || \ 2019 ( d == DEV_ID_4F87 ) || \ 2020 ( d == DEV_ID_4F88 )) 2021 2022 #define GFX_IS_DG2_G10_CONFIG(d) ( ( d == DEV_ID_56A0 ) || \ 2023 ( d == DEV_ID_56A1 ) || \ 2024 ( d == DEV_ID_56A2 ) || \ 2025 ( d == DEV_ID_5690 ) || \ 2026 ( d == DEV_ID_5691 ) || \ 2027 ( d == DEV_ID_5692 ) || \ 2028 ( d == DEV_ID_56BE ) || \ 2029 ( d == DEV_ID_56BF ) || \ 2030 ( d == DEV_ID_56C0 ) || \ 2031 ( d == DEV_ID_56C2 ) || \ 2032 ( d == DEV_ID_4F80 ) || \ 2033 ( d == DEV_ID_4F81 ) || \ 2034 ( d == DEV_ID_4F82 ) || \ 2035 ( d == DEV_ID_4F83 ) || \ 2036 ( d == DEV_ID_4F84 )) 2037 2038 #define GFX_IS_DG2_G12_CONFIG(d) ( ( d == DEV_ID_4F85 ) || \ 2039 ( d == DEV_ID_4F86 ) || \ 2040 ( d == DEV_ID_56A3 ) || \ 2041 ( d == DEV_ID_56A4 ) || \ 2042 ( d == DEV_ID_5696 ) || \ 2043 ( d == DEV_ID_5697 ) || \ 2044 ( d == DEV_ID_56B2 ) || \ 2045 ( d == DEV_ID_56B3 )) 2046 2047 // Macro to identify ARL-S Device ID 2048 #define GFX_IS_ARL_S(d) ( ( d == DEV_ID_7D67 ) ) 2049 2050 // Macro to identify ARL-H Device ID 2051 #define GFX_IS_ARL_H(d) ( ( d == DEV_ID_7D41 ) || \ 2052 ( d == DEV_ID_7D51 ) || \ 2053 ( d == DEV_ID_7DD1 )) 2054 2055 //we define the highest cap and lower cap of stepping IDs 2056 #define SI_REV_ID(lo,hi) (lo | hi<<16) 2057 2058 #define SI_REV_LO(SteppingID) (SteppingID & 0xFFFF) 2059 2060 #define SI_WA_FROM(ulRevID, STEPPING) (ulRevID >= (int)SI_REV_LO(STEPPING)) 2061 2062 //define DG2 Media Rev ID 2063 #ifdef DG2_MEDIA_REV_ID_B0 2064 #undef DG2_MEDIA_REV_ID_B0 2065 #endif 2066 #define DG2_MEDIA_REV_ID_B0 SI_REV_ID(4,4) 2067 2068 #ifdef ACM_G10_MEDIA_REV_ID_B0 2069 #undef ACM_G10_MEDIA_REV_ID_B0 2070 #endif 2071 #define ACM_G10_MEDIA_REV_ID_B0 SI_REV_ID(4,4) 2072 2073 #endif 2074