1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /**
22 *******************************************************************************
23 * @file
24 * ih264e_api.c
25 *
26 * @brief
27 * Contains api function definitions for H264 encoder
28 *
29 * @author
30 * ittiam
31 *
32 * @par List of Functions:
33 * - api_check_struct_sanity
34 * - ih264e_codec_update_config
35 * - ih264e_set_default_params
36 * - ih264e_init
37 * - ih264e_get_num_rec
38 * - ih264e_fill_num_mem_rec
39 * - ih264e_init_mem_rec
40 * - ih264e_retrieve_memrec
41 * - ih264e_set_flush_mode
42 * - ih264e_get_buf_info
43 * - ih264e_set_dimensions
44 * - ih264e_set_frame_rate
45 * - ih264e_set_bit_rate
46 * - ih264e_set_frame_type
47 * - ih264e_set_qp
48 * - ih264e_set_enc_mode
49 * - ih264e_set_vbv_params
50 * - ih264_set_air_params
51 * - ih264_set_me_params
52 * - ih264_set_ipe_params
53 * - ih264_set_gop_params
54 * - ih264_set_profile_params
55 * - ih264_set_deblock_params
56 * - ih264e_set_num_cores
57 * - ih264e_reset
58 * - ih264e_ctl
59 * - ih264e_api_function
60 *
61 * @remarks
62 * none
63 *
64 *******************************************************************************
65 */
66
67 /*****************************************************************************/
68 /* File Includes */
69 /*****************************************************************************/
70
71 /* System Include Files */
72 #include <stdio.h>
73 #include <stddef.h>
74 #include <stdlib.h>
75 #include <string.h>
76 #include <assert.h>
77
78 /* User Include Files */
79 #include "ih264e_config.h"
80 #include "ih264_typedefs.h"
81 #include "iv2.h"
82 #include "ive2.h"
83 #include "ithread.h"
84
85 #include "ih264_debug.h"
86 #include "ih264_macros.h"
87 #include "ih264_error.h"
88 #include "ih264_defs.h"
89 #include "ih264_mem_fns.h"
90 #include "ih264_padding.h"
91 #include "ih264_structs.h"
92 #include "ih264_size_defs.h"
93 #include "ih264_trans_quant_itrans_iquant.h"
94 #include "ih264_inter_pred_filters.h"
95 #include "ih264_intra_pred_filters.h"
96 #include "ih264_deblk_edge_filters.h"
97 #include "ih264_common_tables.h"
98 #include "ih264_cavlc_tables.h"
99 #include "ih264_cabac_tables.h"
100 #include "ih264_buf_mgr.h"
101 #include "ih264_list.h"
102 #include "ih264_dpb_mgr.h"
103 #include "ih264_platform_macros.h"
104
105 #include "ime_defs.h"
106 #include "ime_distortion_metrics.h"
107 #include "ime_structs.h"
108
109 #include "irc_mem_req_and_acq.h"
110 #include "irc_cntrl_param.h"
111 #include "irc_frame_info_collector.h"
112 #include "irc_rate_control_api.h"
113
114 #include "ih264e.h"
115 #include "ih264e_error.h"
116 #include "ih264e_version.h"
117 #include "ih264e_defs.h"
118 #include "ih264e_globals.h"
119 #include "ih264e_time_stamp.h"
120 #include "ih264e_modify_frm_rate.h"
121 #include "ih264e_rate_control.h"
122 #include "ih264e_rc_mem_interface.h"
123 #include "ih264e_bitstream.h"
124 #include "ih264e_cabac_structs.h"
125 #include "ih264e_structs.h"
126 #include "ih264e_utils.h"
127 #include "ih264e_core_coding.h"
128 #include "ih264e_cavlc.h"
129 #include "ih264e_master.h"
130 #include "ih264e_fmt_conv.h"
131 #include "ih264e_platform_macros.h"
132
133
134 /*****************************************************************************/
135 /* Function Definitions */
136 /*****************************************************************************/
137
138 /**
139 *******************************************************************************
140 *
141 * @brief
142 * Used to test arguments for corresponding API call
143 *
144 * @par Description:
145 * For each command the arguments are validated
146 *
147 * @param[in] ps_handle
148 * Codec handle at API level
149 *
150 * @param[in] pv_api_ip
151 * Pointer to input structure
152 *
153 * @param[out] pv_api_op
154 * Pointer to output structure
155 *
156 * @returns error status
157 *
158 * @remarks none
159 *
160 *******************************************************************************
161 */
api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)162 static IV_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
163 void *pv_api_ip,
164 void *pv_api_op)
165 {
166 /* api call */
167 WORD32 command = IV_CMD_NA;
168
169 /* input structure expected by the api call */
170 UWORD32 *pu4_api_ip = pv_api_ip;
171
172 /* output structure expected by the api call */
173 UWORD32 *pu4_api_op = pv_api_op;
174
175 /* temp var */
176 WORD32 i, j;
177
178 if (NULL == pv_api_op || NULL == pv_api_ip)
179 {
180 return (IV_FAIL);
181 }
182
183 /* get command */
184 command = pu4_api_ip[1];
185
186 /* set error code */
187 pu4_api_op[1] = 0;
188
189 /* error checks on handle */
190 switch (command)
191 {
192 case IV_CMD_GET_NUM_MEM_REC:
193 case IV_CMD_FILL_NUM_MEM_REC:
194 break;
195
196 case IV_CMD_INIT:
197 if (ps_handle == NULL)
198 {
199 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
200 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
201 return IV_FAIL;
202 }
203
204 if (ps_handle->u4_size != sizeof(iv_obj_t))
205 {
206 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
207 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
208 return IV_FAIL;
209 }
210 break;
211
212 case IVE_CMD_QUEUE_INPUT:
213 case IVE_CMD_QUEUE_OUTPUT:
214 case IVE_CMD_DEQUEUE_OUTPUT:
215 case IVE_CMD_GET_RECON:
216 case IV_CMD_RETRIEVE_MEMREC:
217 case IVE_CMD_VIDEO_CTL:
218 case IVE_CMD_VIDEO_ENCODE:
219
220 if (ps_handle == NULL)
221 {
222 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
223 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
224 return IV_FAIL;
225 }
226
227 if (ps_handle->u4_size != sizeof(iv_obj_t))
228 {
229 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
230 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
231 return IV_FAIL;
232 }
233
234 if (ps_handle->pv_fxns != ih264e_api_function)
235 {
236 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
237 *(pu4_api_op + 1) |= IVE_ERR_API_FUNCTION_PTR_NULL;
238 return IV_FAIL;
239 }
240
241 if (ps_handle->pv_codec_handle == NULL)
242 {
243 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
244 *(pu4_api_op + 1) |= IVE_ERR_INVALID_CODEC_HANDLE;
245 return IV_FAIL;
246 }
247 break;
248
249 default:
250 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
251 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
252 return IV_FAIL;
253 }
254
255 /* error checks on input output structures */
256 switch (command)
257 {
258 case IV_CMD_GET_NUM_MEM_REC:
259 {
260 ih264e_num_mem_rec_ip_t *ps_ip = pv_api_ip;
261 ih264e_num_mem_rec_op_t *ps_op = pv_api_op;
262
263 ps_op->s_ive_op.u4_error_code = 0;
264
265 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_num_mem_rec_ip_t))
266 {
267 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
268 ps_op->s_ive_op.u4_error_code |=
269 IVE_ERR_IP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
270 return (IV_FAIL);
271 }
272
273 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_num_mem_rec_op_t))
274 {
275 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
276 ps_op->s_ive_op.u4_error_code |=
277 IVE_ERR_OP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
278 return (IV_FAIL);
279 }
280 break;
281 }
282
283 case IV_CMD_FILL_NUM_MEM_REC:
284 {
285 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
286 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op;
287
288 iv_mem_rec_t *ps_mem_rec = NULL;
289
290 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
291 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
292
293 ps_op->s_ive_op.u4_error_code = 0;
294
295 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_fill_mem_rec_ip_t))
296 {
297 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
298 ps_op->s_ive_op.u4_error_code |=
299 IVE_ERR_IP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
300 return (IV_FAIL);
301 }
302
303 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_fill_mem_rec_op_t))
304 {
305 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
306 ps_op->s_ive_op.u4_error_code |=
307 IVE_ERR_OP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
308 return (IV_FAIL);
309 }
310
311 if (max_wd < MIN_WD || max_wd > MAX_WD)
312 {
313 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
314 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
315 return (IV_FAIL);
316 }
317
318 if (max_ht < MIN_HT || max_ht > MAX_HT)
319 {
320 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
321 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
322 return (IV_FAIL);
323 }
324
325 /* verify number of mem rec ptr */
326 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
327 {
328 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
329 ps_op->s_ive_op.u4_error_code |=
330 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
331 return (IV_FAIL);
332 }
333
334 /* verify number of mem records */
335 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT)
336 {
337 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
338 ps_op->s_ive_op.u4_error_code |=
339 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
340 return IV_FAIL;
341 }
342
343 /* check mem records sizes are correct */
344 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
345 for (i = 0; i < MEM_REC_CNT; i++)
346 {
347 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
348 {
349 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
350 ps_op->s_ive_op.u4_error_code |=
351 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
352 return IV_FAIL;
353 }
354 }
355 break;
356 }
357
358 case IV_CMD_INIT:
359 {
360 ih264e_init_ip_t *ps_ip = pv_api_ip;
361 ih264e_init_op_t *ps_op = pv_api_op;
362
363 iv_mem_rec_t *ps_mem_rec = NULL;
364
365 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
366 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
367
368 ps_op->s_ive_op.u4_error_code = 0;
369
370 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_init_ip_t))
371 {
372 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
373 ps_op->s_ive_op.u4_error_code |=
374 IVE_ERR_IP_INIT_API_STRUCT_SIZE_INCORRECT;
375 return (IV_FAIL);
376 }
377
378 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_init_op_t))
379 {
380 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
381 ps_op->s_ive_op.u4_error_code |=
382 IVE_ERR_OP_INIT_API_STRUCT_SIZE_INCORRECT;
383 return (IV_FAIL);
384 }
385
386 if (max_wd < MIN_WD || max_wd > MAX_WD)
387 {
388 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
389 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
390 return (IV_FAIL);
391 }
392
393 if (max_ht < MIN_HT || max_ht > MAX_HT)
394 {
395 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
396 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
397 return (IV_FAIL);
398 }
399
400 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_PIC_CNT ||
401 ps_ip->s_ive_ip.u4_max_ref_cnt < MIN_REF_PIC_CNT)
402 {
403 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
404 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
405 return (IV_FAIL);
406 }
407
408 if (ps_ip->s_ive_ip.u4_max_reorder_cnt != 0)
409 {
410 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
411 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
412 return (IV_FAIL);
413 }
414
415 if ((ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_10)
416 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_1B)
417 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_11)
418 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_12)
419 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_13)
420 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_20)
421 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_21)
422 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_22)
423 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_30)
424 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_31)
425 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_32)
426 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_40)
427 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_41)
428 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_42)
429 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_50)
430 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_51))
431 {
432 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
433 ps_op->s_ive_op.u4_error_code |=
434 IH264E_CODEC_LEVEL_NOT_SUPPORTED;
435 return (IV_FAIL);
436 }
437
438 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
439 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE)
440 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV)
441 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
442 {
443 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
444 ps_op->s_ive_op.u4_error_code |=
445 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
446 return (IV_FAIL);
447 }
448
449 if ((ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420P)
450 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_UV)
451 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_VU))
452 {
453 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
454 ps_op->s_ive_op.u4_error_code |=
455 IH264E_RECON_CHROMA_FORMAT_NOT_SUPPORTED;
456 return (IV_FAIL);
457 }
458
459 if ((ps_ip->s_ive_ip.e_rc_mode != IVE_RC_NONE)
460 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_STORAGE)
461 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_CBR_NON_LOW_DELAY))
462 {
463 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
464 ps_op->s_ive_op.u4_error_code |=
465 IH264E_RATE_CONTROL_MODE_NOT_SUPPORTED;
466 return (IV_FAIL);
467 }
468
469 if (ps_ip->s_ive_ip.u4_max_framerate > DEFAULT_MAX_FRAMERATE)
470 {
471 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
472 ps_op->s_ive_op.u4_error_code |=
473 IH264E_FRAME_RATE_NOT_SUPPORTED;
474 return (IV_FAIL);
475 }
476
477 if (ps_ip->s_ive_ip.u4_max_bitrate > DEFAULT_MAX_BITRATE)
478 {
479 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
480 ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED;
481 return (IV_FAIL);
482 }
483
484 if (ps_ip->s_ive_ip.u4_num_bframes > MAX_NUM_BFRAMES)
485 {
486 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
487 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
488 return (IV_FAIL);
489 }
490
491 if (ps_ip->s_ive_ip.u4_num_bframes
492 && (ps_ip->s_ive_ip.u4_max_ref_cnt < 2))
493 {
494 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
495 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
496 return (IV_FAIL);
497 }
498
499 if (ps_ip->s_ive_ip.e_content_type != IV_PROGRESSIVE)
500 {
501 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
502 ps_op->s_ive_op.u4_error_code |=
503 IH264E_CONTENT_TYPE_NOT_SUPPORTED;
504 return (IV_FAIL);
505 }
506
507 if (ps_ip->s_ive_ip.u4_max_srch_rng_x > DEFAULT_MAX_SRCH_RANGE_X)
508 {
509 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
510 ps_op->s_ive_op.u4_error_code |=
511 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
512 return (IV_FAIL);
513 }
514
515 if (ps_ip->s_ive_ip.u4_max_srch_rng_y > DEFAULT_MAX_SRCH_RANGE_Y)
516 {
517 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
518 ps_op->s_ive_op.u4_error_code |=
519 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
520 return (IV_FAIL);
521 }
522
523 if ((ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_NONE)
524 && (ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_BLOCKS))
525 {
526 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
527 ps_op->s_ive_op.u4_error_code |=
528 IH264E_SLICE_TYPE_INPUT_INVALID;
529 return (IV_FAIL);
530 }
531
532 if (ps_ip->s_ive_ip.e_slice_mode == IVE_SLICE_MODE_BLOCKS)
533 {
534 if (ps_ip->s_ive_ip.u4_slice_param == 0
535 || ps_ip->s_ive_ip.u4_slice_param > ((UWORD32)max_ht >> 4))
536 {
537 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
538 ps_op->s_ive_op.u4_error_code |=
539 IH264E_SLICE_PARAM_INPUT_INVALID;
540 return (IV_FAIL);
541 }
542 }
543
544 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
545 {
546 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
547 ps_op->s_ive_op.u4_error_code |=
548 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
549 return (IV_FAIL);
550 }
551
552 /* verify number of mem records */
553 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT)
554 {
555 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
556 ps_op->s_ive_op.u4_error_code |=
557 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
558 return (IV_FAIL);
559 }
560
561 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
562
563 /* check memrecords sizes are correct */
564 for (i = 0; i <((WORD32)ps_ip->s_ive_ip.u4_num_mem_rec); i++)
565 {
566 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
567 {
568 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
569 ps_op->s_ive_op.u4_error_code |=
570 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
571 return IV_FAIL;
572 }
573
574 /* check memrecords pointers are not NULL */
575 if (ps_mem_rec[i].pv_base == NULL)
576 {
577 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
578 ps_op->s_ive_op.u4_error_code |=
579 IVE_ERR_MEM_REC_BASE_POINTER_NULL;
580 return IV_FAIL;
581 }
582 }
583
584 /* verify memtabs for overlapping regions */
585 {
586 void *start[MEM_REC_CNT];
587 void *end[MEM_REC_CNT];
588
589 start[0] = (ps_mem_rec[0].pv_base);
590 end[0] = ((UWORD8 *) ps_mem_rec[0].pv_base)
591 + ps_mem_rec[0].u4_mem_size - 1;
592
593 for (i = 1; i < MEM_REC_CNT; i++)
594 {
595 /* This array is populated to check memtab overlap */
596 start[i] = (ps_mem_rec[i].pv_base);
597 end[i] = ((UWORD8 *) ps_mem_rec[i].pv_base)
598 + ps_mem_rec[i].u4_mem_size - 1;
599
600 for (j = 0; j < i; j++)
601 {
602 if ((start[i] >= start[j]) && (start[i] <= end[j]))
603 {
604 ps_op->s_ive_op.u4_error_code |= 1
605 << IVE_UNSUPPORTEDPARAM;
606 ps_op->s_ive_op.u4_error_code |=
607 IVE_ERR_MEM_REC_OVERLAP_ERR;
608 return IV_FAIL;
609 }
610
611 if ((end[i] >= start[j]) && (end[i] <= end[j]))
612 {
613 ps_op->s_ive_op.u4_error_code |= 1
614 << IVE_UNSUPPORTEDPARAM;
615 ps_op->s_ive_op.u4_error_code |=
616 IVE_ERR_MEM_REC_OVERLAP_ERR;
617 return IV_FAIL;
618 }
619
620 if ((start[i] < start[j]) && (end[i] > end[j]))
621 {
622 ps_op->s_ive_op.u4_error_code |= 1
623 << IVE_UNSUPPORTEDPARAM;
624 ps_op->s_ive_op.u4_error_code |=
625 IVE_ERR_MEM_REC_OVERLAP_ERR;
626 return IV_FAIL;
627 }
628 }
629 }
630 }
631
632 /* re-validate mem records with init config */
633 {
634 /* mem records */
635 iv_mem_rec_t s_mem_rec_ittiam_api[MEM_REC_CNT];
636
637 /* api interface structs */
638 ih264e_fill_mem_rec_ip_t s_ip;
639 ih264e_fill_mem_rec_op_t s_op;
640
641 /* error status */
642 IV_STATUS_T e_status;
643
644 /* temp var */
645 WORD32 i;
646
647 s_ip.s_ive_ip.u4_size = sizeof(ih264e_fill_mem_rec_ip_t);
648 s_op.s_ive_op.u4_size = sizeof(ih264e_fill_mem_rec_op_t);
649
650 s_ip.s_ive_ip.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
651 s_ip.s_ive_ip.ps_mem_rec = s_mem_rec_ittiam_api;
652 s_ip.s_ive_ip.u4_max_wd = max_wd;
653 s_ip.s_ive_ip.u4_max_ht = max_ht;
654 s_ip.s_ive_ip.u4_num_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
655 s_ip.s_ive_ip.u4_max_level = ps_ip->s_ive_ip.u4_max_level;
656 s_ip.s_ive_ip.u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
657 s_ip.s_ive_ip.u4_max_reorder_cnt =
658 ps_ip->s_ive_ip.u4_max_reorder_cnt;
659 s_ip.s_ive_ip.e_color_format = ps_ip->s_ive_ip.e_inp_color_fmt;
660 s_ip.s_ive_ip.u4_max_srch_rng_x =
661 ps_ip->s_ive_ip.u4_max_srch_rng_x;
662 s_ip.s_ive_ip.u4_max_srch_rng_y =
663 ps_ip->s_ive_ip.u4_max_srch_rng_y;
664
665 for (i = 0; i < MEM_REC_CNT; i++)
666 {
667 s_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
668 }
669
670 /* fill mem records */
671 e_status = ih264e_api_function(NULL, (void *) &s_ip,
672 (void *) &s_op);
673
674 if (IV_FAIL == e_status)
675 {
676 ps_op->s_ive_op.u4_error_code = s_op.s_ive_op.u4_error_code;
677 return (IV_FAIL);
678 }
679
680 /* verify mem records */
681 for (i = 0; i < MEM_REC_CNT; i++)
682 {
683 if (ps_mem_rec[i].u4_mem_size
684 < s_mem_rec_ittiam_api[i].u4_mem_size)
685 {
686 ps_op->s_ive_op.u4_error_code |= 1
687 << IVE_UNSUPPORTEDPARAM;
688 ps_op->s_ive_op.u4_error_code |=
689 IVE_ERR_MEM_REC_INSUFFICIENT_SIZE;
690
691 return IV_FAIL;
692 }
693
694 if (ps_mem_rec[i].u4_mem_alignment
695 != s_mem_rec_ittiam_api[i].u4_mem_alignment)
696 {
697 ps_op->s_ive_op.u4_error_code |= 1
698 << IVE_UNSUPPORTEDPARAM;
699 ps_op->s_ive_op.u4_error_code |=
700 IVE_ERR_MEM_REC_ALIGNMENT_ERR;
701
702 return IV_FAIL;
703 }
704
705 if (ps_mem_rec[i].e_mem_type
706 != s_mem_rec_ittiam_api[i].e_mem_type)
707 {
708 UWORD32 check = IV_SUCCESS;
709 UWORD32 diff = s_mem_rec_ittiam_api[i].e_mem_type
710 - ps_mem_rec[i].e_mem_type;
711
712 if ((ps_mem_rec[i].e_mem_type
713 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM)
714 && (s_mem_rec_ittiam_api[i].e_mem_type
715 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
716 {
717 check = IV_FAIL;
718 }
719
720 if (3 != (s_mem_rec_ittiam_api[i].e_mem_type % 4))
721 {
722 /* It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or
723 * IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM */
724
725 if ((diff < 1) || (diff > 3))
726 {
727 /* Difference between 1 and 3 is okay for all cases other than the
728 * two filtered with the MOD condition above */
729 check = IV_FAIL;
730 }
731 }
732 else
733 {
734 if (diff == 1)
735 {
736 /* This particular case is when codec asked for External Persistent,
737 * but got Internal Scratch */
738 check = IV_FAIL;
739 }
740 if ((diff != 2) && (diff != 3))
741 {
742 check = IV_FAIL;
743 }
744 }
745
746 if (check == IV_FAIL)
747 {
748 ps_op->s_ive_op.u4_error_code |= 1
749 << IVE_UNSUPPORTEDPARAM;
750 ps_op->s_ive_op.u4_error_code |=
751 IVE_ERR_MEM_REC_INCORRECT_TYPE;
752
753 return IV_FAIL;
754 }
755 }
756 }
757 }
758 break;
759 }
760
761 case IVE_CMD_QUEUE_INPUT:
762 case IVE_CMD_QUEUE_OUTPUT:
763 case IVE_CMD_DEQUEUE_OUTPUT:
764 case IVE_CMD_GET_RECON:
765 break;
766
767 case IV_CMD_RETRIEVE_MEMREC:
768 {
769 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
770 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op;
771
772 iv_mem_rec_t *ps_mem_rec = NULL;
773
774 ps_op->s_ive_op.u4_error_code = 0;
775
776 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_retrieve_mem_rec_ip_t))
777 {
778 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
779 ps_op->s_ive_op.u4_error_code |=
780 IVE_ERR_IP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
781 return (IV_FAIL);
782 }
783
784 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_retrieve_mem_rec_op_t))
785 {
786 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
787 ps_op->s_ive_op.u4_error_code |=
788 IVE_ERR_OP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
789 return (IV_FAIL);
790 }
791
792 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
793 {
794 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
795 ps_op->s_ive_op.u4_error_code |=
796 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
797 return (IV_FAIL);
798 }
799
800 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
801
802 /* check memrecords sizes are correct */
803 for (i = 0; i < MEM_REC_CNT; i++)
804 {
805 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
806 {
807 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
808 ps_op->s_ive_op.u4_error_code |=
809 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
810 return IV_FAIL;
811 }
812 }
813 break;
814 }
815
816 case IVE_CMD_VIDEO_ENCODE:
817 {
818 ih264e_video_encode_ip_t *ps_ip = pv_api_ip;
819 ih264e_video_encode_op_t *ps_op = pv_api_op;
820
821 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_video_encode_ip_t))
822 {
823 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
824 ps_op->s_ive_op.u4_error_code |=
825 IVE_ERR_IP_ENCODE_API_STRUCT_SIZE_INCORRECT;
826 return (IV_FAIL);
827 }
828
829 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_video_encode_op_t))
830 {
831 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
832 ps_op->s_ive_op.u4_error_code |=
833 IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT;
834 return (IV_FAIL);
835 }
836
837 break;
838 }
839
840 case IVE_CMD_VIDEO_CTL:
841 {
842 /* ptr to input structure */
843 WORD32 *pu4_ptr_cmd = pv_api_ip;
844
845 /* sub command */
846 WORD32 sub_command = pu4_ptr_cmd[2];
847
848 switch (sub_command)
849 {
850 case IVE_CMD_CTL_SETDEFAULT:
851 {
852 ih264e_ctl_setdefault_ip_t *ps_ip = pv_api_ip;
853 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op;
854
855 if (ps_ip->s_ive_ip.u4_size
856 != sizeof(ih264e_ctl_setdefault_ip_t))
857 {
858 ps_op->s_ive_op.u4_error_code |= 1
859 << IVE_UNSUPPORTEDPARAM;
860 ps_op->s_ive_op.u4_error_code |=
861 IVE_ERR_IP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
862 return IV_FAIL;
863 }
864
865 if (ps_op->s_ive_op.u4_size
866 != sizeof(ih264e_ctl_setdefault_op_t))
867 {
868 ps_op->s_ive_op.u4_error_code |= 1
869 << IVE_UNSUPPORTEDPARAM;
870 ps_op->s_ive_op.u4_error_code |=
871 IVE_ERR_OP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
872 return IV_FAIL;
873 }
874 break;
875 }
876
877 case IVE_CMD_CTL_GETBUFINFO:
878 {
879 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
880
881 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
882 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op;
883
884 if (ps_ip->s_ive_ip.u4_size
885 != sizeof(ih264e_ctl_getbufinfo_ip_t))
886 {
887 ps_op->s_ive_op.u4_error_code |= 1
888 << IVE_UNSUPPORTEDPARAM;
889 ps_op->s_ive_op.u4_error_code |=
890 IVE_ERR_IP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
891 return IV_FAIL;
892 }
893
894 if (ps_op->s_ive_op.u4_size
895 != sizeof(ih264e_ctl_getbufinfo_op_t))
896 {
897 ps_op->s_ive_op.u4_error_code |= 1
898 << IVE_UNSUPPORTEDPARAM;
899 ps_op->s_ive_op.u4_error_code |=
900 IVE_ERR_OP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
901 return IV_FAIL;
902 }
903
904 if (ps_ip->s_ive_ip.u4_max_wd < MIN_WD)
905 {
906 ps_op->s_ive_op.u4_error_code |= 1
907 << IVE_UNSUPPORTEDPARAM;
908 ps_op->s_ive_op.u4_error_code |=
909 IH264E_WIDTH_NOT_SUPPORTED;
910 return (IV_FAIL);
911 }
912
913 if (ps_ip->s_ive_ip.u4_max_wd > ps_codec->s_cfg.u4_max_wd)
914 {
915 ps_op->s_ive_op.u4_error_code |= 1
916 << IVE_UNSUPPORTEDPARAM;
917 ps_op->s_ive_op.u4_error_code |=
918 IH264E_WIDTH_NOT_SUPPORTED;
919 return (IV_FAIL);
920 }
921
922 if (ps_ip->s_ive_ip.u4_max_ht < MIN_HT)
923 {
924 ps_op->s_ive_op.u4_error_code |= 1
925 << IVE_UNSUPPORTEDPARAM;
926 ps_op->s_ive_op.u4_error_code |=
927 IH264E_HEIGHT_NOT_SUPPORTED;
928 return (IV_FAIL);
929 }
930
931 if (ps_ip->s_ive_ip.u4_max_ht > ps_codec->s_cfg.u4_max_ht)
932 {
933 ps_op->s_ive_op.u4_error_code |= 1
934 << IVE_UNSUPPORTEDPARAM;
935 ps_op->s_ive_op.u4_error_code |=
936 IH264E_HEIGHT_NOT_SUPPORTED;
937 return (IV_FAIL);
938 }
939
940 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
941 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE)
942 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV)
943 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
944 {
945 ps_op->s_ive_op.u4_error_code |= 1
946 << IVE_UNSUPPORTEDPARAM;
947 ps_op->s_ive_op.u4_error_code |=
948 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
949 return (IV_FAIL);
950 }
951 break;
952 }
953
954 case IVE_CMD_CTL_GETVERSION:
955 {
956 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
957 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op;
958
959 if (ps_ip->s_ive_ip.u4_size
960 != sizeof(ih264e_ctl_getversioninfo_ip_t))
961 {
962 ps_op->s_ive_op.u4_error_code |= 1
963 << IVE_UNSUPPORTEDPARAM;
964 ps_op->s_ive_op.u4_error_code |=
965 IVE_ERR_IP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
966 return IV_FAIL;
967 }
968
969 if (ps_op->s_ive_op.u4_size
970 != sizeof(ih264e_ctl_getversioninfo_op_t))
971 {
972 ps_op->s_ive_op.u4_error_code |= 1
973 << IVE_UNSUPPORTEDPARAM;
974 ps_op->s_ive_op.u4_error_code |=
975 IVE_ERR_OP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
976 return IV_FAIL;
977 }
978
979 if (ps_ip->s_ive_ip.pu1_version == NULL)
980 {
981 ps_op->s_ive_op.u4_error_code |= 1
982 << IVE_UNSUPPORTEDPARAM;
983 ps_op->s_ive_op.u4_error_code |=
984 IVE_ERR_CTL_GET_VERSION_BUFFER_IS_NULL;
985 return IV_FAIL;
986 }
987
988 break;
989 }
990
991 case IVE_CMD_CTL_FLUSH:
992 {
993 ih264e_ctl_flush_ip_t *ps_ip = pv_api_ip;
994 ih264e_ctl_flush_op_t *ps_op = pv_api_op;
995
996 if (ps_ip->s_ive_ip.u4_size
997 != sizeof(ih264e_ctl_flush_ip_t))
998 {
999 ps_op->s_ive_op.u4_error_code |= 1
1000 << IVE_UNSUPPORTEDPARAM;
1001 ps_op->s_ive_op.u4_error_code |=
1002 IVE_ERR_IP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
1003 return IV_FAIL;
1004 }
1005
1006 if (ps_op->s_ive_op.u4_size
1007 != sizeof(ih264e_ctl_flush_op_t))
1008 {
1009 ps_op->s_ive_op.u4_error_code |= 1
1010 << IVE_UNSUPPORTEDPARAM;
1011 ps_op->s_ive_op.u4_error_code |=
1012 IVE_ERR_OP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
1013 return IV_FAIL;
1014 }
1015
1016 break;
1017 }
1018
1019 case IVE_CMD_CTL_RESET:
1020 {
1021 ih264e_ctl_reset_ip_t *ps_ip = pv_api_ip;
1022 ih264e_ctl_reset_op_t *ps_op = pv_api_op;
1023
1024 if (ps_ip->s_ive_ip.u4_size
1025 != sizeof(ih264e_ctl_reset_ip_t))
1026 {
1027 ps_op->s_ive_op.u4_error_code |= 1
1028 << IVE_UNSUPPORTEDPARAM;
1029 ps_op->s_ive_op.u4_error_code |=
1030 IVE_ERR_IP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
1031 return IV_FAIL;
1032 }
1033
1034 if (ps_op->s_ive_op.u4_size
1035 != sizeof(ih264e_ctl_reset_op_t))
1036 {
1037 ps_op->s_ive_op.u4_error_code |= 1
1038 << IVE_UNSUPPORTEDPARAM;
1039 ps_op->s_ive_op.u4_error_code |=
1040 IVE_ERR_OP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
1041 return IV_FAIL;
1042 }
1043
1044 break;
1045 }
1046
1047 case IVE_CMD_CTL_SET_NUM_CORES:
1048 {
1049 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
1050 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op;
1051
1052 if (ps_ip->s_ive_ip.u4_size
1053 != sizeof(ih264e_ctl_set_num_cores_ip_t))
1054 {
1055 ps_op->s_ive_op.u4_error_code |= 1
1056 << IVE_UNSUPPORTEDPARAM;
1057 ps_op->s_ive_op.u4_error_code |=
1058 IVE_ERR_IP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
1059 return IV_FAIL;
1060 }
1061
1062 if (ps_op->s_ive_op.u4_size
1063 != sizeof(ih264e_ctl_set_num_cores_op_t))
1064 {
1065 ps_op->s_ive_op.u4_error_code |= 1
1066 << IVE_UNSUPPORTEDPARAM;
1067 ps_op->s_ive_op.u4_error_code |=
1068 IVE_ERR_OP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
1069 return IV_FAIL;
1070 }
1071
1072 if ((ps_ip->s_ive_ip.u4_num_cores < 1)
1073 || (ps_ip->s_ive_ip.u4_num_cores > MAX_NUM_CORES))
1074 {
1075 ps_op->s_ive_op.u4_error_code |= 1
1076 << IVE_UNSUPPORTEDPARAM;
1077 ps_op->s_ive_op.u4_error_code |=
1078 IH264E_INVALID_NUM_CORES;
1079 return IV_FAIL;
1080 }
1081
1082 break;
1083 }
1084
1085 case IVE_CMD_CTL_SET_DIMENSIONS:
1086 {
1087 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
1088
1089 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
1090 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op;
1091
1092 if (ps_ip->s_ive_ip.u4_size
1093 != sizeof(ih264e_ctl_set_dimensions_ip_t))
1094 {
1095 ps_op->s_ive_op.u4_error_code |= 1
1096 << IVE_UNSUPPORTEDPARAM;
1097 ps_op->s_ive_op.u4_error_code |=
1098 IVE_ERR_IP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
1099 return IV_FAIL;
1100 }
1101
1102 if (ps_op->s_ive_op.u4_size
1103 != sizeof(ih264e_ctl_set_dimensions_op_t))
1104 {
1105 ps_op->s_ive_op.u4_error_code |= 1
1106 << IVE_UNSUPPORTEDPARAM;
1107 ps_op->s_ive_op.u4_error_code |=
1108 IVE_ERR_OP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
1109 return IV_FAIL;
1110 }
1111
1112 if (ps_ip->s_ive_ip.u4_wd < MIN_WD)
1113 {
1114 ps_op->s_ive_op.u4_error_code |= 1
1115 << IVE_UNSUPPORTEDPARAM;
1116 ps_op->s_ive_op.u4_error_code |=
1117 IH264E_WIDTH_NOT_SUPPORTED;
1118 return (IV_FAIL);
1119 }
1120
1121 if (ps_ip->s_ive_ip.u4_wd > ps_codec->s_cfg.u4_max_wd)
1122 {
1123 ps_op->s_ive_op.u4_error_code |= 1
1124 << IVE_UNSUPPORTEDPARAM;
1125 ps_op->s_ive_op.u4_error_code |=
1126 IH264E_WIDTH_NOT_SUPPORTED;
1127 return (IV_FAIL);
1128 }
1129
1130 if (ps_ip->s_ive_ip.u4_ht < MIN_HT)
1131 {
1132 ps_op->s_ive_op.u4_error_code |= 1
1133 << IVE_UNSUPPORTEDPARAM;
1134 ps_op->s_ive_op.u4_error_code |=
1135 IH264E_HEIGHT_NOT_SUPPORTED;
1136 return (IV_FAIL);
1137 }
1138
1139 if (ps_ip->s_ive_ip.u4_ht > ps_codec->s_cfg.u4_max_ht)
1140 {
1141 ps_op->s_ive_op.u4_error_code |= 1
1142 << IVE_UNSUPPORTEDPARAM;
1143 ps_op->s_ive_op.u4_error_code |=
1144 IH264E_HEIGHT_NOT_SUPPORTED;
1145 return (IV_FAIL);
1146 }
1147
1148 if(ps_ip->s_ive_ip.u4_wd & 1)
1149 {
1150 ps_op->s_ive_op.u4_error_code |= 1
1151 << IVE_UNSUPPORTEDPARAM;
1152 ps_op->s_ive_op.u4_error_code |=
1153 IH264E_WIDTH_NOT_SUPPORTED;
1154 return (IV_FAIL);
1155 }
1156
1157 if(ps_ip->s_ive_ip.u4_ht & 1)
1158 {
1159 ps_op->s_ive_op.u4_error_code |= 1
1160 << IVE_UNSUPPORTEDPARAM;
1161 ps_op->s_ive_op.u4_error_code |=
1162 IH264E_HEIGHT_NOT_SUPPORTED;
1163 return (IV_FAIL);
1164 }
1165
1166 break;
1167 }
1168
1169 case IVE_CMD_CTL_SET_FRAMERATE:
1170 {
1171 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
1172 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
1173
1174 if (ps_ip->s_ive_ip.u4_size
1175 != sizeof(ih264e_ctl_set_frame_rate_ip_t))
1176 {
1177 ps_op->s_ive_op.u4_error_code |= 1
1178 << IVE_UNSUPPORTEDPARAM;
1179 ps_op->s_ive_op.u4_error_code |=
1180 IVE_ERR_IP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1181 return IV_FAIL;
1182 }
1183
1184 if (ps_op->s_ive_op.u4_size
1185 != sizeof(ih264e_ctl_set_frame_rate_op_t))
1186 {
1187 ps_op->s_ive_op.u4_error_code |= 1
1188 << IVE_UNSUPPORTEDPARAM;
1189 ps_op->s_ive_op.u4_error_code |=
1190 IVE_ERR_OP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1191 return IV_FAIL;
1192 }
1193
1194 if (((ps_ip->s_ive_ip.u4_src_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE)
1195 || ((ps_ip->s_ive_ip.u4_tgt_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE))
1196 {
1197 ps_op->s_ive_op.u4_error_code |= 1
1198 << IVE_UNSUPPORTEDPARAM;
1199 ps_op->s_ive_op.u4_error_code |=
1200 IH264E_FRAME_RATE_NOT_SUPPORTED;
1201 return (IV_FAIL);
1202 }
1203
1204 if ((ps_ip->s_ive_ip.u4_src_frame_rate == 0)
1205 || (ps_ip->s_ive_ip.u4_tgt_frame_rate == 0))
1206 {
1207 ps_op->s_ive_op.u4_error_code |= 1
1208 << IVE_UNSUPPORTEDPARAM;
1209 ps_op->s_ive_op.u4_error_code |=
1210 IH264E_FRAME_RATE_NOT_SUPPORTED;
1211 return (IV_FAIL);
1212 }
1213
1214 if (ps_ip->s_ive_ip.u4_tgt_frame_rate
1215 > ps_ip->s_ive_ip.u4_src_frame_rate)
1216 {
1217 ps_op->s_ive_op.u4_error_code |= 1
1218 << IVE_UNSUPPORTEDPARAM;
1219 ps_op->s_ive_op.u4_error_code |=
1220 IH264E_TGT_FRAME_RATE_EXCEEDS_SRC_FRAME_RATE;
1221 return (IV_FAIL);
1222 }
1223
1224 break;
1225 }
1226
1227 case IVE_CMD_CTL_SET_BITRATE:
1228 {
1229 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
1230 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op;
1231
1232 if (ps_ip->s_ive_ip.u4_size
1233 != sizeof(ih264e_ctl_set_bitrate_ip_t))
1234 {
1235 ps_op->s_ive_op.u4_error_code |= 1
1236 << IVE_UNSUPPORTEDPARAM;
1237 ps_op->s_ive_op.u4_error_code |=
1238 IVE_ERR_IP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1239 return IV_FAIL;
1240 }
1241
1242 if (ps_op->s_ive_op.u4_size
1243 != sizeof(ih264e_ctl_set_bitrate_op_t))
1244 {
1245 ps_op->s_ive_op.u4_error_code |= 1
1246 << IVE_UNSUPPORTEDPARAM;
1247 ps_op->s_ive_op.u4_error_code |=
1248 IVE_ERR_OP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1249 return IV_FAIL;
1250 }
1251
1252 if ((ps_ip->s_ive_ip.u4_target_bitrate > DEFAULT_MAX_BITRATE)
1253 || (ps_ip->s_ive_ip.u4_target_bitrate == 0))
1254 {
1255 ps_op->s_ive_op.u4_error_code |= 1
1256 << IVE_UNSUPPORTEDPARAM;
1257 ps_op->s_ive_op.u4_error_code |=
1258 IH264E_BITRATE_NOT_SUPPORTED;
1259 return (IV_FAIL);
1260 }
1261
1262 break;
1263 }
1264
1265 case IVE_CMD_CTL_SET_FRAMETYPE:
1266 {
1267 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
1268 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op;
1269
1270 if (ps_ip->s_ive_ip.u4_size
1271 != sizeof(ih264e_ctl_set_frame_type_ip_t))
1272 {
1273 ps_op->s_ive_op.u4_error_code |= 1
1274 << IVE_UNSUPPORTEDPARAM;
1275 ps_op->s_ive_op.u4_error_code |=
1276 IVE_ERR_IP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1277 return IV_FAIL;
1278 }
1279
1280 if (ps_op->s_ive_op.u4_size
1281 != sizeof(ih264e_ctl_set_frame_type_op_t))
1282 {
1283 ps_op->s_ive_op.u4_error_code |= 1
1284 << IVE_UNSUPPORTEDPARAM;
1285 ps_op->s_ive_op.u4_error_code |=
1286 IVE_ERR_OP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1287 return IV_FAIL;
1288 }
1289
1290 if ((ps_ip->s_ive_ip.e_frame_type != IV_NA_FRAME)
1291 && (ps_ip->s_ive_ip.e_frame_type != IV_I_FRAME)
1292 && (ps_ip->s_ive_ip.e_frame_type != IV_P_FRAME)
1293 && (ps_ip->s_ive_ip.e_frame_type != IV_IDR_FRAME))
1294 {
1295 ps_op->s_ive_op.u4_error_code |= 1
1296 << IVE_UNSUPPORTEDPARAM;
1297 ps_op->s_ive_op.u4_error_code |=
1298 IH264E_INVALID_FORCE_FRAME_INPUT;
1299 return IV_FAIL;
1300 }
1301 break;
1302 }
1303
1304 case IVE_CMD_CTL_SET_ME_PARAMS:
1305 {
1306 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
1307
1308 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
1309 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op;
1310
1311 if (ps_ip->s_ive_ip.u4_size
1312 != sizeof(ih264e_ctl_set_me_params_ip_t))
1313 {
1314 ps_op->s_ive_op.u4_error_code |= 1
1315 << IVE_UNSUPPORTEDPARAM;
1316 ps_op->s_ive_op.u4_error_code |=
1317 IVE_ERR_IP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1318 return IV_FAIL;
1319 }
1320
1321 if (ps_op->s_ive_op.u4_size
1322 != sizeof(ih264e_ctl_set_me_params_op_t))
1323 {
1324 ps_op->s_ive_op.u4_error_code |= 1
1325 << IVE_UNSUPPORTEDPARAM;
1326 ps_op->s_ive_op.u4_error_code |=
1327 IVE_ERR_OP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1328 return IV_FAIL;
1329 }
1330
1331 if (ps_ip->s_ive_ip.u4_me_speed_preset != DMND_SRCH)
1332 {
1333 ps_op->s_ive_op.u4_error_code |= 1
1334 << IVE_UNSUPPORTEDPARAM;
1335 ps_op->s_ive_op.u4_error_code |=
1336 IH264E_INVALID_ME_SPEED_PRESET;
1337 return IV_FAIL;
1338 }
1339
1340 if ((ps_ip->s_ive_ip.u4_enable_hpel != 0)
1341 && (ps_ip->s_ive_ip.u4_enable_hpel != 1))
1342 {
1343 ps_op->s_ive_op.u4_error_code |= 1
1344 << IVE_UNSUPPORTEDPARAM;
1345 ps_op->s_ive_op.u4_error_code |=
1346 IH264E_INVALID_HALFPEL_OPTION;
1347 return IV_FAIL;
1348 }
1349
1350 if ((ps_ip->s_ive_ip.u4_enable_qpel != 0)
1351 && (ps_ip->s_ive_ip.u4_enable_qpel != 1))
1352 {
1353 ps_op->s_ive_op.u4_error_code |= 1
1354 << IVE_UNSUPPORTEDPARAM;
1355 ps_op->s_ive_op.u4_error_code |=
1356 IH264E_INVALID_QPEL_OPTION;
1357 return IV_FAIL;
1358 }
1359
1360 if ((ps_ip->s_ive_ip.u4_enable_fast_sad != 0)
1361 && (ps_ip->s_ive_ip.u4_enable_fast_sad != 1))
1362 {
1363 ps_op->s_ive_op.u4_error_code |= 1
1364 << IVE_UNSUPPORTEDPARAM;
1365 ps_op->s_ive_op.u4_error_code |=
1366 IH264E_INVALID_FAST_SAD_OPTION;
1367 return IV_FAIL;
1368 }
1369
1370 if (ps_ip->s_ive_ip.u4_enable_alt_ref > 255)
1371 {
1372 ps_op->s_ive_op.u4_error_code |= 1
1373 << IVE_UNSUPPORTEDPARAM;
1374 ps_op->s_ive_op.u4_error_code |=
1375 IH264E_INVALID_ALT_REF_OPTION;
1376 return IV_FAIL;
1377 }
1378
1379 if (ps_ip->s_ive_ip.u4_srch_rng_x
1380 > ps_codec->s_cfg.u4_max_srch_rng_x)
1381 {
1382 ps_op->s_ive_op.u4_error_code |= 1
1383 << IVE_UNSUPPORTEDPARAM;
1384 ps_op->s_ive_op.u4_error_code |=
1385 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
1386 return (IV_FAIL);
1387 }
1388
1389 if (ps_ip->s_ive_ip.u4_srch_rng_y
1390 > ps_codec->s_cfg.u4_max_srch_rng_y)
1391 {
1392 ps_op->s_ive_op.u4_error_code |= 1
1393 << IVE_UNSUPPORTEDPARAM;
1394 ps_op->s_ive_op.u4_error_code |=
1395 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
1396 return (IV_FAIL);
1397 }
1398
1399 break;
1400 }
1401
1402 case IVE_CMD_CTL_SET_IPE_PARAMS:
1403 {
1404 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
1405 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
1406
1407 if (ps_ip->s_ive_ip.u4_size
1408 != sizeof(ih264e_ctl_set_ipe_params_ip_t))
1409 {
1410 ps_op->s_ive_op.u4_error_code |= 1
1411 << IVE_UNSUPPORTEDPARAM;
1412 ps_op->s_ive_op.u4_error_code |=
1413 IVE_ERR_IP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1414 return IV_FAIL;
1415 }
1416
1417 if (ps_op->s_ive_op.u4_size
1418 != sizeof(ih264e_ctl_set_ipe_params_op_t))
1419 {
1420 ps_op->s_ive_op.u4_error_code |= 1
1421 << IVE_UNSUPPORTEDPARAM;
1422 ps_op->s_ive_op.u4_error_code |=
1423 IVE_ERR_OP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1424 return IV_FAIL;
1425 }
1426
1427 if ((ps_ip->s_ive_ip.u4_enable_intra_4x4 != 0)
1428 && (ps_ip->s_ive_ip.u4_enable_intra_4x4 != 1))
1429 {
1430 ps_op->s_ive_op.u4_error_code |= 1
1431 << IVE_UNSUPPORTEDPARAM;
1432 ps_op->s_ive_op.u4_error_code |=
1433 IH264E_INVALID_INTRA4x4_OPTION;
1434 return IV_FAIL;
1435 }
1436
1437 if ((ps_ip->s_ive_ip.u4_constrained_intra_pred != 0)
1438 && (ps_ip->s_ive_ip.u4_constrained_intra_pred != 1))
1439 {
1440 ps_op->s_ive_op.u4_error_code |= 1
1441 << IVE_UNSUPPORTEDPARAM;
1442 ps_op->s_ive_op.u4_error_code |=
1443 IH264E_INVALID_CONSTRAINED_INTRA_PREDICTION_MODE;
1444 return IV_FAIL;
1445 }
1446
1447 if ((ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_CONFIG)
1448 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_SLOWEST)
1449 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_NORMAL)
1450 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FAST)
1451 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_HIGH_SPEED)
1452 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FASTEST))
1453 {
1454 ps_op->s_ive_op.u4_error_code |= 1
1455 << IVE_UNSUPPORTEDPARAM;
1456 ps_op->s_ive_op.u4_error_code |=
1457 IH264E_INVALID_ENC_SPEED_PRESET;
1458 return IV_FAIL;
1459 }
1460
1461 break;
1462 }
1463
1464 case IVE_CMD_CTL_SET_GOP_PARAMS:
1465 {
1466 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
1467 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op;
1468
1469 if (ps_ip->s_ive_ip.u4_size
1470 != sizeof(ih264e_ctl_set_gop_params_ip_t))
1471 {
1472 ps_op->s_ive_op.u4_error_code |= 1
1473 << IVE_UNSUPPORTEDPARAM;
1474 ps_op->s_ive_op.u4_error_code |=
1475 IVE_ERR_IP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1476 return IV_FAIL;
1477 }
1478
1479 if (ps_op->s_ive_op.u4_size
1480 != sizeof(ih264e_ctl_set_gop_params_op_t))
1481 {
1482 ps_op->s_ive_op.u4_error_code |= 1
1483 << IVE_UNSUPPORTEDPARAM;
1484 ps_op->s_ive_op.u4_error_code |=
1485 IVE_ERR_OP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1486 return IV_FAIL;
1487 }
1488
1489 if ((ps_ip->s_ive_ip.u4_i_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE)
1490 || (ps_ip->s_ive_ip.u4_i_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1491 {
1492 ps_op->s_ive_op.u4_error_code |= 1
1493 << IVE_UNSUPPORTEDPARAM;
1494 ps_op->s_ive_op.u4_error_code |=
1495 IH264E_INVALID_INTRA_FRAME_INTERVAL;
1496 return IV_FAIL;
1497 }
1498
1499 if ((ps_ip->s_ive_ip.u4_idr_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE)
1500 || (ps_ip->s_ive_ip.u4_idr_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1501 {
1502 ps_op->s_ive_op.u4_error_code |= 1
1503 << IVE_UNSUPPORTEDPARAM;
1504 ps_op->s_ive_op.u4_error_code |=
1505 IH264E_INVALID_IDR_FRAME_INTERVAL;
1506 return IV_FAIL;
1507 }
1508
1509 if((ps_ip->s_ive_ip.u4_idr_frm_interval > ps_ip->s_ive_ip.u4_i_frm_interval) &&
1510 (ps_ip->s_ive_ip.u4_idr_frm_interval % ps_ip->s_ive_ip.u4_i_frm_interval != 0))
1511 {
1512 ps_op->s_ive_op.u4_error_code |= 1
1513 << IVE_UNSUPPORTEDPARAM;
1514 ps_op->s_ive_op.u4_error_code |=
1515 IH264E_INVALID_INTRA_FRAME_INTERVAL;
1516 return IV_FAIL;
1517 }
1518
1519 break;
1520 }
1521
1522 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS:
1523 {
1524 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
1525 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
1526
1527 if (ps_ip->s_ive_ip.u4_size
1528 != sizeof(ih264e_ctl_set_deblock_params_ip_t))
1529 {
1530 ps_op->s_ive_op.u4_error_code |= 1
1531 << IVE_UNSUPPORTEDPARAM;
1532 ps_op->s_ive_op.u4_error_code |=
1533 IVE_ERR_IP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1534 return IV_FAIL;
1535 }
1536
1537 if (ps_op->s_ive_op.u4_size
1538 != sizeof(ih264e_ctl_set_deblock_params_op_t))
1539 {
1540 ps_op->s_ive_op.u4_error_code |= 1
1541 << IVE_UNSUPPORTEDPARAM;
1542 ps_op->s_ive_op.u4_error_code |=
1543 IVE_ERR_OP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1544 return IV_FAIL;
1545 }
1546
1547 if ((ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_0)
1548 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_2)
1549 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_3)
1550 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_4))
1551 {
1552 ps_op->s_ive_op.u4_error_code |= 1
1553 << IVE_UNSUPPORTEDPARAM;
1554 ps_op->s_ive_op.u4_error_code |=
1555 IH264E_INVALID_DEBLOCKING_TYPE_INPUT;
1556 return IV_FAIL;
1557 }
1558
1559 break;
1560 }
1561
1562 case IVE_CMD_CTL_SET_QP:
1563 {
1564 ih264e_ctl_set_qp_ip_t *ps_ip = pv_api_ip;
1565 ih264e_ctl_set_qp_op_t *ps_op = pv_api_op;
1566
1567 if (ps_ip->s_ive_ip.u4_size
1568 != sizeof(ih264e_ctl_set_qp_ip_t))
1569 {
1570 ps_op->s_ive_op.u4_error_code |= 1
1571 << IVE_UNSUPPORTEDPARAM;
1572 ps_op->s_ive_op.u4_error_code |=
1573 IVE_ERR_IP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1574 return IV_FAIL;
1575 }
1576
1577 if (ps_op->s_ive_op.u4_size
1578 != sizeof(ih264e_ctl_set_qp_op_t))
1579 {
1580 ps_op->s_ive_op.u4_error_code |= 1
1581 << IVE_UNSUPPORTEDPARAM;
1582 ps_op->s_ive_op.u4_error_code |=
1583 IVE_ERR_OP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1584 return IV_FAIL;
1585 }
1586
1587 if ((ps_ip->s_ive_ip.u4_i_qp_max > MAX_H264_QP)
1588 || (ps_ip->s_ive_ip.u4_p_qp_max > MAX_H264_QP)
1589 || (ps_ip->s_ive_ip.u4_b_qp_max > MAX_H264_QP))
1590 {
1591 ps_op->s_ive_op.u4_error_code |= 1
1592 << IVE_UNSUPPORTEDPARAM;
1593 ps_op->s_ive_op.u4_error_code |=
1594 IH264E_INVALID_MAX_FRAME_QP;
1595 return IV_FAIL;
1596 }
1597
1598 /* We donot support QP < 4 */
1599 if ((ps_ip->s_ive_ip.u4_i_qp_min < 4)
1600 || (ps_ip->s_ive_ip.u4_p_qp_min < 4)
1601 || (ps_ip->s_ive_ip.u4_b_qp_min < 4)
1602 || (ps_ip->s_ive_ip.u4_i_qp_min > ps_ip->s_ive_ip.u4_i_qp_max)
1603 || (ps_ip->s_ive_ip.u4_p_qp_min > ps_ip->s_ive_ip.u4_p_qp_max)
1604 || (ps_ip->s_ive_ip.u4_b_qp_min > ps_ip->s_ive_ip.u4_b_qp_max))
1605 {
1606 ps_op->s_ive_op.u4_error_code |= 1
1607 << IVE_UNSUPPORTEDPARAM;
1608 ps_op->s_ive_op.u4_error_code |=
1609 IH264E_INVALID_MIN_FRAME_QP;
1610 return IV_FAIL;
1611 }
1612
1613 if ((ps_ip->s_ive_ip.u4_i_qp > ps_ip->s_ive_ip.u4_i_qp_max)
1614 || (ps_ip->s_ive_ip.u4_p_qp > ps_ip->s_ive_ip.u4_p_qp_max)
1615 || (ps_ip->s_ive_ip.u4_b_qp > ps_ip->s_ive_ip.u4_b_qp_max)
1616 || (ps_ip->s_ive_ip.u4_i_qp < ps_ip->s_ive_ip.u4_i_qp_min)
1617 || (ps_ip->s_ive_ip.u4_p_qp < ps_ip->s_ive_ip.u4_p_qp_min)
1618 || (ps_ip->s_ive_ip.u4_b_qp < ps_ip->s_ive_ip.u4_b_qp_min))
1619 {
1620 ps_op->s_ive_op.u4_error_code |= 1
1621 << IVE_UNSUPPORTEDPARAM;
1622 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1623 return IV_FAIL;
1624 }
1625
1626 break;
1627 }
1628
1629 case IVE_CMD_CTL_SET_VUI_PARAMS:
1630 {
1631 ih264e_vui_ip_t *ps_ip = pv_api_ip;
1632 ih264e_vui_op_t *ps_op = pv_api_op;
1633
1634 if(ps_ip->u4_size != sizeof(ih264e_vui_ip_t))
1635 {
1636 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1637 ps_op->u4_error_code |=
1638 IVE_ERR_IP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1639 return IV_FAIL;
1640 }
1641
1642 if(ps_op->u4_size != sizeof(ih264e_vui_op_t))
1643 {
1644 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1645 ps_op->u4_error_code |=
1646 IVE_ERR_OP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1647 return IV_FAIL;
1648 }
1649
1650 break;
1651 }
1652
1653 case IVE_CMD_CTL_SET_SEI_MDCV_PARAMS:
1654 {
1655 ih264e_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip;
1656 ih264e_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op;
1657
1658 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_mdcv_params_ip_t))
1659 {
1660 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1661 ps_op->u4_error_code |=
1662 IVE_ERR_IP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT;
1663 return IV_FAIL;
1664 }
1665
1666 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_mdcv_params_op_t))
1667 {
1668 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1669 ps_op->u4_error_code |=
1670 IVE_ERR_OP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT;
1671 return IV_FAIL;
1672 }
1673
1674 if((ps_ip->u1_sei_mdcv_params_present_flag != 0)
1675 && (ps_ip->u1_sei_mdcv_params_present_flag) != 1)
1676 {
1677 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1678 ps_op->u4_error_code |=
1679 IH264E_INVALID_SEI_MDCV_PARAMS;
1680 return IV_FAIL;
1681 }
1682
1683 if(1 == ps_ip->u1_sei_mdcv_params_present_flag)
1684 {
1685 /* Check values for u2_display_primaries_x and u2_display_primaries_y */
1686 for(i = 0; i < 3; i++)
1687 {
1688 if((ps_ip->au2_display_primaries_x[i] >
1689 DISPLAY_PRIMARIES_X_UPPER_LIMIT) ||
1690 (ps_ip->au2_display_primaries_x[i] <
1691 DISPLAY_PRIMARIES_X_LOWER_LIMIT) ||
1692 ((ps_ip->au2_display_primaries_x[i] %
1693 DISPLAY_PRIMARIES_X_DIVISION_FACTOR) != 0))
1694 {
1695 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1696 ps_op->u4_error_code |=
1697 IH264E_INVALID_SEI_MDCV_PARAMS;
1698 return IV_FAIL;
1699 }
1700
1701 if((ps_ip->au2_display_primaries_y[i] >
1702 DISPLAY_PRIMARIES_Y_UPPER_LIMIT) ||
1703 (ps_ip->au2_display_primaries_y[i] <
1704 DISPLAY_PRIMARIES_Y_LOWER_LIMIT) ||
1705 ((ps_ip->au2_display_primaries_y[i] %
1706 DISPLAY_PRIMARIES_Y_DIVISION_FACTOR) != 0))
1707 {
1708 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1709 ps_op->u4_error_code |=
1710 IH264E_INVALID_SEI_MDCV_PARAMS;
1711 return IV_FAIL;
1712 }
1713 }
1714
1715 if((ps_ip->u2_white_point_x > WHITE_POINT_X_UPPER_LIMIT) ||
1716 (ps_ip->u2_white_point_x < WHITE_POINT_X_LOWER_LIMIT) ||
1717 ((ps_ip->u2_white_point_x % WHITE_POINT_X_DIVISION_FACTOR) != 0))
1718 {
1719 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1720 ps_op->u4_error_code |=
1721 IH264E_INVALID_SEI_MDCV_PARAMS;
1722 return IV_FAIL;
1723 }
1724
1725 if((ps_ip->u2_white_point_y > WHITE_POINT_Y_UPPER_LIMIT) ||
1726 (ps_ip->u2_white_point_y < WHITE_POINT_Y_LOWER_LIMIT) ||
1727 ((ps_ip->u2_white_point_y % WHITE_POINT_Y_DIVISION_FACTOR) != 0))
1728 {
1729 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1730 ps_op->u4_error_code |=
1731 IH264E_INVALID_SEI_MDCV_PARAMS;
1732 return IV_FAIL;
1733 }
1734
1735 if((ps_ip->u4_max_display_mastering_luminance >
1736 MAX_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT) ||
1737 (ps_ip->u4_max_display_mastering_luminance <
1738 MAX_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT) ||
1739 ((ps_ip->u4_max_display_mastering_luminance %
1740 MAX_DISPLAY_MASTERING_LUMINANCE_DIVISION_FACTOR) != 0))
1741 {
1742 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1743 ps_op->u4_error_code |=
1744 IH264E_INVALID_SEI_MDCV_PARAMS;
1745 return IV_FAIL;
1746 }
1747
1748 if((ps_ip->u4_min_display_mastering_luminance >
1749 MIN_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT ) ||
1750 (ps_ip->u4_min_display_mastering_luminance <
1751 MIN_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT))
1752 {
1753 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1754 ps_op->u4_error_code |=
1755 IH264E_INVALID_SEI_MDCV_PARAMS;
1756 return IV_FAIL;
1757 }
1758
1759 if(ps_ip->u4_max_display_mastering_luminance <=
1760 ps_ip->u4_min_display_mastering_luminance)
1761 {
1762 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1763 ps_op->u4_error_code |=
1764 IH264E_INVALID_SEI_MDCV_PARAMS;
1765 return IV_FAIL;
1766 }
1767 }
1768 break;
1769 }
1770
1771 case IVE_CMD_CTL_SET_SEI_CLL_PARAMS:
1772 {
1773 ih264e_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip;
1774 ih264e_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op;
1775
1776 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_cll_params_ip_t))
1777 {
1778 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1779 ps_op->u4_error_code |=
1780 IVE_ERR_IP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT;
1781 return IV_FAIL;
1782 }
1783
1784 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_cll_params_op_t))
1785 {
1786 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1787 ps_op->u4_error_code |=
1788 IVE_ERR_OP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT;
1789 return IV_FAIL;
1790 }
1791
1792 if((ps_ip->u1_sei_cll_params_present_flag != 0)
1793 && (ps_ip->u1_sei_cll_params_present_flag != 1))
1794 {
1795 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1796 ps_op->u4_error_code |=
1797 IH264E_INVALID_SEI_CLL_PARAMS;
1798 return IV_FAIL;
1799 }
1800 break;
1801 }
1802
1803 case IVE_CMD_CTL_SET_SEI_AVE_PARAMS:
1804 {
1805 ih264e_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip;
1806 ih264e_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op;
1807
1808 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_ave_params_ip_t))
1809 {
1810 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1811 ps_op->u4_error_code |=
1812 IVE_ERR_IP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT;
1813 return IV_FAIL;
1814 }
1815
1816 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_ave_params_op_t))
1817 {
1818 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1819 ps_op->u4_error_code |=
1820 IVE_ERR_OP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT;
1821 return IV_FAIL;
1822 }
1823
1824 if((ps_ip->u1_sei_ave_params_present_flag != 0)
1825 && (ps_ip->u1_sei_ave_params_present_flag != 1))
1826 {
1827 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1828 ps_op->u4_error_code |=
1829 IH264E_INVALID_SEI_AVE_PARAMS;
1830 return IV_FAIL;
1831 }
1832
1833 if(1 == ps_ip->u1_sei_ave_params_present_flag)
1834 {
1835 if((0 == ps_ip->u4_ambient_illuminance))
1836 {
1837 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1838 ps_op->u4_error_code |=
1839 IH264E_INVALID_SEI_AVE_PARAMS;
1840 return IV_FAIL;
1841 }
1842
1843 if(ps_ip->u2_ambient_light_x > AMBIENT_LIGHT_X_UPPER_LIMIT)
1844 {
1845 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1846 ps_op->u4_error_code |=
1847 IH264E_INVALID_SEI_AVE_PARAMS;
1848 return IV_FAIL;
1849 }
1850
1851 if(ps_ip->u2_ambient_light_y > AMBIENT_LIGHT_Y_UPPER_LIMIT)
1852 {
1853 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1854 ps_op->u4_error_code |=
1855 IH264E_INVALID_SEI_AVE_PARAMS;
1856 return IV_FAIL;
1857 }
1858 }
1859 break;
1860 }
1861
1862 case IVE_CMD_CTL_SET_SEI_CCV_PARAMS:
1863 {
1864 ih264e_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip;
1865 ih264e_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op;
1866
1867 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_ccv_params_ip_t))
1868 {
1869 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1870 ps_op->u4_error_code |=
1871 IVE_ERR_IP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT;
1872 return IV_FAIL;
1873 }
1874
1875 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_ccv_params_op_t))
1876 {
1877 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1878 ps_op->u4_error_code |=
1879 IVE_ERR_OP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT;
1880 return IV_FAIL;
1881 }
1882
1883 if((ps_ip->u1_sei_ccv_params_present_flag != 0)
1884 && (ps_ip->u1_sei_ccv_params_present_flag != 1))
1885 {
1886 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1887 ps_op->u4_error_code |=
1888 IH264E_INVALID_SEI_CCV_PARAMS;
1889 return IV_FAIL;
1890 }
1891
1892
1893 if(1 == ps_ip->u1_sei_ccv_params_present_flag)
1894 {
1895 if((ps_ip->u1_ccv_cancel_flag != 0)
1896 && (ps_ip->u1_ccv_cancel_flag != 1))
1897 {
1898 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1899 ps_op->u4_error_code |=
1900 IH264E_INVALID_SEI_CCV_PARAMS;
1901 return IV_FAIL;
1902 }
1903
1904 if(0 == ps_ip->u1_ccv_cancel_flag)
1905 {
1906 if((ps_ip->u1_ccv_persistence_flag != 0)
1907 && (ps_ip->u1_ccv_persistence_flag != 1))
1908 {
1909 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1910 ps_op->u4_error_code |=
1911 IH264E_INVALID_SEI_CCV_PARAMS;
1912 return IV_FAIL;
1913 }
1914 if((ps_ip->u1_ccv_primaries_present_flag != 0)
1915 && (ps_ip->u1_ccv_primaries_present_flag != 1))
1916 {
1917 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1918 ps_op->u4_error_code |=
1919 IH264E_INVALID_SEI_CCV_PARAMS;
1920 return IV_FAIL;
1921 }
1922 if((ps_ip->u1_ccv_min_luminance_value_present_flag != 0)
1923 && (ps_ip->u1_ccv_min_luminance_value_present_flag != 1))
1924 {
1925 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1926 ps_op->u4_error_code |=
1927 IH264E_INVALID_SEI_CCV_PARAMS;
1928 return IV_FAIL;
1929 }
1930 if((ps_ip->u1_ccv_max_luminance_value_present_flag != 0)
1931 && (ps_ip->u1_ccv_max_luminance_value_present_flag != 1))
1932 {
1933 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1934 ps_op->u4_error_code |=
1935 IH264E_INVALID_SEI_CCV_PARAMS;
1936 return IV_FAIL;
1937 }
1938 if((ps_ip->u1_ccv_avg_luminance_value_present_flag != 0)
1939 && (ps_ip->u1_ccv_avg_luminance_value_present_flag != 1))
1940 {
1941 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1942 ps_op->u4_error_code |=
1943 IH264E_INVALID_SEI_CCV_PARAMS;
1944 return IV_FAIL;
1945 }
1946 if((ps_ip->u1_ccv_primaries_present_flag == 0)
1947 && (ps_ip->u1_ccv_min_luminance_value_present_flag == 0)
1948 && (ps_ip->u1_ccv_max_luminance_value_present_flag == 0)
1949 && (ps_ip->u1_ccv_avg_luminance_value_present_flag == 0))
1950 {
1951 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1952 ps_op->u4_error_code |=
1953 IH264E_INVALID_SEI_CCV_PARAMS;
1954 return IV_FAIL;
1955 }
1956
1957 if((ps_ip->u1_ccv_reserved_zero_2bits != 0))
1958 {
1959 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1960 ps_op->u4_error_code |=
1961 IH264E_INVALID_SEI_CCV_PARAMS;
1962 return IV_FAIL;
1963 }
1964
1965 if(1 == ps_ip->u1_ccv_primaries_present_flag)
1966 {
1967 for(i = 0; i < 3; i++)
1968 {
1969 if((ps_ip->ai4_ccv_primaries_x[i] >
1970 CCV_PRIMARIES_X_UPPER_LIMIT) ||
1971 (ps_ip->ai4_ccv_primaries_x[i] <
1972 CCV_PRIMARIES_X_LOWER_LIMIT))
1973 {
1974 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1975 ps_op->u4_error_code |=
1976 IH264E_INVALID_SEI_CCV_PARAMS;
1977 return IV_FAIL;
1978 }
1979
1980 if((ps_ip->ai4_ccv_primaries_y[i] >
1981 CCV_PRIMARIES_Y_UPPER_LIMIT) ||
1982 (ps_ip->ai4_ccv_primaries_y[i] <
1983 CCV_PRIMARIES_Y_LOWER_LIMIT))
1984 {
1985 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1986 ps_op->u4_error_code |=
1987 IH264E_INVALID_SEI_CCV_PARAMS;
1988 return IV_FAIL;
1989 }
1990 }
1991 }
1992
1993 if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) &&
1994 (1 == ps_ip->u1_ccv_avg_luminance_value_present_flag))
1995 {
1996 if((ps_ip->u4_ccv_avg_luminance_value <
1997 ps_ip->u4_ccv_min_luminance_value))
1998 {
1999 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2000 ps_op->u4_error_code |=
2001 IH264E_INVALID_SEI_CCV_PARAMS;
2002 return IV_FAIL;
2003 }
2004 }
2005
2006 if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) &&
2007 (1 == ps_ip->u1_ccv_max_luminance_value_present_flag))
2008 {
2009 if((ps_ip->u4_ccv_max_luminance_value <
2010 ps_ip->u4_ccv_min_luminance_value))
2011 {
2012 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2013 ps_op->u4_error_code |=
2014 IH264E_INVALID_SEI_CCV_PARAMS;
2015 return IV_FAIL;
2016 }
2017 }
2018 if((1 == ps_ip->u1_ccv_avg_luminance_value_present_flag) &&
2019 (1 == ps_ip->u1_ccv_max_luminance_value_present_flag))
2020 {
2021 if((ps_ip->u4_ccv_max_luminance_value <
2022 ps_ip->u4_ccv_avg_luminance_value))
2023 {
2024 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2025 ps_op->u4_error_code |=
2026 IH264E_INVALID_SEI_CCV_PARAMS;
2027 return IV_FAIL;
2028 }
2029 }
2030 }
2031 }
2032 break;
2033 }
2034
2035 case IVE_CMD_CTL_SET_SEI_SII_PARAMS:
2036 {
2037 ih264e_ctl_set_sei_sii_params_ip_t *ps_ip = pv_api_ip;
2038 ih264e_ctl_set_sei_sii_params_op_t *ps_op = pv_api_op;
2039
2040 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_sii_params_ip_t))
2041 {
2042 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2043 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_SII_STRUCT_SIZE_INCORRECT;
2044 return IV_FAIL;
2045 }
2046
2047 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_sii_params_op_t))
2048 {
2049 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2050 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_SII_STRUCT_SIZE_INCORRECT;
2051 return IV_FAIL;
2052 }
2053
2054 /* The below error check is based on H264 spec docs SII syntax */
2055 if(0 != ps_ip->u4_sii_sub_layer_idx)
2056 {
2057 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2058 ps_op->u4_error_code |= IH264E_INVALID_SEI_SII_PARAMS;
2059 return IV_FAIL;
2060 }
2061
2062 if(ps_ip->u1_sii_max_sub_layers_minus1 > 7)
2063 {
2064 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2065 ps_op->u4_error_code |= IH264E_INVALID_SEI_SII_PARAMS;
2066 return IV_FAIL;
2067 }
2068
2069 if((ps_ip->u4_sii_sub_layer_idx > 0) &&
2070 (ps_ip->u1_fixed_shutter_interval_within_cvs_flag == 1))
2071 {
2072 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2073 ps_op->u4_error_code |= IH264E_SEI_SII_FAILED_TO_MATCH_SPEC_COND;
2074 return IV_FAIL;
2075 }
2076
2077 if((ps_ip->u4_sii_sub_layer_idx > ps_ip->u1_sii_max_sub_layers_minus1) &&
2078 (ps_ip->u1_fixed_shutter_interval_within_cvs_flag == 0))
2079 {
2080 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2081 ps_op->u4_error_code |= IH264E_SEI_SII_FAILED_TO_MATCH_SPEC_COND;
2082 return IV_FAIL;
2083 }
2084
2085 break;
2086 }
2087
2088 case IVE_CMD_CTL_SET_ENC_MODE:
2089 {
2090 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
2091 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
2092
2093 if (ps_ip->s_ive_ip.u4_size
2094 != sizeof(ih264e_ctl_set_enc_mode_ip_t))
2095 {
2096 ps_op->s_ive_op.u4_error_code |= 1
2097 << IVE_UNSUPPORTEDPARAM;
2098 ps_op->s_ive_op.u4_error_code |=
2099 IVE_ERR_IP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
2100 return IV_FAIL;
2101 }
2102
2103 if (ps_op->s_ive_op.u4_size
2104 != sizeof(ih264e_ctl_set_enc_mode_op_t))
2105 {
2106 ps_op->s_ive_op.u4_error_code |= 1
2107 << IVE_UNSUPPORTEDPARAM;
2108 ps_op->s_ive_op.u4_error_code |=
2109 IVE_ERR_OP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
2110 return IV_FAIL;
2111 }
2112
2113 if ((ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_HEADER)
2114 && (ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_PICTURE))
2115 {
2116 ps_op->s_ive_op.u4_error_code |= 1
2117 << IVE_UNSUPPORTEDPARAM;
2118 ps_op->s_ive_op.u4_error_code |=
2119 IH264E_INVALID_ENC_OPERATION_MODE;
2120 return IV_FAIL;
2121 }
2122
2123 break;
2124 }
2125
2126 case IVE_CMD_CTL_SET_VBV_PARAMS:
2127 {
2128 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
2129 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
2130
2131 if (ps_ip->s_ive_ip.u4_size
2132 != sizeof(ih264e_ctl_set_vbv_params_ip_t))
2133 {
2134 ps_op->s_ive_op.u4_error_code |= 1
2135 << IVE_UNSUPPORTEDPARAM;
2136 ps_op->s_ive_op.u4_error_code |=
2137 IVE_ERR_IP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
2138 return IV_FAIL;
2139 }
2140
2141 if (ps_op->s_ive_op.u4_size
2142 != sizeof(ih264e_ctl_set_vbv_params_op_t))
2143 {
2144 ps_op->s_ive_op.u4_error_code |= 1
2145 << IVE_UNSUPPORTEDPARAM;
2146 ps_op->s_ive_op.u4_error_code |=
2147 IVE_ERR_OP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
2148 return IV_FAIL;
2149 }
2150
2151 if ((ps_ip->s_ive_ip.u4_vbv_buffer_delay < DEFAULT_MIN_BUFFER_DELAY)
2152 || (ps_ip->s_ive_ip.u4_vbv_buffer_delay > DEFAULT_MAX_BUFFER_DELAY))
2153 {
2154 ps_op->s_ive_op.u4_error_code |= 1
2155 << IVE_UNSUPPORTEDPARAM;
2156 ps_op->s_ive_op.u4_error_code |=
2157 IH264E_INVALID_BUFFER_DELAY;
2158 return IV_FAIL;
2159 }
2160
2161 break;
2162 }
2163
2164 case IVE_CMD_CTL_SET_AIR_PARAMS:
2165 {
2166 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
2167 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op;
2168
2169 if (ps_ip->s_ive_ip.u4_size
2170 != sizeof(ih264e_ctl_set_air_params_ip_t))
2171 {
2172 ps_op->s_ive_op.u4_error_code |= 1
2173 << IVE_UNSUPPORTEDPARAM;
2174 ps_op->s_ive_op.u4_error_code |=
2175 IVE_ERR_IP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
2176 return IV_FAIL;
2177 }
2178
2179 if (ps_op->s_ive_op.u4_size
2180 != sizeof(ih264e_ctl_set_air_params_op_t))
2181 {
2182 ps_op->s_ive_op.u4_error_code |= 1
2183 << IVE_UNSUPPORTEDPARAM;
2184 ps_op->s_ive_op.u4_error_code |=
2185 IVE_ERR_OP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
2186 return IV_FAIL;
2187 }
2188
2189 if ((ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE)
2190 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_CYCLIC)
2191 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_RANDOM))
2192 {
2193 ps_op->s_ive_op.u4_error_code |= 1
2194 << IVE_UNSUPPORTEDPARAM;
2195 ps_op->s_ive_op.u4_error_code |=
2196 IH264E_INVALID_AIR_MODE;
2197 return IV_FAIL;
2198 }
2199
2200 if (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE &&
2201 ps_ip->s_ive_ip.u4_air_refresh_period == 0)
2202 {
2203 ps_op->s_ive_op.u4_error_code |= 1
2204 << IVE_UNSUPPORTEDPARAM;
2205 ps_op->s_ive_op.u4_error_code |=
2206 IH264E_INVALID_AIR_REFRESH_PERIOD;
2207 return IV_FAIL;
2208 }
2209
2210 break;
2211 }
2212
2213 case IVE_CMD_CTL_SET_PROFILE_PARAMS:
2214 {
2215 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
2216 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op;
2217
2218 if (ps_ip->s_ive_ip.u4_size
2219 != sizeof(ih264e_ctl_set_profile_params_ip_t))
2220 {
2221 ps_op->s_ive_op.u4_error_code |= 1
2222 << IVE_UNSUPPORTEDPARAM;
2223 ps_op->s_ive_op.u4_error_code |=
2224 IVE_ERR_IP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
2225 return IV_FAIL;
2226 }
2227
2228 if (ps_op->s_ive_op.u4_size
2229 != sizeof(ih264e_ctl_set_profile_params_op_t))
2230 {
2231 ps_op->s_ive_op.u4_error_code |= 1
2232 << IVE_UNSUPPORTEDPARAM;
2233 ps_op->s_ive_op.u4_error_code |=
2234 IVE_ERR_OP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
2235 return IV_FAIL;
2236 }
2237
2238 if (ps_ip->s_ive_ip.e_profile != IV_PROFILE_BASE &&
2239 ps_ip->s_ive_ip.e_profile != IV_PROFILE_MAIN)
2240 {
2241 ps_op->s_ive_op.u4_error_code |= 1
2242 << IVE_UNSUPPORTEDPARAM;
2243 ps_op->s_ive_op.u4_error_code |=
2244 IH264E_PROFILE_NOT_SUPPORTED;
2245 return IV_FAIL;
2246 }
2247
2248 if (ps_ip->s_ive_ip.u4_entropy_coding_mode > 1)
2249 {
2250 ps_op->s_ive_op.u4_error_code |= 1
2251 << IVE_UNSUPPORTEDPARAM;
2252 ps_op->s_ive_op.u4_error_code |=
2253 IH264E_INVALID_ENTROPY_CODING_MODE;
2254 return IV_FAIL;
2255 }
2256
2257 break;
2258 }
2259
2260 default:
2261 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
2262 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_SUB_CMD;
2263 return IV_FAIL;
2264 }
2265
2266 break;
2267 }
2268
2269 default:
2270 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
2271 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
2272 return IV_FAIL;
2273 }
2274
2275 return IV_SUCCESS;
2276 }
2277
2278 /**
2279 *******************************************************************************
2280 *
2281 * @brief update encoder configuration parameters
2282 *
2283 * @par Description:
2284 * updates encoder configuration parameters from the given config set.
2285 * Initialize/reinitialize codec parameters according to new configurations.
2286 *
2287 * @param[in] ps_codec
2288 * Pointer to codec context
2289 *
2290 * @param[in] ps_cfg
2291 * Pointer to config param set
2292 *
2293 * @remarks none
2294 *
2295 *******************************************************************************
2296 */
ih264e_codec_update_config(codec_t * ps_codec,cfg_params_t * ps_cfg)2297 IH264E_ERROR_T ih264e_codec_update_config(codec_t *ps_codec,
2298 cfg_params_t *ps_cfg)
2299 {
2300 /* config params */
2301 cfg_params_t *ps_curr_cfg = &ps_codec->s_cfg;
2302
2303 /* error status */
2304 IH264E_ERROR_T err = IH264E_SUCCESS;
2305
2306 /* temp var */
2307 UWORD32 u4_init_rc = 0;
2308
2309 /***********************/
2310 /* UPDATE CODEC CONFIG */
2311 /***********************/
2312 if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DIMENSIONS)
2313 {
2314 UWORD32 wd_aln = ALIGN16(ps_cfg->u4_wd);
2315 UWORD32 ht_aln = ALIGN16(ps_cfg->u4_ht);
2316
2317 if (ps_curr_cfg->u4_wd != wd_aln || ps_curr_cfg->u4_ht != ht_aln
2318 || ps_curr_cfg->u4_disp_wd != ps_cfg->u4_disp_wd
2319 || ps_curr_cfg->u4_disp_ht != ps_cfg->u4_disp_ht)
2320 {
2321 ps_curr_cfg->u4_wd = wd_aln;
2322 ps_curr_cfg->u4_ht = ht_aln;
2323
2324 ps_curr_cfg->u4_disp_wd = ps_cfg->u4_disp_wd;
2325 ps_curr_cfg->u4_disp_ht = ps_cfg->u4_disp_ht;
2326
2327 ps_curr_cfg->i4_wd_mbs = ps_curr_cfg->u4_wd >> 4;
2328 ps_curr_cfg->i4_ht_mbs = ps_curr_cfg->u4_ht >> 4;
2329
2330 ps_codec->i4_rec_strd = ALIGN16(ps_cfg->u4_wd) + PAD_WD;
2331
2332 /* If number of MBs in a frame changes the air map also changes.
2333 * Hence recompute air map also reset air pic cnt */
2334 if (ps_codec->s_cfg.e_air_mode != IVE_AIR_MODE_NONE)
2335 {
2336 /* re-init the air map */
2337 ih264e_init_air_map(ps_codec);
2338
2339 /* reset air counter */
2340 ps_codec->i4_air_pic_cnt = -1;
2341 }
2342
2343 /* initialize mv bank buffer manager */
2344 err = ih264e_mv_buf_mgr_add_bufs(ps_codec);
2345 if (err != IH264E_SUCCESS)
2346 return err;
2347
2348 /* initialize ref bank buffer manager */
2349 err = ih264e_pic_buf_mgr_add_bufs(ps_codec);
2350 if (err != IH264E_SUCCESS)
2351 return err;
2352
2353 /* since dimension changed, start new sequence by forcing IDR */
2354 ps_codec->force_curr_frame_type = IV_IDR_FRAME;
2355
2356 /* in case dimension changes, we need to reinitialize RC as the
2357 * old model shall not fit further */
2358 u4_init_rc = 1;
2359
2360 /* when the dimension changes, the header needs to be regenerated */
2361 ps_codec->i4_gen_header = 1;
2362 }
2363 }
2364 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMERATE)
2365 {
2366 /* temp var */
2367 UWORD32 u4_src_ticks, u4_tgt_ticks;
2368
2369 u4_src_ticks = ih264e_frame_time_get_src_ticks(
2370 ps_codec->s_rate_control.pps_frame_time);
2371
2372 u4_tgt_ticks = ih264e_frame_time_get_tgt_ticks(
2373 ps_codec->s_rate_control.pps_frame_time);
2374
2375 /* Change frame rate */
2376 if (ps_codec->s_cfg.u4_src_frame_rate
2377 != ps_cfg->u4_src_frame_rate * 1000)
2378 {
2379 ps_codec->s_cfg.u4_src_frame_rate = ps_cfg->u4_src_frame_rate
2380 * 1000;
2381
2382 ih264e_frame_time_update_src_frame_rate(
2383 ps_codec->s_rate_control.pps_frame_time,
2384 ps_codec->s_cfg.u4_src_frame_rate);
2385
2386 ih264_time_stamp_update_frame_rate(
2387 ps_codec->s_rate_control.pps_time_stamp,
2388 ps_codec->s_cfg.u4_src_frame_rate);
2389
2390 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api,
2391 ps_codec->s_cfg.u4_src_frame_rate,
2392 u4_src_ticks, u4_tgt_ticks);
2393 }
2394
2395 if (ps_codec->s_cfg.u4_tgt_frame_rate
2396 != ps_cfg->u4_tgt_frame_rate * 1000)
2397 {
2398 ps_codec->s_cfg.u4_tgt_frame_rate = ps_cfg->u4_tgt_frame_rate
2399 * 1000;
2400
2401 ih264e_frame_time_update_tgt_frame_rate(
2402 ps_codec->s_rate_control.pps_frame_time,
2403 ps_codec->s_cfg.u4_tgt_frame_rate);
2404
2405 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api,
2406 ps_codec->s_cfg.u4_src_frame_rate,
2407 u4_src_ticks, u4_tgt_ticks);
2408
2409 irc_change_frm_rate_for_bit_alloc(
2410 ps_codec->s_rate_control.pps_rate_control_api,
2411 ps_codec->s_cfg.u4_tgt_frame_rate);
2412 }
2413
2414 }
2415 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_BITRATE)
2416 {
2417 if (ps_curr_cfg->u4_target_bitrate != ps_cfg->u4_target_bitrate)
2418 {
2419 if (IVE_RC_NONE != ps_curr_cfg->e_rc_mode)
2420 irc_change_avg_bit_rate(
2421 ps_codec->s_rate_control.pps_rate_control_api,
2422 ps_cfg->u4_target_bitrate);
2423
2424 ps_curr_cfg->u4_target_bitrate = ps_cfg->u4_target_bitrate;
2425 }
2426 }
2427 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMETYPE)
2428 {
2429 switch (ps_cfg->e_frame_type)
2430 {
2431 case IV_I_FRAME:
2432 ps_codec->force_curr_frame_type = IV_I_FRAME;
2433 break;
2434
2435 case IV_IDR_FRAME:
2436 ps_codec->force_curr_frame_type = IV_IDR_FRAME;
2437 break;
2438
2439 case IV_P_FRAME:
2440 default:
2441 break;
2442 }
2443 }
2444 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ME_PARAMS)
2445 {
2446 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2447 {
2448 ps_codec->s_cfg.u4_enable_hpel = ps_cfg->u4_enable_hpel;
2449 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad;
2450 ps_codec->s_cfg.u4_me_speed_preset = ps_cfg->u4_me_speed_preset;
2451 ps_codec->s_cfg.u4_enable_qpel = ps_cfg->u4_enable_qpel;
2452 }
2453 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST)
2454 {
2455 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad;
2456 }
2457 ps_codec->s_cfg.u4_srch_rng_x = ps_cfg->u4_srch_rng_x;
2458 ps_codec->s_cfg.u4_srch_rng_y = ps_cfg->u4_srch_rng_y;
2459
2460 if (ps_codec->s_cfg.u4_enable_alt_ref != ps_cfg->u4_enable_alt_ref)
2461 {
2462 ps_codec->s_cfg.u4_enable_alt_ref = ps_cfg->u4_enable_alt_ref;
2463 ps_codec->u4_is_curr_frm_ref = 1;
2464 }
2465 }
2466 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_IPE_PARAMS)
2467 {
2468 ps_curr_cfg->u4_enc_speed_preset = ps_cfg->u4_enc_speed_preset;
2469
2470 ps_curr_cfg->u4_constrained_intra_pred = ps_cfg->u4_constrained_intra_pred;
2471
2472 if (ps_curr_cfg->u4_enc_speed_preset != IVE_CONFIG)
2473 {
2474 ih264e_speed_preset_side_effects(ps_codec);
2475 }
2476 else
2477 {
2478 ps_curr_cfg->u4_enable_intra_4x4 = ps_cfg->u4_enable_intra_4x4;
2479 }
2480 }
2481 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_GOP_PARAMS)
2482 {
2483 if (ps_curr_cfg->u4_i_frm_interval != ps_cfg->u4_i_frm_interval)
2484 {
2485 ps_curr_cfg->u4_i_frm_interval = ps_cfg->u4_i_frm_interval;
2486
2487 /* reset air counter */
2488 ps_codec->i4_air_pic_cnt = -1;
2489
2490 /* re-init air map */
2491 ih264e_init_air_map(ps_codec);
2492
2493 /* Effect intra frame interval change */
2494 irc_change_intra_frm_int_call(
2495 ps_codec->s_rate_control.pps_rate_control_api,
2496 ps_curr_cfg->u4_i_frm_interval);
2497 }
2498
2499 ps_curr_cfg->u4_idr_frm_interval = ps_cfg->u4_idr_frm_interval;
2500
2501 }
2502 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DEBLOCK_PARAMS)
2503 {
2504 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2505 {
2506 ps_curr_cfg->u4_disable_deblock_level =
2507 ps_cfg->u4_disable_deblock_level;
2508 }
2509 }
2510 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_QP)
2511 {
2512 UWORD8 au1_init_qp[MAX_PIC_TYPE];
2513 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE];
2514
2515 ps_codec->s_cfg.u4_i_qp_max = ps_cfg->u4_i_qp_max;
2516 ps_codec->s_cfg.u4_i_qp_min = ps_cfg->u4_i_qp_min;
2517 ps_codec->s_cfg.u4_i_qp = ps_cfg->u4_i_qp;
2518
2519 ps_codec->s_cfg.u4_p_qp_max = ps_cfg->u4_p_qp_max;
2520 ps_codec->s_cfg.u4_p_qp_min = ps_cfg->u4_p_qp_min;
2521 ps_codec->s_cfg.u4_p_qp = ps_cfg->u4_p_qp;
2522
2523 ps_codec->s_cfg.u4_b_qp_max = ps_cfg->u4_b_qp_max;
2524 ps_codec->s_cfg.u4_b_qp_min = ps_cfg->u4_b_qp_min;
2525 ps_codec->s_cfg.u4_b_qp = ps_cfg->u4_b_qp;
2526
2527 /* update rc lib with modified qp */
2528 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp];
2529 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp];
2530 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp];
2531
2532 irc_change_init_qp(ps_codec->s_rate_control.pps_rate_control_api,
2533 au1_init_qp);
2534
2535 au1_min_max_qp[2 * I_PIC] =
2536 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min];
2537 au1_min_max_qp[2 * I_PIC + 1] =
2538 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max];
2539
2540 au1_min_max_qp[2 * P_PIC] =
2541 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min];
2542 au1_min_max_qp[2 * P_PIC + 1] =
2543 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max];
2544
2545 au1_min_max_qp[2 * B_PIC] =
2546 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min];
2547 au1_min_max_qp[2 * B_PIC + 1] =
2548 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max];
2549
2550 irc_change_min_max_qp(ps_codec->s_rate_control.pps_rate_control_api,
2551 au1_min_max_qp);
2552 }
2553 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ENC_MODE)
2554 {
2555 ps_codec->s_cfg.e_enc_mode = ps_cfg->e_enc_mode;
2556
2557 if (ps_codec->s_cfg.e_enc_mode == IVE_ENC_MODE_HEADER)
2558 {
2559 ps_codec->i4_header_mode = 1;
2560 ps_codec->s_cfg.e_enc_mode = IVE_ENC_MODE_PICTURE;
2561 }
2562 else
2563 {
2564 ps_codec->i4_header_mode = 0;
2565 }
2566 }
2567 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VBV_PARAMS
2568 && IVE_RC_NONE != ps_codec->s_cfg.e_rc_mode)
2569 {
2570 ps_codec->s_cfg.u4_vbv_buf_size = ps_cfg->u4_vbv_buf_size;
2571 ps_codec->s_cfg.u4_vbv_buffer_delay = ps_cfg->u4_vbv_buffer_delay;
2572
2573 // irc_change_buffer_delay(ps_codec->s_rate_control.pps_rate_control_api, ps_codec->s_cfg.u4_vbv_buffer_delay);
2574
2575 // TODO: remove this when the support for changing buffer dynamically
2576 // is yet to be added.
2577 u4_init_rc = 1;
2578 }
2579 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_AIR_PARAMS)
2580 {
2581 if (ps_curr_cfg->e_air_mode != ps_cfg->e_air_mode
2582 || ps_curr_cfg->u4_air_refresh_period
2583 != ps_cfg->u4_air_refresh_period)
2584 {
2585 ps_curr_cfg->e_air_mode = ps_cfg->e_air_mode;
2586 ps_curr_cfg->u4_air_refresh_period = ps_cfg->u4_air_refresh_period;
2587
2588 ih264e_init_air_map(ps_codec);
2589
2590 /* reset air counter */
2591 ps_codec->i4_air_pic_cnt = -1;
2592 }
2593 }
2594 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_PROFILE_PARAMS)
2595 {
2596 ps_codec->s_cfg.e_profile = ps_cfg->e_profile;
2597 ps_codec->s_cfg.u4_entropy_coding_mode = ps_cfg->u4_entropy_coding_mode;
2598 }
2599 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_NUM_CORES)
2600 {
2601 ps_codec->s_cfg.u4_num_cores = ps_cfg->u4_num_cores;
2602 }
2603 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VUI_PARAMS)
2604 {
2605 ps_codec->s_cfg.s_vui = ps_cfg->s_vui;
2606 }
2607
2608 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_MDCV_PARAMS)
2609 {
2610 ps_codec->s_cfg.s_sei.u1_sei_mdcv_params_present_flag =
2611 ps_cfg->s_sei.u1_sei_mdcv_params_present_flag;
2612 ps_codec->s_cfg.s_sei.s_sei_mdcv_params = ps_cfg->s_sei.s_sei_mdcv_params;
2613 }
2614 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_CLL_PARAMS)
2615 {
2616 ps_codec->s_cfg.s_sei.u1_sei_cll_params_present_flag =
2617 ps_cfg->s_sei.u1_sei_cll_params_present_flag;
2618 ps_codec->s_cfg.s_sei.s_sei_cll_params = ps_cfg->s_sei.s_sei_cll_params;
2619 }
2620 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_AVE_PARAMS)
2621 {
2622 ps_codec->s_cfg.s_sei.u1_sei_ave_params_present_flag =
2623 ps_cfg->s_sei.u1_sei_ave_params_present_flag;
2624 ps_codec->s_cfg.s_sei.s_sei_ave_params = ps_cfg->s_sei.s_sei_ave_params;
2625 }
2626 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_CCV_PARAMS)
2627 {
2628 ps_codec->s_cfg.s_sei.u1_sei_ccv_params_present_flag =
2629 ps_cfg->s_sei.u1_sei_ccv_params_present_flag;
2630 ps_codec->s_cfg.s_sei.s_sei_ccv_params = ps_cfg->s_sei.s_sei_ccv_params;
2631 }
2632 else if(ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_SII_PARAMS)
2633 {
2634 ps_codec->s_cfg.s_sei.u1_sei_sii_params_present_flag =
2635 ps_cfg->s_sei.u1_sei_sii_params_present_flag;
2636 ps_codec->s_cfg.s_sei.s_sei_sii_params = ps_cfg->s_sei.s_sei_sii_params;
2637 }
2638
2639 /* reset RC model */
2640 if (u4_init_rc)
2641 {
2642 /* init qp */
2643 UWORD8 au1_init_qp[MAX_PIC_TYPE];
2644
2645 /* min max qp */
2646 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE];
2647
2648 /* init i,p,b qp */
2649 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp];
2650 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp];
2651 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp];
2652
2653 /* init min max qp */
2654 au1_min_max_qp[2 * I_PIC] =
2655 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min];
2656 au1_min_max_qp[2 * I_PIC + 1] =
2657 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max];
2658
2659 au1_min_max_qp[2 * P_PIC] =
2660 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min];
2661 au1_min_max_qp[2 * P_PIC + 1] =
2662 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max];
2663
2664 au1_min_max_qp[2 * B_PIC] =
2665 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min];
2666 au1_min_max_qp[2 * B_PIC + 1] =
2667 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max];
2668
2669 /* get rc mode */
2670 switch (ps_codec->s_cfg.e_rc_mode)
2671 {
2672 case IVE_RC_STORAGE:
2673 ps_codec->s_rate_control.e_rc_type = VBR_STORAGE;
2674 break;
2675
2676 case IVE_RC_CBR_NON_LOW_DELAY:
2677 ps_codec->s_rate_control.e_rc_type = CBR_NLDRC;
2678 break;
2679
2680 case IVE_RC_CBR_LOW_DELAY:
2681 ps_codec->s_rate_control.e_rc_type = CBR_LDRC;
2682 break;
2683
2684 case IVE_RC_NONE:
2685 ps_codec->s_rate_control.e_rc_type = CONST_QP;
2686 break;
2687
2688 default:
2689 break;
2690 }
2691
2692 /* init rate control */
2693 ih264e_rc_init(ps_codec->s_rate_control.pps_rate_control_api,
2694 ps_codec->s_rate_control.pps_frame_time,
2695 ps_codec->s_rate_control.pps_time_stamp,
2696 ps_codec->s_rate_control.pps_pd_frm_rate,
2697 ps_codec->s_cfg.u4_max_framerate,
2698 ps_codec->s_cfg.u4_src_frame_rate,
2699 ps_codec->s_cfg.u4_tgt_frame_rate,
2700 ps_codec->s_rate_control.e_rc_type,
2701 ps_codec->s_cfg.u4_target_bitrate,
2702 ps_codec->s_cfg.u4_max_bitrate,
2703 ps_codec->s_cfg.u4_vbv_buffer_delay,
2704 ps_codec->s_cfg.u4_i_frm_interval,
2705 ps_codec->s_cfg.u4_num_bframes + 1, au1_init_qp,
2706 ps_codec->s_cfg.u4_num_bframes + 2, au1_min_max_qp,
2707 ps_codec->s_cfg.u4_max_level);
2708 }
2709
2710 return err;
2711 }
2712
2713 /**
2714 *******************************************************************************
2715 *
2716 * @brief
2717 * Sets default encoder config parameters
2718 *
2719 * @par Description:
2720 * Sets default dynamic parameters. Will be called in ih264e_init() to ensure
2721 * that even if set_params is not called, codec continues to work
2722 *
2723 * @param[in] ps_cfg
2724 * Pointer to encoder config params
2725 *
2726 * @returns error status
2727 *
2728 * @remarks none
2729 *
2730 *******************************************************************************
2731 */
ih264e_set_default_params(cfg_params_t * ps_cfg)2732 static WORD32 ih264e_set_default_params(cfg_params_t *ps_cfg)
2733 {
2734 WORD32 ret = IV_SUCCESS;
2735
2736 ps_cfg->u4_max_wd = MAX_WD;
2737 ps_cfg->u4_max_ht = MAX_HT;
2738 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
2739 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
2740 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
2741 ps_cfg->e_inp_color_fmt = IV_YUV_420SP_UV;
2742 ps_cfg->u4_enable_recon = DEFAULT_RECON_ENABLE;
2743 ps_cfg->u4_enable_quality_metrics = DEFAULT_QUALITY_METRICS_ENABLE;
2744 ps_cfg->e_recon_color_fmt = IV_YUV_420P;
2745 ps_cfg->u4_enc_speed_preset = IVE_FASTEST;
2746 ps_cfg->e_rc_mode = DEFAULT_RC;
2747 ps_cfg->u4_max_framerate = DEFAULT_MAX_FRAMERATE;
2748 ps_cfg->u4_max_bitrate = DEFAULT_MAX_BITRATE;
2749 ps_cfg->u4_num_bframes = DEFAULT_MAX_NUM_BFRAMES;
2750 ps_cfg->e_content_type = IV_PROGRESSIVE;
2751 ps_cfg->u4_max_srch_rng_x = DEFAULT_MAX_SRCH_RANGE_X;
2752 ps_cfg->u4_max_srch_rng_y = DEFAULT_MAX_SRCH_RANGE_Y;
2753 ps_cfg->e_slice_mode = IVE_SLICE_MODE_NONE;
2754 ps_cfg->u4_slice_param = DEFAULT_SLICE_PARAM;
2755 ps_cfg->e_arch = ih264e_default_arch();
2756 ps_cfg->e_soc = SOC_GENERIC;
2757 ps_cfg->u4_disp_wd = MAX_WD;
2758 ps_cfg->u4_disp_ht = MAX_HT;
2759 ps_cfg->u4_wd = MAX_WD;
2760 ps_cfg->u4_ht = MAX_HT;
2761 ps_cfg->u4_src_frame_rate = DEFAULT_SRC_FRAME_RATE;
2762 ps_cfg->u4_tgt_frame_rate = DEFAULT_TGT_FRAME_RATE;
2763 ps_cfg->u4_target_bitrate = DEFAULT_BITRATE;
2764 ps_cfg->e_frame_type = IV_NA_FRAME;
2765 ps_cfg->e_enc_mode = IVE_ENC_MODE_DEFAULT;
2766 ps_cfg->u4_i_qp = DEFAULT_I_QP;
2767 ps_cfg->u4_p_qp = DEFAULT_P_QP;
2768 ps_cfg->u4_b_qp = DEFAULT_B_QP;
2769 ps_cfg->u4_i_qp_min = DEFAULT_QP_MIN;
2770 ps_cfg->u4_i_qp_max = DEFAULT_QP_MAX;
2771 ps_cfg->u4_p_qp_min = DEFAULT_QP_MIN;
2772 ps_cfg->u4_p_qp_max = DEFAULT_QP_MAX;
2773 ps_cfg->u4_b_qp_min = DEFAULT_QP_MIN;
2774 ps_cfg->u4_b_qp_max = DEFAULT_QP_MAX;
2775 ps_cfg->e_air_mode = DEFAULT_AIR_MODE;
2776 ps_cfg->u4_air_refresh_period = DEFAULT_AIR_REFRESH_PERIOD;
2777 ps_cfg->u4_vbv_buffer_delay = DEFAULT_VBV_DELAY;
2778 ps_cfg->u4_vbv_buf_size = DEFAULT_VBV_SIZE;
2779 ps_cfg->u4_num_cores = DEFAULT_NUM_CORES;
2780 ps_cfg->u4_me_speed_preset = DEFAULT_ME_SPEED_PRESET;
2781 ps_cfg->u4_enable_hpel = DEFAULT_HPEL;
2782 ps_cfg->u4_enable_qpel = DEFAULT_QPEL;
2783 ps_cfg->u4_enable_intra_4x4 = DEFAULT_I4;
2784 ps_cfg->u4_enable_intra_8x8 = DEFAULT_I8;
2785 ps_cfg->u4_enable_intra_16x16 = DEFAULT_I16;
2786 ps_cfg->u4_enable_fast_sad = DEFAULT_ENABLE_FAST_SAD;
2787 ps_cfg->u4_enable_satqd = DEFAULT_ENABLE_SATQD;
2788 ps_cfg->i4_min_sad =
2789 (ps_cfg->u4_enable_satqd == DEFAULT_ENABLE_SATQD) ?
2790 DEFAULT_MIN_SAD_ENABLE :
2791 DEFAULT_MIN_SAD_DISABLE;
2792 ps_cfg->u4_srch_rng_x = DEFAULT_SRCH_RNG_X;
2793 ps_cfg->u4_srch_rng_y = DEFAULT_SRCH_RNG_Y;
2794 ps_cfg->u4_i_frm_interval = DEFAULT_I_INTERVAL;
2795 ps_cfg->u4_idr_frm_interval = DEFAULT_IDR_INTERVAL;
2796 ps_cfg->u4_disable_deblock_level = DEFAULT_DISABLE_DEBLK_LEVEL;
2797 ps_cfg->e_profile = DEFAULT_PROFILE;
2798 ps_cfg->u4_timestamp_low = 0;
2799 ps_cfg->u4_timestamp_high = 0;
2800 ps_cfg->u4_is_valid = 1;
2801 ps_cfg->e_cmd = IVE_CMD_CT_NA;
2802 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
2803 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
2804 ps_cfg->u4_entropy_coding_mode = DEFAULT_ENTROPY_CODING_MODE;
2805 ps_cfg->u4_weighted_prediction = 0;
2806 ps_cfg->u4_constrained_intra_pred = DEFAULT_CONSTRAINED_INTRAPRED;
2807 ps_cfg->u4_pic_info_type = 0;
2808 ps_cfg->u4_mb_info_type = 0;
2809 ps_cfg->s_vui.u1_video_signal_type_present_flag = 0;
2810 ps_cfg->s_vui.u1_colour_description_present_flag = 0;
2811
2812 return ret;
2813 }
2814
2815 /**
2816 *******************************************************************************
2817 *
2818 * @brief
2819 * Initialize encoder context. This will be called by init_mem_rec and during
2820 * codec reset
2821 *
2822 * @par Description:
2823 * Initializes the context
2824 *
2825 * @param[in] ps_codec
2826 * Codec context pointer
2827 *
2828 * @returns error status
2829 *
2830 * @remarks none
2831 *
2832 *******************************************************************************
2833 */
ih264e_init(codec_t * ps_codec)2834 static WORD32 ih264e_init(codec_t *ps_codec)
2835 {
2836 /* enc config param set */
2837 cfg_params_t *ps_cfg = &(ps_codec->s_cfg);
2838
2839 /* temp var */
2840 WORD32 i;
2841
2842 /* coded pic count */
2843 ps_codec->i4_poc = 0;
2844
2845 /* Number of API calls to encode are made */
2846 ps_codec->i4_encode_api_call_cnt = -1;
2847
2848 /* Indicates no header has been generated yet */
2849 ps_codec->u4_header_generated = 0;
2850
2851 /* Number of pictures encoded */
2852 ps_codec->i4_pic_cnt = -1;
2853
2854 /* Number of threads created */
2855 ps_codec->i4_proc_thread_cnt = 0;
2856
2857 /* ctl mutex init */
2858 ithread_mutex_init(ps_codec->pv_ctl_mutex);
2859
2860 /* Set encoder chroma format */
2861 ps_codec->e_codec_color_format =
2862 (ps_cfg->e_inp_color_fmt == IV_YUV_420SP_VU) ?
2863 IV_YUV_420SP_VU : IV_YUV_420SP_UV;
2864
2865 /* Number of continuous frames where deblocking was disabled */
2866 ps_codec->i4_disable_deblk_pic_cnt = 0;
2867
2868 /* frame num */
2869 ps_codec->i4_frame_num = 0;
2870
2871 /* set the current frame type to I frame, since we are going to start encoding*/
2872 ps_codec->force_curr_frame_type = IV_NA_FRAME;
2873
2874 /* idr_pic_id */
2875 ps_codec->i4_idr_pic_id = -1;
2876
2877 /* Flush mode */
2878 ps_codec->i4_flush_mode = 0;
2879
2880 /* Encode header mode */
2881 ps_codec->i4_header_mode = 0;
2882
2883 /* Encode generate header */
2884 ps_codec->i4_gen_header = 0;
2885
2886 /* To signal successful completion of init */
2887 ps_codec->i4_init_done = 1;
2888
2889 /* To signal that at least one picture was decoded */
2890 ps_codec->i4_first_pic_done = 0;
2891
2892 /* Reset Codec */
2893 ps_codec->i4_reset_flag = 0;
2894
2895 /* Current error code */
2896 ps_codec->i4_error_code = IH264E_SUCCESS;
2897
2898 /* threshold residue */
2899 ps_codec->u4_thres_resi = 1;
2900
2901 /* inter gating enable */
2902 ps_codec->u4_inter_gate = 0;
2903
2904 /* entropy mutex init */
2905 ithread_mutex_init(ps_codec->pv_entropy_mutex);
2906
2907 /* sps id */
2908 ps_codec->i4_sps_id = 0;
2909
2910 /* sps id */
2911 ps_codec->i4_pps_id = 0;
2912
2913 /* Process thread created status */
2914 memset(ps_codec->ai4_process_thread_created, 0,
2915 sizeof(ps_codec->ai4_process_thread_created));
2916
2917 memset(&ps_codec->s_global_quality_stats, 0, sizeof(ps_codec->s_global_quality_stats));
2918
2919 /* Number of MBs processed together */
2920 ps_codec->i4_proc_nmb = 8;
2921
2922 /* Previous POC msb */
2923 ps_codec->i4_prev_poc_msb = 0;
2924
2925 /* Previous POC lsb */
2926 ps_codec->i4_prev_poc_lsb = -1;
2927
2928 /* max Previous POC lsb */
2929 ps_codec->i4_max_prev_poc_lsb = -1;
2930
2931 /* sps, pps status */
2932 {
2933 sps_t *ps_sps = ps_codec->ps_sps_base;
2934 pps_t *ps_pps = ps_codec->ps_pps_base;
2935
2936 for (i = 0; i < MAX_SPS_CNT; i++)
2937 {
2938 ps_sps->i1_sps_valid = 0;
2939 ps_sps++;
2940 }
2941
2942 for (i = 0; i < MAX_PPS_CNT; i++)
2943 {
2944 ps_pps->i1_pps_valid = 0;
2945 ps_pps++;
2946 }
2947 }
2948
2949 {
2950 WORD32 max_mb_rows = ps_cfg->i4_ht_mbs;
2951
2952 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
2953 WORD32 clz;
2954
2955 /* Use next power of two number of entries*/
2956 clz = CLZ(num_jobs);
2957 num_jobs = 1 << (32 - clz);
2958
2959 /* init process jobq */
2960 ps_codec->pv_proc_jobq = ih264_list_init(
2961 ps_codec->pv_proc_jobq_buf,
2962 ps_codec->i4_proc_jobq_buf_size, num_jobs,
2963 sizeof(job_t), 10);
2964 RETURN_IF((ps_codec->pv_proc_jobq == NULL), IV_FAIL);
2965 ih264_list_reset(ps_codec->pv_proc_jobq);
2966
2967 /* init entropy jobq */
2968 ps_codec->pv_entropy_jobq = ih264_list_init(
2969 ps_codec->pv_entropy_jobq_buf,
2970 ps_codec->i4_entropy_jobq_buf_size, num_jobs,
2971 sizeof(job_t), 10);
2972 RETURN_IF((ps_codec->pv_entropy_jobq == NULL), IV_FAIL);
2973 ih264_list_reset(ps_codec->pv_entropy_jobq);
2974 }
2975
2976 /* Update the jobq context to all the threads */
2977 for (i = 0; i < MAX_PROCESS_CTXT; i++)
2978 {
2979 ps_codec->as_process[i].pv_proc_jobq = ps_codec->pv_proc_jobq;
2980 ps_codec->as_process[i].pv_entropy_jobq = ps_codec->pv_entropy_jobq;
2981
2982 /* i4_id always stays between 0 and MAX_PROCESS_THREADS */
2983 ps_codec->as_process[i].i4_id =
2984 (i >= MAX_PROCESS_THREADS) ?
2985 (i - MAX_PROCESS_THREADS) : i;
2986 ps_codec->as_process[i].ps_codec = ps_codec;
2987
2988 ps_codec->as_process[i].s_entropy.pv_proc_jobq = ps_codec->pv_proc_jobq;
2989 ps_codec->as_process[i].s_entropy.pv_entropy_jobq =
2990 ps_codec->pv_entropy_jobq;
2991 ps_codec->as_process[i].s_entropy.i4_abs_pic_order_cnt = -1;
2992 }
2993
2994 /* Initialize MV Bank buffer manager */
2995 ps_codec->pv_mv_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_mv_buf_mgr_base);
2996
2997 /* Initialize Picture buffer manager for reference buffers*/
2998 ps_codec->pv_ref_buf_mgr = ih264_buf_mgr_init(
2999 ps_codec->pv_ref_buf_mgr_base);
3000
3001 /* Initialize Picture buffer manager for input buffers*/
3002 ps_codec->pv_inp_buf_mgr = ih264_buf_mgr_init(
3003 ps_codec->pv_inp_buf_mgr_base);
3004
3005 /* Initialize buffer manager for output buffers*/
3006 ps_codec->pv_out_buf_mgr = ih264_buf_mgr_init(
3007 ps_codec->pv_out_buf_mgr_base);
3008
3009 /* buffer cnt in buffer manager */
3010 ps_codec->i4_inp_buf_cnt = 0;
3011 ps_codec->i4_out_buf_cnt = 0;
3012 ps_codec->i4_ref_buf_cnt = 0;
3013
3014 ps_codec->ps_pic_buf = (pic_buf_t *) ps_codec->pv_pic_buf_base;
3015 memset(ps_codec->ps_pic_buf, 0, BUF_MGR_MAX_CNT * sizeof(pic_buf_t));
3016
3017 /* Initialize dpb manager */
3018 ih264_dpb_mgr_init((dpb_mgr_t*) ps_codec->pv_dpb_mgr);
3019
3020 memset(ps_codec->as_ref_set, 0,
3021 sizeof(ref_set_t) * (MAX_DPB_SIZE + MAX_CTXT_SETS));
3022 for (i = 0; i < (MAX_DPB_SIZE + MAX_CTXT_SETS); i++)
3023 {
3024 ps_codec->as_ref_set[i].i4_pic_cnt = -1;
3025 }
3026
3027 /* fn ptr init */
3028 ih264e_init_function_ptr(ps_codec);
3029
3030 /* reset status flags */
3031 for (i = 0; i < MAX_CTXT_SETS; i++)
3032 {
3033 ps_codec->au4_entropy_thread_active[i] = 0;
3034 ps_codec->ai4_pic_cnt[i] = -1;
3035
3036 ps_codec->s_rate_control.pre_encode_skip[i] = 0;
3037 ps_codec->s_rate_control.post_encode_skip[i] = 0;
3038 }
3039
3040 ps_codec->s_rate_control.num_intra_in_prev_frame = 0;
3041 ps_codec->s_rate_control.i4_avg_activity = 0;
3042
3043 return IV_SUCCESS;
3044 }
3045
3046 /**
3047 *******************************************************************************
3048 *
3049 * @brief
3050 * Gets number of memory records required by the codec
3051 *
3052 * @par Description:
3053 * Gets codec memory requirements
3054 *
3055 * @param[in] pv_api_ip
3056 * Pointer to input argument structure
3057 *
3058 * @param[out] pv_api_op
3059 * Pointer to output argument structure
3060 *
3061 * @returns status
3062 *
3063 * @remarks
3064 *
3065 *******************************************************************************
3066 */
ih264e_get_num_rec(void * pv_api_ip,void * pv_api_op)3067 static WORD32 ih264e_get_num_rec(void *pv_api_ip, void *pv_api_op)
3068 {
3069 /* api call I/O structures */
3070 ih264e_num_mem_rec_op_t *ps_op = pv_api_op;
3071
3072 UNUSED(pv_api_ip);
3073
3074 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT;
3075
3076 return IV_SUCCESS;
3077 }
3078
3079 /**
3080 *******************************************************************************
3081 *
3082 * @brief
3083 * Fills memory records of the codec
3084 *
3085 * @par Description:
3086 * Fills codec memory requirements
3087 *
3088 * @param[in] pv_api_ip
3089 * Pointer to input argument structure
3090 *
3091 * @param[out] pv_api_op
3092 * Pointer to output argument structure
3093 *
3094 * @returns error status
3095 *
3096 * @remarks none
3097 *
3098 *******************************************************************************
3099 */
ih264e_fill_num_mem_rec(void * pv_api_ip,void * pv_api_op)3100 static WORD32 ih264e_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
3101 {
3102 /* api call I/O structures */
3103 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
3104 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op;
3105
3106 /* profile / level info */
3107 WORD32 level;
3108 WORD32 num_reorder_frames;
3109 WORD32 num_ref_frames;
3110
3111 /* mem records */
3112 WORD32 no_of_mem_rec;
3113 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
3114
3115 /* frame dimensions */
3116 WORD32 max_wd_luma, max_ht_luma;
3117 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
3118
3119 /* temp var */
3120 WORD32 i;
3121
3122 /* error status */
3123 IV_STATUS_T status = IV_SUCCESS;
3124
3125 num_reorder_frames = ps_ip->s_ive_ip.u4_max_reorder_cnt;
3126 num_ref_frames = ps_ip->s_ive_ip.u4_max_ref_cnt;
3127
3128 /* mem records */
3129 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
3130 no_of_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
3131
3132 /* frame dimensions */
3133 max_ht_luma = ps_ip->s_ive_ip.u4_max_ht;
3134 max_wd_luma = ps_ip->s_ive_ip.u4_max_wd;
3135 max_ht_luma = ALIGN16(max_ht_luma);
3136 max_wd_luma = ALIGN16(max_wd_luma);
3137 max_mb_rows = max_ht_luma / MB_SIZE;
3138 max_mb_cols = max_wd_luma / MB_SIZE;
3139 max_mb_cnt = max_mb_rows * max_mb_cols;
3140
3141 /* profile / level info */
3142 level = ih264e_get_min_level(max_wd_luma, max_ht_luma);
3143
3144 /* validate params */
3145 if ((level < MIN_LEVEL) || (level > MAX_LEVEL))
3146 {
3147 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
3148 level = MAX_LEVEL;
3149 }
3150
3151 if (num_ref_frames > MAX_REF_CNT)
3152 {
3153 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
3154 num_ref_frames = MAX_REF_CNT;
3155 }
3156
3157 if (num_reorder_frames > MAX_REF_CNT)
3158 {
3159 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
3160 num_reorder_frames = MAX_REF_CNT;
3161 }
3162
3163 /* Set all memory records as persistent and alignment as 128 by default */
3164 ps_mem_rec = ps_mem_rec_base;
3165 for (i = 0; i < no_of_mem_rec; i++)
3166 {
3167 ps_mem_rec->u4_mem_alignment = 128;
3168 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
3169 ps_mem_rec++;
3170 }
3171
3172 /************************************************************************
3173 * Request memory for h264 encoder handle *
3174 ***********************************************************************/
3175 ps_mem_rec = &ps_mem_rec_base[MEM_REC_IV_OBJ];
3176 {
3177 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
3178 }
3179 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_IV_OBJ, ps_mem_rec->u4_mem_size);
3180
3181 /************************************************************************
3182 * Request memory for h264 encoder context *
3183 ***********************************************************************/
3184 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
3185 {
3186 ps_mem_rec->u4_mem_size = sizeof(codec_t);
3187 }
3188 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CODEC, ps_mem_rec->u4_mem_size);
3189
3190 /************************************************************************
3191 * Request memory for CABAC context *
3192 ***********************************************************************/
3193 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC];
3194 {
3195 ps_mem_rec->u4_mem_size = sizeof(cabac_ctxt_t);
3196 }
3197 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC, ps_mem_rec->u4_mem_size);
3198
3199 /************************************************************************
3200 * Request memory for CABAC MB info *
3201 ***********************************************************************/
3202 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO];
3203 {
3204 ps_mem_rec->u4_mem_size = ((max_mb_cols + 1) + 1)
3205 * sizeof(mb_info_ctxt_t);
3206 }
3207 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC_MB_INFO, ps_mem_rec->u4_mem_size);
3208
3209
3210 /************************************************************************
3211 * Request memory for entropy context *
3212 * In multi core encoding, each row is assumed to be launched on a *
3213 * thread. The rows below can only start after its neighbors are coded *
3214 * The status of an mb coded/uncoded is signaled via entropy map. *
3215 * 1. One word32 to store skip run cnt *
3216 * 2. mb entropy map (mb status entropy coded/uncoded). The size*
3217 * of the entropy map is max mb cols. Further allocate one *
3218 * more additional row to evade checking for row -1. *
3219 * 3. size of bit stream buffer to store bit stream ctxt. *
3220 * 4. Entropy coding is dependent on nnz coefficient count for *
3221 * the neighbor blocks. It is sufficient to maintain one row *
3222 * worth of nnz as entropy for lower row waits on entropy map*
3223 ************************************************************************/
3224 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY];
3225 {
3226 /* total size of the mem record */
3227 WORD32 total_size = 0;
3228
3229 /* size of skip mb run */
3230 total_size += sizeof(WORD32);
3231 total_size = ALIGN8(total_size);
3232
3233 /* size in bytes to store entropy status of an entire frame */
3234 total_size += (max_mb_cols * max_mb_rows);
3235 /* add an additional 1 row of bytes to evade the special case of row 0 */
3236 total_size += max_mb_cols;
3237 total_size = ALIGN128(total_size);
3238
3239 /* size of bit stream buffer */
3240 total_size += sizeof(bitstrm_t);
3241 total_size = ALIGN128(total_size);
3242
3243 /* top nnz luma */
3244 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
3245 total_size = ALIGN128(total_size);
3246
3247 /* top nnz cbcr */
3248 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
3249 total_size = ALIGN128(total_size);
3250
3251 /* total size per each proc ctxt */
3252 total_size *= MAX_CTXT_SETS;
3253
3254 ps_mem_rec->u4_mem_size = total_size;
3255 }
3256 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY, ps_mem_rec->u4_mem_size);
3257
3258 /************************************************************************
3259 * The residue coefficients that needs to be entropy coded are packed *
3260 * at a buffer space by the proc threads. The entropy thread shall *
3261 * read from the buffer space, unpack them and encode the same. The *
3262 * buffer space required to pack a row of mbs are as follows. *
3263 * Assuming transform_8x8_flag is disabled, *
3264 * In the worst case, 1 mb contains 1 dc 4x4 luma sub block, followed *
3265 * by 16 ac 4x4 luma sub blocks, 2 dc chroma 2x2 sub blocks, followed *
3266 * by 8 ac 4x4 chroma sub blocks. *
3267 * For the sake of simplicity we assume that all sub blocks are of *
3268 * type 4x4. The packing of each 4x4 is depicted by the structure *
3269 * tu_sblk_coeff_data_t *
3270 ************************************************************************/
3271 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA];
3272 {
3273 /* temp var */
3274 WORD32 size = 0;
3275
3276 /* size of coeff data of 1 mb */
3277 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
3278
3279 /* size of coeff data of 1 row of mb's */
3280 size *= max_mb_cols;
3281
3282 /* align to avoid any false sharing across threads */
3283 size = ALIGN64(size);
3284
3285 /* size for one full frame */
3286 size *= max_mb_rows;
3287
3288 /* size of each proc buffer set (ping, pong) */
3289 size *= MAX_CTXT_SETS;
3290
3291 ps_mem_rec->u4_mem_size = size;
3292 }
3293 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_COEFF_DATA, ps_mem_rec->u4_mem_size);
3294
3295 /************************************************************************
3296 * while encoding an mb, the mb header data is signaled to the entropy*
3297 * thread by writing to a buffer space. the size of header data per mb *
3298 * is assumed to be 40 bytes *
3299 * TODO: revisit this inference *
3300 ************************************************************************/
3301 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA];
3302 {
3303 /* temp var */
3304 WORD32 size;
3305
3306 /* size per MB */
3307 size = 40;
3308
3309 /* size for 1 row of mbs */
3310 size = size * max_mb_cols;
3311
3312 /* align to avoid any false sharing across threads */
3313 size = ALIGN64(size);
3314
3315 /* size for one full frame */
3316 size *= max_mb_rows;
3317
3318 /* size of each proc buffer set (ping, pong) */
3319 size *= MAX_CTXT_SETS;
3320
3321 ps_mem_rec->u4_mem_size = size;
3322 }
3323 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_HEADER_DATA, ps_mem_rec->u4_mem_size);
3324
3325 /************************************************************************
3326 * Size for holding mv_buf_t for each MV Bank. *
3327 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3328 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3329 * max_dpb_size will be based on max_wd and max_ht *
3330 * For higher max_wd and max_ht this number will be smaller than *
3331 * MAX_DPB_SIZE But during actual initialization number of buffers *
3332 * allocated can be more. *
3333 * *
3334 * One extra MV Bank is needed to hold current pics MV bank. *
3335 * Since this is only a structure allocation and not actual buffer *
3336 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3337 ************************************************************************/
3338 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
3339 {
3340 /* max luma samples */
3341 WORD32 max_luma_samples = 0;
3342
3343 /* determine max luma samples */
3344 for (i = 0; i < 16; i++)
3345 if (level ==(WORD32)gas_ih264_lvl_tbl[i].u4_level_idc)
3346 max_luma_samples = gas_ih264_lvl_tbl[i].u4_max_fs
3347 << (BLK_SIZE + BLK_SIZE);
3348
3349 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3350
3351 /************************************************************************
3352 * Allocate for pu_map, enc_pu_t and pic_pu_idx for each MV bank *
3353 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
3354 * is set to maximum number of luma samples allowed at the given level. *
3355 * This is done to ensure that any stream with width and height lesser *
3356 * than max_wd and max_ht is supported. Number of buffers required can *
3357 * be greater for lower width and heights at a given level and this *
3358 * increased number of buffers might require more memory than what *
3359 * max_wd and max_ht buffer would have required Also note one extra *
3360 * buffer is allocated to store current pictures MV bank. *
3361 ***********************************************************************/
3362
3363 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(mv_buf_t);
3364
3365 ps_mem_rec->u4_mem_size += (num_ref_frames + num_reorder_frames
3366 + MAX_CTXT_SETS)
3367 * ih264e_get_pic_mv_bank_size(max_luma_samples);
3368 }
3369 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBANK, ps_mem_rec->u4_mem_size);
3370
3371 /************************************************************************
3372 * While encoding inter slices, to compute the cost of encoding an mb *
3373 * with the mv's at hand, we employ the expression cost = sad + lambda *
3374 * x mv_bits. Here mv_bits is the total number of bits taken to represe*
3375 * nt the mv in the stream. The mv bits for all the possible mv are *
3376 * stored in the look up table. The mem record for this look up table *
3377 * is given below. *
3378 ************************************************************************/
3379 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS];
3380 {
3381 /* max srch range x */
3382 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3383
3384 /* max srch range y */
3385 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3386
3387 /* max srch range */
3388 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
3389
3390 /* due to subpel */
3391 u4_max_srch_range <<= 2;
3392
3393 /* due to mv on either direction */
3394 u4_max_srch_range = (u4_max_srch_range << 1);
3395
3396 /* due to pred mv + zero */
3397 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
3398
3399 u4_max_srch_range = ALIGN128(u4_max_srch_range);
3400
3401 ps_mem_rec->u4_mem_size = u4_max_srch_range;
3402 }
3403 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBITS, ps_mem_rec->u4_mem_size);
3404
3405 /************************************************************************
3406 * Frame level Intra Cost Map. During intra/inter analysis preserve the*
3407 * intra mb cost for future complexity estimation. *
3408 * NOTE: The cost map is a overlay on the previous frame. In case if an*
3409 * mb is not intra analyzed, the cost here represents its collocated mb*
3410 * intra cost. This traversal can go till the latest I frame at worse *
3411 ************************************************************************/
3412 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INTRA_COST];
3413 {
3414 /* total size of the mem record */
3415 WORD32 total_size = 0;
3416
3417 /* size in bytes to mb core coding status of an entire frame */
3418 total_size = max_mb_cnt * sizeof(WORD32);
3419
3420 ps_mem_rec->u4_mem_size = total_size;
3421 }
3422 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_INTRA_COST, ps_mem_rec->u4_mem_size);
3423
3424 /************************************************************************
3425 * Request memory for SPS *
3426 ***********************************************************************/
3427 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
3428 {
3429 ps_mem_rec->u4_mem_size = MAX_SPS_CNT * sizeof(sps_t);
3430 }
3431 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SPS, ps_mem_rec->u4_mem_size);
3432
3433 /************************************************************************
3434 * Request memory for PPS *
3435 ***********************************************************************/
3436 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
3437 {
3438 ps_mem_rec->u4_mem_size = MAX_PPS_CNT * sizeof(pps_t);
3439 }
3440 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PPS, ps_mem_rec->u4_mem_size);
3441
3442 /************************************************************************
3443 * Request memory for Slice Header *
3444 ***********************************************************************/
3445 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
3446 {
3447 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * MAX_SLICE_HDR_CNT
3448 * sizeof(slice_header_t);
3449 }
3450 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_HDR, ps_mem_rec->u4_mem_size);
3451
3452 /************************************************************************
3453 * Request memory for Adaptive Intra Refresh *
3454 ***********************************************************************/
3455 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP];
3456 {
3457 /* total size of the mem record */
3458 WORD32 total_size = 0;
3459
3460 /* intra coded map */
3461 total_size += max_mb_cnt;
3462 total_size *= MAX_CTXT_SETS;
3463
3464 /* mb refresh map */
3465 total_size += sizeof(UWORD16) * max_mb_cnt;
3466
3467 /* alignment */
3468 total_size = ALIGN128(total_size);
3469
3470 ps_mem_rec->u4_mem_size = total_size;
3471 }
3472 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_AIR_MAP, ps_mem_rec->u4_mem_size);
3473
3474 /************************************************************************
3475 * In multi slice encoding, this memory record helps tracking the start*
3476 * of slice with reference to mb. *
3477 * MEM RECORD for holding *
3478 * 1. mb slice map *
3479 ************************************************************************/
3480 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP];
3481 {
3482 /* total size of the mem record */
3483 WORD32 total_size = 0;
3484
3485 /* size in bytes to slice index of all mbs of a frame */
3486 total_size = ALIGN64(max_mb_cnt);
3487
3488 /* ih264e_update_proc_ctxt can overread by 1 at the end */
3489 total_size += 1;
3490
3491 /* total size per each proc ctxt */
3492 total_size *= MAX_CTXT_SETS;
3493 ps_mem_rec->u4_mem_size = total_size;
3494 }
3495 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_MAP, ps_mem_rec->u4_mem_size);
3496
3497 /************************************************************************
3498 * Request memory to hold thread handles for each processing thread *
3499 ************************************************************************/
3500 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
3501 {
3502 WORD32 handle_size = ithread_get_handle_size();
3503
3504 ps_mem_rec->u4_mem_size = MAX_PROCESS_THREADS * handle_size;
3505 }
3506 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_THREAD_HANDLE, ps_mem_rec->u4_mem_size);
3507
3508 /************************************************************************
3509 * Request memory to hold mutex for control calls *
3510 ************************************************************************/
3511 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX];
3512 {
3513 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
3514 }
3515 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CTL_MUTEX, ps_mem_rec->u4_mem_size);
3516
3517 /************************************************************************
3518 * Request memory to hold mutex for entropy calls *
3519 ************************************************************************/
3520 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX];
3521 {
3522 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
3523 }
3524 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_MUTEX, ps_mem_rec->u4_mem_size);
3525
3526 /************************************************************************
3527 * Request memory to hold process jobs *
3528 ***********************************************************************/
3529 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
3530 {
3531 /* One process job per row of MBs */
3532 /* Allocate for two pictures, so that wrap around can be handled easily */
3533 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
3534
3535 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
3536
3537 ps_mem_rec->u4_mem_size = job_queue_size;
3538 }
3539 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_JOBQ, ps_mem_rec->u4_mem_size);
3540
3541 /************************************************************************
3542 * Request memory to hold entropy jobs *
3543 ***********************************************************************/
3544 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ];
3545 {
3546 /* One process job per row of MBs */
3547 /* Allocate for two pictures, so that wrap around can be handled easily */
3548 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
3549
3550 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
3551
3552 ps_mem_rec->u4_mem_size = job_queue_size;
3553 }
3554 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_JOBQ, ps_mem_rec->u4_mem_size);
3555
3556 /************************************************************************
3557 * In multi core encoding, each row is assumed to be launched on a *
3558 * thread. The rows below can only start after its neighbors are coded *
3559 * The status of an mb coded/uncoded is signaled via proc map. *
3560 * MEM RECORD for holding *
3561 * 1. mb proc map (mb status core coded/uncoded) *
3562 ************************************************************************/
3563 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
3564 {
3565 /* total size of the mem record */
3566 WORD32 total_size = 0;
3567
3568 /* size in bytes to mb core coding status of an entire frame */
3569 total_size = max_mb_cnt;
3570
3571 /* add an additional 1 row of bytes to evade the special case of row 0 */
3572 total_size += max_mb_cols;
3573
3574 /* total size per each proc ctxt */
3575 total_size *= MAX_CTXT_SETS;
3576 ps_mem_rec->u4_mem_size = total_size;
3577 }
3578 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_MAP, ps_mem_rec->u4_mem_size);
3579
3580 /************************************************************************
3581 * mem record for holding a particular MB is deblocked or not *
3582 * 1. mb deblk map (mb status deblocked/not deblocked) *
3583 ************************************************************************/
3584 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP];
3585 {
3586 /* total size of the mem record */
3587 WORD32 total_size = 0;
3588
3589 /* size in bytes to mb core coding status of an entire frame */
3590 total_size = max_mb_cnt;
3591
3592 /* add an additional 1 row of bytes to evade the special case of row 0 */
3593 total_size += max_mb_cols;
3594
3595 total_size = ALIGN64(total_size);
3596
3597 /* total size per each proc ctxt */
3598 total_size *= MAX_CTXT_SETS;
3599 ps_mem_rec->u4_mem_size = total_size;
3600 }
3601 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DBLK_MAP, ps_mem_rec->u4_mem_size);
3602
3603 /************************************************************************
3604 * mem record for holding a particular MB's me is done or not *
3605 * 1. mb me map *
3606 ************************************************************************/
3607 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP];
3608 {
3609 /* total size of the mem record */
3610 WORD32 total_size = 0;
3611
3612 /* size in bytes to mb core coding status of an entire frame */
3613 total_size = max_mb_cnt;
3614
3615 /* add an additional 1 row of bytes to evade the special case of row 0 */
3616 total_size += max_mb_cols;
3617
3618 /* total size per each proc ctxt */
3619 total_size *= MAX_CTXT_SETS;
3620
3621 ps_mem_rec->u4_mem_size = total_size;
3622 }
3623 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ME_MAP, ps_mem_rec->u4_mem_size);
3624
3625 /************************************************************************
3626 * size for holding dpb manager context *
3627 ************************************************************************/
3628 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
3629 {
3630 ps_mem_rec->u4_mem_size = sizeof(dpb_mgr_t);
3631 }
3632 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DPB_MGR, ps_mem_rec->u4_mem_size);
3633
3634 /************************************************************************
3635 * luma or chroma core coding involves mb estimation, error computation*
3636 * between the estimated singnal and the actual signal, transform the *
3637 * error, quantize the error, then inverse transform and inverse quant *
3638 * ize the residue and add the result back to estimated signal. *
3639 * To perform all these, a set of temporary buffers are needed. *
3640 * MEM RECORD for holding scratch buffers *
3641 * 1. prediction buffer used during mb mode analysis *
3642 * 2 temp. reference buffer when intra 4x4 with rdopt on is *
3643 * enabled *
3644 * - when intra 4x4 is enabled, rdopt is on, to store the *
3645 * reconstructed values and use them later this temp. buffer *
3646 * is used. *
3647 * 3. prediction buffer used during intra mode analysis *
3648 * 4. prediction buffer used during intra 16x16 plane mode *
3649 * analysis
3650 * 5. prediction buffer used during intra chroma mode analysis *
3651 * 6. prediction buffer used during intra chroma 16x16 plane *
3652 * mode analysis
3653 * 7. forward transform output buffer *
3654 * - to store the error between estimated and the actual inp *
3655 * ut and to store the fwd transformed quantized output *
3656 * 8. forward transform output buffer *
3657 * - when intra 4x4 is enabled, rdopt is on, to store the *
3658 * fwd transform values and use them later this temp. buffer *
3659 * is used. *
3660 * 9. temporary buffer for inverse transform *
3661 * - temporary buffer used in inverse transform and inverse *
3662 * quantization *
3663 * A. Buffers for holding half_x , half_y and half_xy planes *
3664 ************************************************************************/
3665 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
3666 {
3667 WORD32 total_size = 0;
3668 WORD32 i4_tmp_size;
3669
3670 /* size to hold prediction buffer */
3671 total_size += sizeof(UWORD8) * 16 * 16;
3672 total_size = ALIGN64(total_size);
3673
3674 /* size to hold recon for intra 4x4 buffer */
3675 total_size += sizeof(UWORD8) * 16 * 16;
3676 total_size = ALIGN64(total_size);
3677
3678 /* prediction buffer intra 16x16 */
3679 total_size += sizeof(UWORD8) * 16 * 16;
3680 total_size = ALIGN64(total_size);
3681
3682 /* prediction buffer intra 16x16 plane*/
3683 total_size += sizeof(UWORD8) * 16 * 16;
3684 total_size = ALIGN64(total_size);
3685
3686 /* prediction buffer intra chroma*/
3687 total_size += sizeof(UWORD8) * 16 * 8;
3688 total_size = ALIGN64(total_size);
3689
3690 /* prediction buffer intra chroma plane*/
3691 total_size += sizeof(UWORD8) * 16 * 8;
3692 total_size = ALIGN64(total_size);
3693
3694 /* size to hold fwd transform output */
3695 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
3696 total_size = ALIGN64(total_size);
3697
3698 /* size to hold fwd transform output */
3699 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
3700 total_size = ALIGN64(total_size);
3701
3702 /* size to hold temporary data during inverse transform */
3703 total_size += sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
3704 total_size = ALIGN64(total_size);
3705
3706 /* Buffers for holding half_x , half_y and half_xy planes */
3707 i4_tmp_size = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
3708 total_size += (ALIGN64(i4_tmp_size) * SUBPEL_BUFF_CNT);
3709
3710 /* Allocate for each process thread */
3711 total_size *= MAX_PROCESS_CTXT;
3712
3713 ps_mem_rec->u4_mem_size = total_size;
3714 }
3715 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_SCRATCH, ps_mem_rec->u4_mem_size);
3716
3717 /************************************************************************
3718 * When transform_8x8_flag is disabled, the size of a sub block is *
3719 * 4x4 and when the transform_8x8_flag is enabled the size of the sub *
3720 * block is 8x8. The threshold matrix and the forward scaling list *
3721 * is of the size of the sub block. *
3722 * MEM RECORD for holding *
3723 * 1. quantization parameters for plane y, cb, cr *
3724 * - threshold matrix for quantization *
3725 * - forward weight matrix *
3726 * - satqd threshold matrix *
3727 ************************************************************************/
3728 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM];
3729 {
3730 /* total size of the mem record */
3731 WORD32 total_size = 0;
3732
3733 /* quantization parameter list for planes y,cb and cr */
3734 total_size += ALIGN64(sizeof(quant_params_t)) * 3;
3735
3736 /* size of threshold matrix for quantization
3737 * (assuming the transform_8x8_flag is disabled).
3738 * for all 3 planes */
3739 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
3740
3741 /* size of forward weight matrix for quantization
3742 * (assuming the transform_8x8_flag is disabled).
3743 * for all 3 planes */
3744 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
3745
3746 /* Size for SATDQ threshold matrix for palnes y, cb and cr */
3747 total_size += ALIGN64(sizeof(UWORD16) * 9) * 3;
3748
3749 /* total size per each proc thread */
3750 total_size *= MAX_PROCESS_CTXT;
3751
3752 ps_mem_rec->u4_mem_size = total_size;
3753 }
3754 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_QUANT_PARAM, ps_mem_rec->u4_mem_size);
3755
3756 /************************************************************************
3757 * While computing blocking strength for the current mb, the csbp, mb *
3758 * type for the neighboring mbs are necessary. memtab for storing top *
3759 * row mbtype and csbp is evaluated here. *
3760 * *
3761 * when encoding intra 4x4 or intra 8x8 the submb types are estimated *
3762 * and sent. The estimation is dependent on neighbor mbs. For this *
3763 * store the top row sub mb types for intra mbs *
3764 * *
3765 * During motion vector prediction, the curr mb mv is predicted from *
3766 * neigbors left, top, top right and sometimes top left depending on *
3767 * the availability. The top and top right content is accessed from *
3768 * the memtab specified below. *
3769 ************************************************************************/
3770 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO];
3771 {
3772 /* total size of the mem record */
3773 WORD32 total_size = 0;
3774
3775 /* size in bytes to store 1 row of mb_info_t */
3776 /* one additional mb, to avoid checking end of row condition */
3777 total_size += (max_mb_cols + 1) * sizeof(mb_info_t);
3778
3779 /* size in bytes to store 1 row of intra macroblock sub modes */
3780 total_size += max_mb_cols * sizeof(UWORD8) * 16;
3781
3782 /* size in bytes to store 1 row + 1 of enc_pu_t */
3783 /* one additional mb, to avoid checking end of row condition */
3784 total_size += (max_mb_cols + 1) * sizeof(enc_pu_t);
3785
3786 /* total size per proc ctxt */
3787 total_size = ALIGN128(total_size);
3788
3789 /* total size per each proc ctxt */
3790 total_size *= MAX_CTXT_SETS;
3791 ps_mem_rec->u4_mem_size = total_size;
3792 }
3793 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TOP_ROW_SYN_INFO, ps_mem_rec->u4_mem_size);
3794
3795 /************************************************************************
3796 * When transform_8x8_flag is disabled, the mb is partitioned into *
3797 * 4 sub blocks. This corresponds to 1 vertical left edge and 1 *
3798 * vertical inner edge, 1 horizontal top edge and 1 horizontal *
3799 * inner edge per mb. Further, When transform_8x8_flag is enabled, *
3800 * the mb is partitioned in to 16 sub blocks. This corresponds to *
3801 * 1 vertical left edge and 3 vertical inner edges, 1 horizontal top *
3802 * edge and 3 horizontal inner edges per mb. *
3803 * MEM RECORD for holding *
3804 * 1. vertical edge blocking strength *
3805 * 2. horizontal edge blocking strength *
3806 * 3. mb qp *
3807 * all are frame level *
3808 ************************************************************************/
3809 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
3810 {
3811 /* total size of the mem record */
3812 WORD32 total_size = 0;
3813
3814 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/
3815 WORD32 vert_bs_size, horz_bs_size, qp_size;
3816
3817 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */
3818 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
3819 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
3820 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3821
3822 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */
3823 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
3824 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
3825 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3826
3827 /* qp of each mb requires 1 byte */
3828 qp_size = ALIGN64(max_mb_cnt);
3829
3830 /* total size */
3831 total_size = vert_bs_size + horz_bs_size + qp_size;
3832
3833 /* total size per each proc ctxt */
3834 total_size *= MAX_CTXT_SETS;
3835
3836 ps_mem_rec->u4_mem_size = total_size;
3837 }
3838 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BS_QP, ps_mem_rec->u4_mem_size);
3839
3840 /************************************************************************
3841 * size for holding dpb manager context *
3842 ************************************************************************/
3843 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC];
3844 {
3845 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3846 }
3847 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_INP_PIC, ps_mem_rec->u4_mem_size);
3848
3849 /************************************************************************
3850 * size for holding dpb manager context *
3851 ************************************************************************/
3852 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT];
3853 {
3854 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3855 }
3856 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_OUT, ps_mem_rec->u4_mem_size);
3857
3858 /************************************************************************
3859 * Size for color space conversion *
3860 ************************************************************************/
3861 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC];
3862 {
3863 /* We need a total a memory for a single frame of 420 sp, ie
3864 * (wd * ht) for luma and (wd * ht / 2) for chroma*/
3865 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS
3866 * ((3 * max_ht_luma * max_wd_luma) >> 1);
3867 /* Allocate an extra row, since inverse transform functions for
3868 * chroma access(only read, not used) few extra bytes due to
3869 * interleaved input
3870 */
3871 ps_mem_rec->u4_mem_size += max_wd_luma;
3872 }
3873 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CSC, ps_mem_rec->u4_mem_size);
3874
3875 /************************************************************************
3876 * Size for holding pic_buf_t for each reference picture *
3877 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3878 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3879 * max_dpb_size will be based on max_wd and max_ht *
3880 * For higher max_wd and max_ht this number will be smaller than *
3881 * MAX_DPB_SIZE But during actual initialization number of buffers *
3882 * allocated can be more. *
3883 * *
3884 * Also to handle display depth application can allocate more than *
3885 * what codec asks for in case of non-shared mode *
3886 * Since this is only a structure allocation and not actual buffer *
3887 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3888 ************************************************************************/
3889 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
3890 {
3891 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3892 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(pic_buf_t);
3893
3894 /************************************************************************
3895 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
3896 * is set to maximum number of luma samples allowed at the given level. *
3897 * This is done to ensure that any stream with width and height lesser *
3898 * than max_wd and max_ht is supported. Number of buffers required can *
3899 * be greater for lower width and heights at a given level and this *
3900 * increased number of buffers might require more memory than what *
3901 * max_wd and max_ht buffer would have required. Number of buffers is *
3902 * doubled in order to return one frame at a time instead of sending *
3903 * multiple outputs during dpb full case. Also note one extra buffer is *
3904 * allocted to store current picture. *
3905 * *
3906 * Half-pel planes for each reference buffer are allocated along with *
3907 * the reference buffer. So each reference buffer is 4 times the *
3908 * required size. This way buffer management for the half-pel planes is *
3909 * easier and while using the half-pel planes in MC, an offset can be *
3910 * used from a single pointer *
3911 ***********************************************************************/
3912 ps_mem_rec->u4_mem_size += HPEL_PLANES_CNT
3913 * ih264e_get_total_pic_buf_size(
3914 max_wd_luma * max_ht_luma, level,
3915 PAD_WD, PAD_HT, num_ref_frames,
3916 num_reorder_frames);
3917 }
3918 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_REF_PIC, ps_mem_rec->u4_mem_size);
3919
3920 /************************************************************************
3921 * Request memory to hold mem recs to be returned during retrieve call *
3922 ************************************************************************/
3923 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
3924 {
3925 ps_mem_rec->u4_mem_size = MEM_REC_CNT * sizeof(iv_mem_rec_t);
3926 }
3927 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BACKUP, ps_mem_rec->u4_mem_size);
3928
3929 /************************************************************************
3930 * size for memory required by NMB info structs and buffer for storing *
3931 * half pel plane *
3932 ************************************************************************/
3933 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB];
3934 {
3935 ps_mem_rec->u4_mem_size = MAX_PROCESS_CTXT * max_mb_cols *
3936 (sizeof(mb_info_nmb_t) + MB_SIZE * MB_SIZE
3937 * sizeof(UWORD8));
3938 }
3939 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_INFO_NMB, ps_mem_rec->u4_mem_size);
3940
3941 /************************************************************************
3942 * RC mem records *
3943 ************************************************************************/
3944 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC];
3945 {
3946 ih264e_get_rate_control_mem_tab(NULL, ps_mem_rec, FILL_MEMTAB);
3947 }
3948 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_RC, ps_mem_rec->u4_mem_size);
3949
3950 /* Each memtab size is aligned to next multiple of 128 bytes */
3951 /* This is to ensure all the memtabs start at different cache lines */
3952 ps_mem_rec = ps_mem_rec_base;
3953 for (i = 0; i < MEM_REC_CNT; i++)
3954 {
3955 ps_mem_rec->u4_mem_size = ALIGN128(ps_mem_rec->u4_mem_size);
3956 ps_mem_rec++;
3957 }
3958
3959 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT;
3960
3961 DEBUG("Num mem recs in fill call : %d\n", ps_op->s_ive_op.u4_num_mem_rec);
3962
3963 return (status);
3964 }
3965
3966 /**
3967 *******************************************************************************
3968 *
3969 * @brief
3970 * Initializes from mem records passed to the codec
3971 *
3972 * @par Description:
3973 * Initializes pointers based on mem records passed
3974 *
3975 * @param[in] ps_codec_obj
3976 * Pointer to codec object at API level
3977 *
3978 * @param[in] pv_api_ip
3979 * Pointer to input argument structure
3980 *
3981 * @param[out] pv_api_op
3982 * Pointer to output argument structure
3983 *
3984 * @returns error status
3985 *
3986 * @remarks none
3987 *
3988 *******************************************************************************
3989 */
ih264e_init_mem_rec(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)3990 static WORD32 ih264e_init_mem_rec(iv_obj_t *ps_codec_obj,
3991 void *pv_api_ip,
3992 void *pv_api_op)
3993 {
3994 /* api call I/O structures */
3995 ih264e_init_ip_t *ps_ip = pv_api_ip;
3996 ih264e_init_op_t *ps_op = pv_api_op;
3997
3998 /* mem records */
3999 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
4000
4001 /* codec variables */
4002 codec_t * ps_codec;
4003 cabac_ctxt_t *ps_cabac;
4004 mb_info_ctxt_t *ps_mb_map_ctxt_inc;
4005
4006 cfg_params_t *ps_cfg;
4007
4008 /* frame dimensions */
4009 WORD32 max_wd_luma, max_ht_luma;
4010 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
4011
4012 /* temp var */
4013 WORD32 i, j;
4014 WORD32 status = IV_SUCCESS;
4015
4016 /* frame dimensions */
4017 max_ht_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
4018 max_wd_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
4019 max_mb_rows = max_ht_luma / MB_SIZE;
4020 max_mb_cols = max_wd_luma / MB_SIZE;
4021 max_mb_cnt = max_mb_rows * max_mb_cols;
4022
4023 /* mem records */
4024 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
4025 /* memset all allocated memory, except the first one. First buffer (i.e. i == MEM_REC_IV_OBJ)
4026 is initialized by application before calling this init function */
4027 for (i = MEM_REC_CODEC; i < MEM_REC_CNT; i++)
4028 {
4029 ps_mem_rec = &ps_mem_rec_base[i];
4030 memset(ps_mem_rec->pv_base, 0, ps_mem_rec->u4_mem_size);
4031 }
4032
4033 /* Init mem records */
4034 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
4035 {
4036 ps_codec_obj->pv_codec_handle = ps_mem_rec->pv_base;
4037 ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle);
4038 }
4039 /* Init mem records_cabac ctxt */
4040 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC];
4041 {
4042 ps_cabac = (cabac_ctxt_t *)(ps_mem_rec->pv_base);
4043 }
4044
4045 /* Init mem records mb info array for CABAC */
4046 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO];
4047 {
4048 ps_mb_map_ctxt_inc = (mb_info_ctxt_t *)(ps_mem_rec->pv_base);
4049 }
4050
4051 /* Note this memset can not be done in init() call, since init will called
4052 during reset as well. And calling this during reset will mean all pointers
4053 need to reinitialized */
4054 memset(ps_codec, 0, sizeof(codec_t));
4055 memset(ps_cabac, 0, sizeof(cabac_ctxt_t));
4056
4057 /* Set default Config Params */
4058 ps_cfg = &ps_codec->s_cfg;
4059 ih264e_set_default_params(ps_cfg);
4060
4061 /* Update config params as per input */
4062 ps_cfg->u4_max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
4063 ps_cfg->u4_max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
4064
4065 /* Initialize dimensions to max dimensions during init */
4066 ps_cfg->u4_wd = ps_cfg->u4_disp_wd = ps_cfg->u4_max_wd;
4067 ps_cfg->u4_ht = ps_cfg->u4_disp_ht = ps_cfg->u4_max_ht;
4068
4069 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
4070 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
4071 ps_cfg->u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
4072 ps_cfg->u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt;
4073 ps_cfg->u4_max_level = ps_ip->s_ive_ip.u4_max_level;
4074 ps_cfg->e_inp_color_fmt = ps_ip->s_ive_ip.e_inp_color_fmt;
4075 ps_cfg->e_recon_color_fmt = ps_ip->s_ive_ip.e_recon_color_fmt;
4076 ps_cfg->u4_max_framerate = ps_ip->s_ive_ip.u4_max_framerate;
4077 ps_cfg->u4_max_bitrate = ps_ip->s_ive_ip.u4_max_bitrate;
4078 ps_cfg->u4_num_bframes = ps_ip->s_ive_ip.u4_num_bframes;
4079 ps_cfg->e_content_type = ps_ip->s_ive_ip.e_content_type;
4080 ps_cfg->u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
4081 ps_cfg->u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
4082 ps_cfg->e_slice_mode = ps_ip->s_ive_ip.e_slice_mode;
4083 ps_cfg->u4_slice_param = ps_ip->s_ive_ip.u4_slice_param;
4084 ps_cfg->e_arch = ps_ip->s_ive_ip.e_arch;
4085 ps_cfg->e_soc = ps_ip->s_ive_ip.e_soc;
4086 ps_cfg->u4_enable_recon = ps_ip->s_ive_ip.u4_enable_recon;
4087 ps_cfg->e_rc_mode = ps_ip->s_ive_ip.e_rc_mode;
4088
4089 /* Validate params */
4090 if ((ps_ip->s_ive_ip.u4_max_level < MIN_LEVEL)
4091 || (ps_ip->s_ive_ip.u4_max_level > MAX_LEVEL))
4092 {
4093 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
4094 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
4095 }
4096
4097 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_CNT)
4098 {
4099 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
4100 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
4101 }
4102
4103 if (ps_ip->s_ive_ip.u4_max_reorder_cnt > MAX_REF_CNT)
4104 {
4105 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
4106 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
4107 }
4108
4109 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
4110 {
4111 ps_codec->ps_mem_rec_backup = (iv_mem_rec_t *) ps_mem_rec->pv_base;
4112
4113 memcpy(ps_codec->ps_mem_rec_backup, ps_mem_rec_base,
4114 MEM_REC_CNT * sizeof(iv_mem_rec_t));
4115 }
4116
4117 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY];
4118 {
4119 /* temp var */
4120 WORD32 size = 0, offset;
4121
4122 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4123 {
4124 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4125 {
4126 /* base ptr */
4127 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4128
4129 /* reset size */
4130 size = 0;
4131
4132 /* skip mb run */
4133 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run =
4134 (void *) (pu1_buf + size);
4135 size += sizeof(WORD32);
4136 size = ALIGN8(size);
4137
4138 /* entropy map */
4139 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
4140 (void *) (pu1_buf + size + max_mb_cols);
4141 /* size in bytes to store entropy status of an entire frame */
4142 size += (max_mb_cols * max_mb_rows);
4143 /* add an additional 1 row of bytes to evade the special case of row 0 */
4144 size += max_mb_cols;
4145 size = ALIGN128(size);
4146
4147 /* bit stream ptr */
4148 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf
4149 + size);
4150 size += sizeof(bitstrm_t);
4151 size = ALIGN128(size);
4152
4153 /* nnz luma */
4154 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
4155 (void *) (pu1_buf + size);
4156 size += (max_mb_cols * 4 * sizeof(UWORD8));
4157 size = ALIGN128(size);
4158
4159 /* nnz chroma */
4160 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr =
4161 (void *) (pu1_buf + size);
4162 size += (max_mb_cols * 4 * sizeof(UWORD8));
4163 size = ALIGN128(size);
4164 offset = size;
4165 /* cabac Context */
4166 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
4167 }
4168 else
4169 {
4170 /* base ptr */
4171 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4172
4173 /* reset size */
4174 size = offset;
4175
4176 /* skip mb run */
4177 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run =
4178 (void *) (pu1_buf + size);
4179 size += sizeof(WORD32);
4180 size = ALIGN8(size);
4181
4182 /* entropy map */
4183 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
4184 (void *) (pu1_buf + size + max_mb_cols);
4185 /* size in bytes to store entropy status of an entire frame */
4186 size += (max_mb_cols * max_mb_rows);
4187 /* add an additional 1 row of bytes to evade the special case of row 0 */
4188 size += max_mb_cols;
4189 size = ALIGN128(size);
4190
4191 /* bit stream ptr */
4192 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf
4193 + size);
4194 size += sizeof(bitstrm_t);
4195 size = ALIGN128(size);
4196
4197 /* nnz luma */
4198 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
4199 (void *) (pu1_buf + size);
4200 size += (max_mb_cols * 4 * sizeof(UWORD8));
4201 size = ALIGN128(size);
4202
4203 /* nnz chroma */
4204 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr =
4205 (void *) (pu1_buf + size);
4206 size += (max_mb_cols * 4 * sizeof(UWORD8));
4207 size = ALIGN128(size);
4208 /* cabac Context */
4209 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
4210 }
4211 }
4212 ps_codec->as_process[0].s_entropy.ps_cabac->ps_mb_map_ctxt_inc_base =
4213 ps_mb_map_ctxt_inc;
4214 }
4215
4216 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA];
4217 {
4218 /* temp var */
4219 WORD32 size = 0, size_of_row;
4220 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4221
4222 /* size of coeff data of 1 mb */
4223 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
4224
4225 /* size of coeff data of 1 row of mb's */
4226 size *= max_mb_cols;
4227
4228 /* align to avoid false sharing */
4229 size = ALIGN64(size);
4230 size_of_row = size;
4231
4232 /* size for one full frame */
4233 size *= max_mb_rows;
4234
4235 ps_codec->u4_size_coeff_data = size_of_row;
4236
4237 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4238 {
4239 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4240 {
4241 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf;
4242 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data =
4243 pu1_buf;
4244 }
4245 else
4246 {
4247 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf + size;
4248 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = pu1_buf
4249 + size;
4250 }
4251 }
4252 }
4253
4254 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA];
4255 {
4256 /* temp var */
4257 WORD32 size, size_of_row;
4258 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4259
4260 /* size of header data of 1 mb */
4261 size = sizeof(mb_hdr_t);
4262
4263 /* size for 1 row of mbs */
4264 size = size * max_mb_cols;
4265
4266 /* align to avoid any false sharing across threads */
4267 size = ALIGN64(size);
4268 size_of_row = size;
4269
4270 /* size for one full frame */
4271 size *= max_mb_rows;
4272
4273 ps_codec->u4_size_header_data = size_of_row;
4274
4275 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4276 {
4277 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4278 {
4279 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf;
4280 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data =
4281 pu1_buf;
4282 }
4283 else
4284 {
4285 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf + size;
4286 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data =
4287 pu1_buf + size;
4288 }
4289 }
4290 }
4291
4292 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
4293 {
4294 /* size of buf mgr struct */
4295 WORD32 size = ih264_buf_mgr_size();
4296
4297 /* temp var */
4298 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4299
4300 /* mv buffer mgr */
4301 ps_codec->pv_mv_buf_mgr_base = pu1_buf;
4302
4303 /* mv bank */
4304 ps_codec->pv_mv_bank_buf_base = pu1_buf + size;
4305 ps_codec->i4_total_mv_bank_size = ps_mem_rec->u4_mem_size - size;
4306 }
4307
4308 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS];
4309 {
4310 /* max srch range x */
4311 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
4312
4313 /* max srch range y */
4314 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
4315
4316 /* max srch range */
4317 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
4318
4319 /* temp var */
4320 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4321
4322 /* due to subpel */
4323 u4_max_srch_range <<= 2;
4324
4325 // /* due to mv on either direction */
4326 // u4_max_srch_range = (u4_max_srch_range << 1);
4327
4328 /* due to pred mv + zero */
4329 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
4330
4331 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4332 {
4333 /* me ctxt */
4334 me_ctxt_t *ps_mem_ctxt = &(ps_codec->as_process[i].s_me_ctxt);
4335
4336 /* init at zero mv */
4337 ps_mem_ctxt->pu1_mv_bits = pu1_buf + u4_max_srch_range;
4338 }
4339 }
4340
4341 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INTRA_COST];
4342 {
4343 ps_codec->pi4_mb_intra_cost = ps_mem_rec->pv_base;
4344 }
4345
4346 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
4347 {
4348 ps_codec->ps_sps_base = (sps_t *) ps_mem_rec->pv_base;
4349 }
4350
4351 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
4352 {
4353 ps_codec->ps_pps_base = (pps_t *) ps_mem_rec->pv_base;
4354 }
4355
4356 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
4357 {
4358 ps_codec->ps_slice_hdr_base = ps_mem_rec->pv_base;
4359
4360 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4361 {
4362 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4363 {
4364 ps_codec->as_process[i].ps_slice_hdr_base = ps_mem_rec->pv_base;
4365 }
4366 else
4367 {
4368 /* temp var */
4369 WORD32 size = MAX_SLICE_HDR_CNT * sizeof(slice_header_t);
4370 void *pv_buf = (UWORD8 *) ps_mem_rec->pv_base + size;
4371
4372 ps_codec->as_process[i].ps_slice_hdr_base = pv_buf;
4373 }
4374 }
4375 }
4376
4377 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP];
4378 {
4379 /* temp var */
4380 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4381
4382 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4383 {
4384 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4385 {
4386 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf;
4387 }
4388 else
4389 {
4390 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf
4391 + max_mb_cnt;
4392 }
4393 }
4394
4395 ps_codec->pu2_intr_rfrsh_map = (UWORD16 *) (pu1_buf + max_mb_cnt * MAX_CTXT_SETS);
4396 }
4397
4398 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP];
4399 {
4400 /* pointer to storage space */
4401 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
4402
4403 /* init pointer */
4404 pu1_buf_ping = ps_mem_rec->pv_base;
4405 pu1_buf_pong = pu1_buf_ping + ALIGN64(max_mb_cnt);
4406
4407 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4408 {
4409 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4410 {
4411 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_ping;
4412 }
4413 else
4414 {
4415 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_pong;
4416 }
4417 }
4418 }
4419
4420 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
4421 {
4422 WORD32 handle_size = ithread_get_handle_size();
4423
4424 for (i = 0; i < MAX_PROCESS_THREADS; i++)
4425 {
4426 ps_codec->apv_proc_thread_handle[i] = (UWORD8 *) ps_mem_rec->pv_base
4427 + (i * handle_size);
4428 }
4429 }
4430
4431 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX];
4432 {
4433 ps_codec->pv_ctl_mutex = ps_mem_rec->pv_base;
4434 }
4435
4436 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX];
4437 {
4438 ps_codec->pv_entropy_mutex = ps_mem_rec->pv_base;
4439 }
4440
4441 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
4442 {
4443 ps_codec->pv_proc_jobq_buf = ps_mem_rec->pv_base;
4444 ps_codec->i4_proc_jobq_buf_size = ps_mem_rec->u4_mem_size;
4445 }
4446
4447 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ];
4448 {
4449 ps_codec->pv_entropy_jobq_buf = ps_mem_rec->pv_base;
4450 ps_codec->i4_entropy_jobq_buf_size = ps_mem_rec->u4_mem_size;
4451 }
4452
4453 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
4454 {
4455 /* pointer to storage space */
4456 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4457
4458 /* total size of the mem record */
4459 WORD32 total_size = 0;
4460
4461 /* size in bytes to mb core coding status of an entire frame */
4462 total_size = max_mb_cnt;
4463
4464 /* add an additional 1 row of bytes to evade the special case of row 0 */
4465 total_size += max_mb_cols;
4466
4467 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4468 {
4469 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4470 {
4471 ps_codec->as_process[i].pu1_proc_map = pu1_buf + max_mb_cols;
4472 }
4473 else
4474 {
4475 ps_codec->as_process[i].pu1_proc_map = pu1_buf + total_size
4476 + max_mb_cols;
4477 }
4478 }
4479 }
4480
4481 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP];
4482 {
4483 /* pointer to storage space */
4484 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4485
4486 /* total size of the mem record */
4487 WORD32 total_size = 0;
4488
4489 /* size in bytes to mb core coding status of an entire frame */
4490 total_size = max_mb_cnt;
4491
4492 /* add an additional 1 row of bytes to evade the special case of row 0 */
4493 total_size += max_mb_cols;
4494
4495 /*Align the memory offsets*/
4496 total_size = ALIGN64(total_size);
4497
4498 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4499 {
4500 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4501 {
4502 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + max_mb_cols;
4503
4504 }
4505 else
4506 {
4507 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + total_size
4508 + max_mb_cols;
4509
4510 }
4511 }
4512 }
4513
4514 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP];
4515 {
4516 /* pointer to storage space */
4517 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4518
4519 /* total size of the mem record */
4520 WORD32 total_size = 0;
4521
4522 /* size in bytes to mb core coding status of an entire frame */
4523 total_size = max_mb_cnt;
4524
4525 /* add an additional 1 row of bytes to evade the special case of row 0 */
4526 total_size += max_mb_cols;
4527
4528 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4529 {
4530 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4531 {
4532 ps_codec->as_process[i].pu1_me_map = pu1_buf + max_mb_cols;
4533 }
4534 else
4535 {
4536 ps_codec->as_process[i].pu1_me_map = pu1_buf + total_size
4537 + max_mb_cols;
4538 }
4539 }
4540 }
4541
4542 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
4543 {
4544 ps_codec->pv_dpb_mgr = ps_mem_rec->pv_base;
4545 }
4546
4547 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
4548 {
4549 /* pointer to storage space */
4550 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4551
4552 /* size of pred buffer, fwd transform output, temp buffer for inv tra */
4553 WORD32 size_pred_luma, size_pred_chroma, size_fwd, size_inv, size_hp;
4554
4555 /* temp var */
4556 WORD32 size = 0;
4557
4558 /* size to hold intra/inter prediction buffer */
4559 size_pred_luma = sizeof(UWORD8) * 16 * 16;
4560 size_pred_chroma = sizeof(UWORD8) * 8 * 16;
4561
4562 /* size to hold fwd transform output */
4563 size_fwd = sizeof(WORD16) * SIZE_TRANS_BUFF;
4564
4565 /* size to hold temporary data during inverse transform */
4566 size_inv = sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
4567
4568 /* size to hold half pel plane buffers */
4569 size_hp = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
4570
4571 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4572 {
4573 /* prediction buffer */
4574 ps_codec->as_process[i].pu1_pred_mb = (void *) (pu1_buf + size);
4575 ps_codec->as_process[i].i4_pred_strd = 16;
4576 size += size_pred_luma;
4577 size = ALIGN64(size);
4578
4579 /* prediction buffer */
4580 ps_codec->as_process[i].pu1_ref_mb_intra_4x4 = (void *) (pu1_buf
4581 + size);
4582 size += size_pred_luma;
4583 size = ALIGN64(size);
4584
4585 /* prediction buffer intra 16x16 */
4586 ps_codec->as_process[i].pu1_pred_mb_intra_16x16 = (void *) (pu1_buf
4587 + size);
4588 size += size_pred_luma;
4589 size = ALIGN64(size);
4590
4591 /* prediction buffer intra 16x16 plane*/
4592 ps_codec->as_process[i].pu1_pred_mb_intra_16x16_plane =
4593 (void *) (pu1_buf + size);
4594 size += size_pred_luma;
4595 size = ALIGN64(size);
4596
4597 /* prediction buffer intra chroma*/
4598 ps_codec->as_process[i].pu1_pred_mb_intra_chroma = (void *) (pu1_buf
4599 + size);
4600 size += size_pred_chroma;
4601 size = ALIGN64(size);
4602
4603 /* prediction buffer intra chroma plane*/
4604 ps_codec->as_process[i].pu1_pred_mb_intra_chroma_plane =
4605 (void *) (pu1_buf + size);
4606 size += size_pred_chroma;
4607 size = ALIGN64(size);
4608
4609 /* Fwd transform output */
4610 ps_codec->as_process[i].pi2_res_buf = (void *) (pu1_buf + size);
4611 ps_codec->as_process[i].i4_res_strd = 16;
4612 size += size_fwd;
4613 size = ALIGN64(size);
4614
4615 /* Fwd transform output */
4616 ps_codec->as_process[i].pi2_res_buf_intra_4x4 = (void *) (pu1_buf
4617 + size);
4618 size += size_fwd;
4619 size = ALIGN64(size);
4620
4621 /* scratch buffer used during inverse transform */
4622 ps_codec->as_process[i].pv_scratch_buff = (void *) (pu1_buf + size);
4623 size += size_inv;
4624 size = ALIGN64(size);
4625
4626 for (j = 0; j < SUBPEL_BUFF_CNT; j++)
4627 {
4628 ps_codec->as_process[i].apu1_subpel_buffs[j] = (pu1_buf + size);
4629 size += ALIGN64(size_hp);
4630 }
4631 }
4632 }
4633
4634 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM];
4635 {
4636 /* pointer to storage space */
4637 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4638
4639 /* size of qp, threshold matrix, fwd scaling list for one plane */
4640 WORD32 size_quant_param, size_thres_mat, size_fwd_weight_mat,
4641 size_satqd_weight_mat;
4642
4643 /* temp var */
4644 WORD32 total_size = 0;
4645
4646 /* size of quantization parameter list of 1 plane */
4647 size_quant_param = ALIGN64(sizeof(quant_params_t));
4648
4649 /* size of threshold matrix for quantization
4650 * (assuming the transform_8x8_flag is disabled).
4651 * for 1 plane */
4652 size_thres_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4653
4654 /* size of forward weight matrix for quantization
4655 * (assuming the transform_8x8_flag is disabled).
4656 * for 1 plane */
4657 size_fwd_weight_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4658
4659 /* size of SATQD matrix*/
4660 size_satqd_weight_mat = ALIGN64(sizeof(UWORD16) * 9);
4661
4662 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4663 {
4664 quant_params_t **ps_qp_params = ps_codec->as_process[i].ps_qp_params;
4665
4666 /* quantization param structure */
4667 ps_qp_params[0] = (quant_params_t *) (pu1_buf + total_size);
4668 total_size = total_size + size_quant_param;
4669 ps_qp_params[1] = (quant_params_t *) (pu1_buf + total_size);
4670 total_size = total_size + size_quant_param;
4671 ps_qp_params[2] = (quant_params_t *) (pu1_buf + total_size);
4672 total_size = total_size + size_quant_param;
4673
4674 /* threshold matrix for quantization */
4675 ps_qp_params[0]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4676 total_size = total_size + size_thres_mat;
4677 ps_qp_params[1]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4678 total_size = total_size + size_thres_mat;
4679 ps_qp_params[2]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4680 total_size = total_size + size_thres_mat;
4681
4682 /* fwd weight matrix */
4683 ps_qp_params[0]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4684 total_size = total_size + size_fwd_weight_mat;
4685 ps_qp_params[1]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4686 total_size = total_size + size_fwd_weight_mat;
4687 ps_qp_params[2]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4688 total_size = total_size + size_fwd_weight_mat;
4689
4690 /* threshold matrix for SATQD */
4691 ps_qp_params[0]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4692 total_size = total_size + size_satqd_weight_mat;
4693 ps_qp_params[1]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4694 total_size = total_size + size_satqd_weight_mat;
4695 ps_qp_params[2]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4696 total_size = total_size + size_satqd_weight_mat;
4697
4698 total_size = ALIGN128(total_size);
4699 }
4700 }
4701
4702 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO];
4703 {
4704 /* total size of the mem record */
4705 WORD32 total_size = 0, size_csbp, size_intra_modes, size_mv;
4706
4707 /* pointer to buffer */
4708 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4709
4710 /* size in bytes to store 1 row of mb_info_t */
4711 /* one additional mb, to avoid checking end of row condition */
4712 size_csbp = (max_mb_cols + 1) * sizeof(mb_info_t);
4713
4714 /* size in bytes to store 1 row of intra macroblock sub modes */
4715 size_intra_modes = max_mb_cols * sizeof(UWORD8) * 16;
4716
4717 /* size in bytes to store 1 row + 1 of enc_pu_t */
4718 /* one additional mb, to avoid checking end of row condition */
4719 size_mv = (max_mb_cols + 1) * sizeof(enc_pu_t);
4720
4721 /* total size per proc ctxt */
4722 total_size = size_csbp + size_intra_modes + size_mv;
4723
4724 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4725 {
4726 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4727 {
4728 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base =
4729 (mb_info_t *) pu1_buf;
4730 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf
4731 + size_csbp;
4732 ps_codec->as_process[i].ps_top_row_pu_base =
4733 (enc_pu_t *) (pu1_buf + size_csbp
4734 + size_intra_modes);
4735 }
4736 else
4737 {
4738 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base =
4739 (mb_info_t *) (pu1_buf + total_size);
4740 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf
4741 + total_size + size_csbp;
4742 ps_codec->as_process[i].ps_top_row_pu_base =
4743 (enc_pu_t *) (pu1_buf + total_size + size_csbp
4744 + size_intra_modes);
4745 }
4746 }
4747 }
4748
4749 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
4750 {
4751 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
4752
4753 /* total size of the mem record */
4754 WORD32 total_size = 0;
4755
4756 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/
4757 WORD32 vert_bs_size, horz_bs_size, qp_size;
4758
4759 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */
4760 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
4761 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
4762 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4763
4764 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */
4765 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
4766 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
4767 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4768
4769 /* qp of each mb requires 1 byte */
4770 qp_size = ALIGN64(max_mb_cnt);
4771
4772 /* total size */
4773 total_size = vert_bs_size + horz_bs_size + qp_size;
4774
4775 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4776 {
4777 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4778 {
4779 pu1_buf_ping = (UWORD8 *) ps_mem_rec->pv_base;
4780
4781 /* vertical edge bs storage space */
4782 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4783 (UWORD32 *) pu1_buf_ping;
4784 pu1_buf_ping += vert_bs_size;
4785
4786 /* horizontal edge bs storage space */
4787 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4788 (UWORD32 *) pu1_buf_ping;
4789 pu1_buf_ping += horz_bs_size;
4790
4791 /* qp */
4792 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp =
4793 (UWORD8 *) pu1_buf_ping;
4794 pu1_buf_ping += qp_size;
4795 }
4796 else
4797 {
4798 pu1_buf_pong = (UWORD8 *) ps_mem_rec->pv_base;
4799 pu1_buf_pong += total_size;
4800
4801 /* vertical edge bs storage space */
4802 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4803 (UWORD32 *) pu1_buf_pong;
4804 pu1_buf_pong += vert_bs_size;
4805
4806 /* horizontal edge bs storage space */
4807 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4808 (UWORD32 *) pu1_buf_pong;
4809 pu1_buf_pong += horz_bs_size;
4810
4811 /* qp */
4812 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp =
4813 (UWORD8 *) pu1_buf_pong;
4814 pu1_buf_pong += qp_size;
4815 }
4816 }
4817 }
4818
4819 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC];
4820 {
4821 ps_codec->pv_inp_buf_mgr_base = ps_mem_rec->pv_base;
4822 }
4823
4824 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT];
4825 {
4826 ps_codec->pv_out_buf_mgr_base = ps_mem_rec->pv_base;
4827 }
4828
4829 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC];
4830 {
4831 ps_codec->pu1_y_csc_buf_base = ps_mem_rec->pv_base;
4832 ps_codec->pu1_uv_csc_buf_base = (UWORD8 *) ps_mem_rec->pv_base
4833 + (max_ht_luma * max_wd_luma);
4834 }
4835
4836 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
4837 {
4838 /* size of buf mgr struct */
4839 WORD32 size = ih264_buf_mgr_size();
4840
4841 /* temp var */
4842 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4843
4844 /* pic buffer mgr */
4845 ps_codec->pv_ref_buf_mgr_base = pu1_buf;
4846
4847 /* picture bank */
4848 ps_codec->pv_pic_buf_base = pu1_buf + size;
4849 ps_codec->i4_total_pic_buf_size = ps_mem_rec->u4_mem_size - size;
4850 }
4851
4852 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB];
4853 {
4854 /* temp var */
4855 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4856
4857 /* size of nmb ctxt */
4858 WORD32 size = max_mb_cols * sizeof(mb_info_nmb_t);
4859
4860 WORD32 nmb_cntr, subpel_buf_size;
4861
4862 /* init nmb info structure pointer in all proc ctxts */
4863 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4864 {
4865 ps_codec->as_process[i].ps_nmb_info = (mb_info_nmb_t *) (pu1_buf);
4866
4867 pu1_buf += size;
4868 }
4869
4870 subpel_buf_size = MB_SIZE * MB_SIZE * sizeof(UWORD8);
4871
4872 /* adjusting pointers for nmb halfpel buffer */
4873 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4874 {
4875 mb_info_nmb_t* ps_mb_info_nmb =
4876 &ps_codec->as_process[i].ps_nmb_info[0];
4877
4878 for (nmb_cntr = 0; nmb_cntr < max_mb_cols; nmb_cntr++)
4879 {
4880 ps_mb_info_nmb[nmb_cntr].pu1_best_sub_pel_buf = pu1_buf;
4881
4882 pu1_buf = pu1_buf + subpel_buf_size;
4883
4884 ps_mb_info_nmb[nmb_cntr].u4_bst_spel_buf_strd = MB_SIZE;
4885 }
4886 }
4887 }
4888
4889 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC];
4890 {
4891 ih264e_get_rate_control_mem_tab(&ps_codec->s_rate_control, ps_mem_rec,
4892 USE_BASE);
4893 }
4894
4895 /* init codec ctxt */
4896 status = ih264e_init(ps_codec);
4897
4898 return status;
4899 }
4900
4901 /**
4902 *******************************************************************************
4903 *
4904 * @brief
4905 * Retrieves mem records passed to the codec
4906 *
4907 * @par Description:
4908 * Retrieves mem recs passed during init
4909 *
4910 * @param[in] ps_codec_obj
4911 * Pointer to codec object at API level
4912 *
4913 * @param[in] pv_api_ip
4914 * Pointer to input argument structure
4915 *
4916 * @param[out] pv_api_op
4917 * Pointer to output argument structure
4918 *
4919 * @returns error status
4920 *
4921 * @remarks none
4922 *
4923 *******************************************************************************
4924 */
ih264e_retrieve_memrec(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)4925 static WORD32 ih264e_retrieve_memrec(iv_obj_t *ps_codec_obj,
4926 void *pv_api_ip,
4927 void *pv_api_op)
4928 {
4929 /* codec ctxt */
4930 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
4931
4932 /* ctrl call I/O structures */
4933 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
4934 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op;
4935
4936 if (ps_codec->i4_init_done != 1)
4937 {
4938 ps_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
4939 ps_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
4940 return IV_FAIL;
4941 }
4942
4943 /* join threads upon at end of sequence */
4944 ih264e_join_threads(ps_codec);
4945
4946 /* collect list of memory records used by the encoder library */
4947 memcpy(ps_ip->s_ive_ip.ps_mem_rec, ps_codec->ps_mem_rec_backup,
4948 MEM_REC_CNT * (sizeof(iv_mem_rec_t)));
4949 ps_op->s_ive_op.u4_num_mem_rec_filled = MEM_REC_CNT;
4950
4951 /* clean up mutex memory */
4952 ih264_list_free(ps_codec->pv_entropy_jobq);
4953 ih264_list_free(ps_codec->pv_proc_jobq);
4954 ithread_mutex_destroy(ps_codec->pv_ctl_mutex);
4955 ithread_mutex_destroy(ps_codec->pv_entropy_mutex);
4956
4957
4958 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_mv_buf_mgr);
4959 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_ref_buf_mgr);
4960 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_inp_buf_mgr);
4961 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_out_buf_mgr);
4962
4963 return IV_SUCCESS;
4964 }
4965
4966 /**
4967 *******************************************************************************
4968 *
4969 * @brief
4970 * Sets the encoder in flush mode.
4971 *
4972 * @par Description:
4973 * Sets the encoder in flush mode
4974 *
4975 * @param[in] ps_codec_obj
4976 * Pointer to codec object at API level
4977 *
4978 * @param[in] pv_api_ip
4979 * Pointer to input argument structure
4980 *
4981 * @param[out] pv_api_op
4982 * Pointer to output argument structure
4983 *
4984 * @returns error status
4985 *
4986 * @remarks This call has no real effect on encoder
4987 *
4988 *******************************************************************************
4989 */
ih264e_set_flush_mode(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)4990 static WORD32 ih264e_set_flush_mode(iv_obj_t *ps_codec_obj,
4991 void *pv_api_ip,
4992 void *pv_api_op)
4993 {
4994 /* codec ctxt */
4995 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
4996
4997 /* ctrl call I/O structures */
4998 ih264e_ctl_flush_op_t *ps_ctl_op = pv_api_op;
4999
5000 UNUSED(pv_api_ip);
5001
5002 ps_ctl_op->s_ive_op.u4_error_code = 0;
5003
5004 /* signal flush frame control call */
5005 ps_codec->i4_flush_mode = 1;
5006
5007 return IV_SUCCESS;
5008 }
5009
5010 /**
5011 *******************************************************************************
5012 *
5013 * @brief
5014 * Gets encoder buffer requirements
5015 *
5016 * @par Description:
5017 * Gets the encoder buffer requirements. Basing on max width and max height
5018 * configuration settings, this routine, computes the sizes of necessary input,
5019 * output buffers returns this info to callee.
5020 *
5021 * @param[in] ps_codec_obj
5022 * Pointer to codec object at API level
5023 *
5024 * @param[in] pv_api_ip
5025 * Pointer to input argument structure
5026 *
5027 * @param[out] pv_api_op
5028 * Pointer to output argument structure
5029 *
5030 * @returns error status
5031 *
5032 * @remarks none
5033 *
5034 *******************************************************************************
5035 */
ih264e_get_buf_info(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)5036 static WORD32 ih264e_get_buf_info(iv_obj_t *ps_codec_obj,
5037 void *pv_api_ip,
5038 void *pv_api_op)
5039 {
5040 /* ctrl call I/O structures */
5041 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
5042 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op;
5043
5044 /* temp var */
5045 WORD32 wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
5046 WORD32 ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
5047 WORD32 i;
5048
5049 UNUSED(ps_codec_obj);
5050
5051 ps_op->s_ive_op.u4_error_code = 0;
5052
5053 /* Number of components in input buffers required for codec &
5054 * Minimum sizes of each component in input buffer required */
5055 if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420P)
5056 {
5057 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420_COMP;
5058
5059 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
5060 ps_op->s_ive_op.au4_min_in_buf_size[1] = (wd >> 1) * (ht >> 1);
5061 ps_op->s_ive_op.au4_min_in_buf_size[2] = (wd >> 1) * (ht >> 1);
5062 }
5063 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_422ILE)
5064 {
5065 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_422ILE_COMP;
5066
5067 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
5068 ps_op->s_ive_op.au4_min_in_buf_size[1] =
5069 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5070 }
5071 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGB_565)
5072 {
5073 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGB565_COMP;
5074
5075 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
5076 ps_op->s_ive_op.au4_min_in_buf_size[1] =
5077 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5078 }
5079 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGBA_8888)
5080 {
5081 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGBA8888_COMP;
5082
5083 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 4;
5084 ps_op->s_ive_op.au4_min_in_buf_size[1] =
5085 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5086 }
5087 else if ((ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_UV)
5088 || (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_VU))
5089 {
5090 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420SP_COMP;
5091
5092 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
5093 ps_op->s_ive_op.au4_min_in_buf_size[1] = wd * (ht >> 1);
5094 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5095 }
5096
5097 /* Number of components in output buffers required for codec &
5098 * Minimum sizes of each component in output buffer required */
5099 ps_op->s_ive_op.u4_out_comp_cnt = MIN_BITS_BUFS_COMP;
5100
5101 for (i = 0; i < (WORD32) ps_op->s_ive_op.u4_out_comp_cnt; i++)
5102 {
5103 ps_op->s_ive_op.au4_min_out_buf_size[i] = MAX(((wd * ht * 3) >> 1), MIN_STREAM_SIZE);
5104 }
5105
5106 ps_op->s_ive_op.u4_min_inp_bufs = MIN_INP_BUFS;
5107 ps_op->s_ive_op.u4_min_out_bufs = MIN_OUT_BUFS;
5108
5109 return IV_SUCCESS;
5110 }
5111
5112 /**
5113 *******************************************************************************
5114 *
5115 * @brief
5116 * Sets the picture dimensions
5117 *
5118 * @par Description:
5119 * Sets width, height, display width, display height and strides
5120 *
5121 * @param[in] pv_api_ip
5122 * Pointer to input argument structure
5123 *
5124 * @param[out] pv_api_op
5125 * Pointer to output argument structure
5126 *
5127 * @param[out] ps_cfg
5128 * Pointer to config structure to be updated
5129 *
5130 * @returns error status
5131 *
5132 * @remarks none
5133 *
5134 *******************************************************************************
5135 */
ih264e_set_dimensions(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5136 static IV_STATUS_T ih264e_set_dimensions(void *pv_api_ip,
5137 void *pv_api_op,
5138 cfg_params_t *ps_cfg)
5139 {
5140 /* ctrl call I/O structures */
5141 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
5142 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op;
5143
5144 ps_op->s_ive_op.u4_error_code = 0;
5145
5146 ps_cfg->u4_wd = ALIGN16(ps_ip->s_ive_ip.u4_wd);
5147 ps_cfg->u4_ht = ALIGN16(ps_ip->s_ive_ip.u4_ht);
5148 ps_cfg->i4_wd_mbs = ps_cfg->u4_wd >> 4;
5149 ps_cfg->i4_ht_mbs = ps_cfg->u4_ht >> 4;
5150 ps_cfg->u4_disp_wd = ps_ip->s_ive_ip.u4_wd;
5151 ps_cfg->u4_disp_ht = ps_ip->s_ive_ip.u4_ht;
5152
5153 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5154 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5155
5156 return IV_SUCCESS;
5157 }
5158
5159 /**
5160 *******************************************************************************
5161 *
5162 * @brief
5163 * Sets source and target frame rates
5164 *
5165 * @par Description:
5166 * Sets source and target frame rates
5167 *
5168 * @param[in] pv_api_ip
5169 * Pointer to input argument structure
5170 *
5171 * @param[out] pv_api_op
5172 * Pointer to output argument structure
5173 *
5174 * @param[out] ps_cfg
5175 * Pointer to config structure to be updated
5176 *
5177 * @returns error status
5178 *
5179 * @remarks none
5180 *
5181 *******************************************************************************
5182 */
ih264e_set_frame_rate(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5183 static IV_STATUS_T ih264e_set_frame_rate(void *pv_api_ip,
5184 void *pv_api_op,
5185 cfg_params_t *ps_cfg)
5186 {
5187 /* ctrl call I/O structures */
5188 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
5189 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
5190
5191 ps_op->s_ive_op.u4_error_code = 0;
5192
5193 ps_cfg->u4_src_frame_rate = ps_ip->s_ive_ip.u4_src_frame_rate;
5194 ps_cfg->u4_tgt_frame_rate = ps_ip->s_ive_ip.u4_tgt_frame_rate;
5195
5196 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5197 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5198
5199 return IV_SUCCESS;
5200 }
5201
5202 /**
5203 *******************************************************************************
5204 *
5205 * @brief
5206 * Sets target bit rate
5207 *
5208 * @par Description:
5209 * Sets target bit rate
5210 *
5211 * @param[in] pv_api_ip
5212 * Pointer to input argument structure
5213 *
5214 * @param[out] pv_api_op
5215 * Pointer to output argument structure
5216 *
5217 * @param[out] ps_cfg
5218 * Pointer to config structure to be updated
5219 *
5220 * @returns error status
5221 *
5222 * @remarks none
5223 *
5224 *******************************************************************************
5225 */
ih264e_set_bit_rate(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5226 static IV_STATUS_T ih264e_set_bit_rate(void *pv_api_ip,
5227 void *pv_api_op,
5228 cfg_params_t *ps_cfg)
5229 {
5230 /* ctrl call I/O structures */
5231 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
5232 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op;
5233
5234 ps_op->s_ive_op.u4_error_code = 0;
5235
5236 ps_cfg->u4_target_bitrate = ps_ip->s_ive_ip.u4_target_bitrate;
5237
5238 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5239 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5240
5241 return IV_SUCCESS;
5242 }
5243
5244 /**
5245 *******************************************************************************
5246 *
5247 * @brief
5248 * Sets frame type
5249 *
5250 * @par Description:
5251 * Sets frame type
5252 *
5253 * @param[in] pv_api_ip
5254 * Pointer to input argument structure
5255 *
5256 * @param[out] pv_api_op
5257 * Pointer to output argument structure
5258 *
5259 * @param[out] ps_cfg
5260 * Pointer to config structure to be updated
5261 *
5262 * @returns error status
5263 *
5264 * @remarks not a sticky tag
5265 *
5266 *******************************************************************************
5267 */
ih264e_set_frame_type(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5268 static IV_STATUS_T ih264e_set_frame_type(void *pv_api_ip,
5269 void *pv_api_op,
5270 cfg_params_t *ps_cfg)
5271 {
5272 /* ctrl call I/O structures */
5273 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
5274 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op;
5275
5276 ps_op->s_ive_op.u4_error_code = 0;
5277
5278 ps_cfg->e_frame_type = ps_ip->s_ive_ip.e_frame_type;
5279
5280 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5281 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5282
5283 return IV_SUCCESS;
5284 }
5285
5286 /**
5287 *******************************************************************************
5288 *
5289 * @brief
5290 * Sets quantization params
5291 *
5292 * @par Description:
5293 * Sets the max, min and default qp for I frame, P frame and B frame
5294 *
5295 * @param[in] pv_api_ip
5296 * Pointer to input argument structure
5297 *
5298 * @param[out] pv_api_op
5299 * Pointer to output argument structure
5300 *
5301 * @param[out] ps_cfg
5302 * Pointer to config structure to be updated
5303 *
5304 * @returns error status
5305 *
5306 * @remarks none
5307 *
5308 *******************************************************************************
5309 */
ih264e_set_qp(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5310 static IV_STATUS_T ih264e_set_qp(void *pv_api_ip,
5311 void *pv_api_op,
5312 cfg_params_t *ps_cfg)
5313 {
5314 /* ctrl call I/O structures */
5315 ih264e_ctl_set_qp_ip_t *ps_set_qp_ip = pv_api_ip;
5316 ih264e_ctl_set_qp_op_t *ps_set_qp_op = pv_api_op;
5317
5318 ps_set_qp_op->s_ive_op.u4_error_code = 0;
5319
5320 ps_cfg->u4_i_qp_max = ps_set_qp_ip->s_ive_ip.u4_i_qp_max;
5321 ps_cfg->u4_i_qp_min = ps_set_qp_ip->s_ive_ip.u4_i_qp_min;
5322 ps_cfg->u4_i_qp = ps_set_qp_ip->s_ive_ip.u4_i_qp;
5323 ps_cfg->u4_p_qp_max = ps_set_qp_ip->s_ive_ip.u4_p_qp_max;
5324 ps_cfg->u4_p_qp_min = ps_set_qp_ip->s_ive_ip.u4_p_qp_min;
5325 ps_cfg->u4_p_qp = ps_set_qp_ip->s_ive_ip.u4_p_qp;
5326 ps_cfg->u4_b_qp_max = ps_set_qp_ip->s_ive_ip.u4_b_qp_max;
5327 ps_cfg->u4_b_qp_min = ps_set_qp_ip->s_ive_ip.u4_b_qp_min;
5328 ps_cfg->u4_b_qp = ps_set_qp_ip->s_ive_ip.u4_b_qp;
5329
5330 ps_cfg->u4_timestamp_high = ps_set_qp_ip->s_ive_ip.u4_timestamp_high;
5331 ps_cfg->u4_timestamp_low = ps_set_qp_ip->s_ive_ip.u4_timestamp_low;
5332
5333 return IV_SUCCESS;
5334 }
5335
5336 /**
5337 *******************************************************************************
5338 *
5339 * @brief
5340 * Sets encoding mode
5341 *
5342 * @par Description:
5343 * Sets encoding mode
5344 *
5345 * @param[in] pv_api_ip
5346 * Pointer to input argument structure
5347 *
5348 * @param[out] pv_api_op
5349 * Pointer to output argument structure
5350 *
5351 * @param[out] ps_cfg
5352 * Pointer to config structure to be updated
5353 *
5354 * @returns error status
5355 *
5356 * @remarks none
5357 *
5358 *******************************************************************************
5359 */
ih264e_set_enc_mode(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5360 static IV_STATUS_T ih264e_set_enc_mode(void *pv_api_ip,
5361 void *pv_api_op,
5362 cfg_params_t *ps_cfg)
5363 {
5364 /* ctrl call I/O structures */
5365 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
5366 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
5367
5368 ps_op->s_ive_op.u4_error_code = 0;
5369
5370 ps_cfg->e_enc_mode = ps_ip->s_ive_ip.e_enc_mode;
5371
5372 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5373 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5374
5375 return IV_SUCCESS;
5376 }
5377
5378 /**
5379 *******************************************************************************
5380 *
5381 * @brief
5382 * Sets vbv parameters
5383 *
5384 * @par Description:
5385 * Sets vbv parameters
5386 *
5387 * @param[in] pv_api_ip
5388 * Pointer to input argument structure
5389 *
5390 * @param[out] pv_api_op
5391 * Pointer to output argument structure
5392 *
5393 * @param[out] ps_cfg
5394 * Pointer to config structure to be updated
5395 *
5396 * @returns error status
5397 *
5398 * @remarks none
5399 *
5400 *******************************************************************************
5401 */
ih264e_set_vbv_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5402 static IV_STATUS_T ih264e_set_vbv_params(void *pv_api_ip,
5403 void *pv_api_op,
5404 cfg_params_t *ps_cfg)
5405 {
5406 /* ctrl call I/O structures */
5407 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
5408 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
5409
5410 ps_op->s_ive_op.u4_error_code = 0;
5411
5412 ps_cfg->u4_vbv_buf_size = ps_ip->s_ive_ip.u4_vbv_buf_size;
5413 ps_cfg->u4_vbv_buffer_delay = ps_ip->s_ive_ip.u4_vbv_buffer_delay;
5414
5415 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5416 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5417
5418 return IV_SUCCESS;
5419 }
5420
5421 /**
5422 *******************************************************************************
5423 *
5424 * @brief
5425 * Sets AIR parameters
5426 *
5427 * @par Description:
5428 * Sets AIR parameters
5429 *
5430 * @param[in] pv_api_ip
5431 * Pointer to input argument structure
5432 *
5433 * @param[out] pv_api_op
5434 * Pointer to output argument structure
5435 *
5436 * @param[out] ps_cfg
5437 * Pointer to config structure to be updated
5438 *
5439 * @returns error status
5440 *
5441 * @remarks none
5442 *
5443 *******************************************************************************
5444 */
ih264_set_air_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5445 static IV_STATUS_T ih264_set_air_params(void *pv_api_ip,
5446 void *pv_api_op,
5447 cfg_params_t *ps_cfg)
5448 {
5449 /* ctrl call I/O structures */
5450 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
5451 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op;
5452
5453 ps_op->s_ive_op.u4_error_code = 0;
5454
5455 ps_cfg->e_air_mode = ps_ip->s_ive_ip.e_air_mode;
5456 ps_cfg->u4_air_refresh_period = ps_ip->s_ive_ip.u4_air_refresh_period;
5457
5458 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5459 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5460
5461 return IV_SUCCESS;
5462 }
5463
5464 /**
5465 *******************************************************************************
5466 *
5467 * @brief
5468 * Sets motion estimation parameters
5469 *
5470 * @par Description:
5471 * Sets motion estimation parameters
5472 *
5473 * @param[in] pv_api_ip
5474 * Pointer to input argument structure
5475 *
5476 * @param[out] pv_api_op
5477 * Pointer to output argument structure
5478 *
5479 * @param[out] ps_cfg
5480 * Pointer to config structure to be updated
5481 *
5482 * @returns error status
5483 *
5484 * @remarks none
5485 *
5486 *******************************************************************************
5487 */
ih264_set_me_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5488 static IV_STATUS_T ih264_set_me_params(void *pv_api_ip,
5489 void *pv_api_op,
5490 cfg_params_t *ps_cfg)
5491 {
5492 /* ctrl call I/O structures */
5493 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
5494 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op;
5495
5496 ps_op->s_ive_op.u4_error_code = 0;
5497
5498 ps_cfg->u4_enable_hpel = ps_ip->s_ive_ip.u4_enable_hpel;
5499 ps_cfg->u4_enable_qpel = ps_ip->s_ive_ip.u4_enable_qpel;
5500 ps_cfg->u4_enable_fast_sad = ps_ip->s_ive_ip.u4_enable_fast_sad;
5501 ps_cfg->u4_enable_alt_ref = ps_ip->s_ive_ip.u4_enable_alt_ref;
5502 ps_cfg->u4_srch_rng_x = ps_ip->s_ive_ip.u4_srch_rng_x;
5503 ps_cfg->u4_srch_rng_y = ps_ip->s_ive_ip.u4_srch_rng_y;
5504 ps_cfg->u4_me_speed_preset = ps_ip->s_ive_ip.u4_me_speed_preset;
5505
5506 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5507 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5508
5509 return IV_SUCCESS;
5510 }
5511
5512 /**
5513 *******************************************************************************
5514 *
5515 * @brief
5516 * Sets Intra/Inter Prediction estimation parameters
5517 *
5518 * @par Description:
5519 * Sets Intra/Inter Prediction estimation parameters
5520 *
5521 * @param[in] pv_api_ip
5522 * Pointer to input argument structure
5523 *
5524 * @param[out] pv_api_op
5525 * Pointer to output argument structure
5526 *
5527 * @param[out] ps_cfg
5528 * Pointer to config structure to be updated
5529 *
5530 * @returns error status
5531 *
5532 * @remarks none
5533 *
5534 *******************************************************************************
5535 */
ih264_set_ipe_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5536 static IV_STATUS_T ih264_set_ipe_params(void *pv_api_ip,
5537 void *pv_api_op,
5538 cfg_params_t *ps_cfg)
5539 {
5540 /* ctrl call I/O structures */
5541 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
5542 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
5543
5544 ps_op->s_ive_op.u4_error_code = 0;
5545
5546 ps_cfg->u4_enable_intra_4x4 = ps_ip->s_ive_ip.u4_enable_intra_4x4;
5547 ps_cfg->u4_enc_speed_preset = ps_ip->s_ive_ip.u4_enc_speed_preset;
5548 ps_cfg->u4_constrained_intra_pred = ps_ip->s_ive_ip.u4_constrained_intra_pred;
5549
5550 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5551 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5552
5553 return IV_SUCCESS;
5554 }
5555
5556 /**
5557 *******************************************************************************
5558 *
5559 * @brief
5560 * Sets GOP parameters
5561 *
5562 * @par Description:
5563 * Sets GOP parameters
5564 *
5565 * @param[in] pv_api_ip
5566 * Pointer to input argument structure
5567 *
5568 * @param[out] pv_api_op
5569 * Pointer to output argument structure
5570 *
5571 * @param[out] ps_cfg
5572 * Pointer to config structure to be updated
5573 *
5574 * @returns error status
5575 *
5576 * @remarks none
5577 *
5578 *******************************************************************************
5579 */
ih264_set_gop_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5580 static IV_STATUS_T ih264_set_gop_params(void *pv_api_ip,
5581 void *pv_api_op,
5582 cfg_params_t *ps_cfg)
5583 {
5584 /* ctrl call I/O structures */
5585 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
5586 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op;
5587
5588 ps_op->s_ive_op.u4_error_code = 0;
5589
5590 ps_cfg->u4_i_frm_interval = ps_ip->s_ive_ip.u4_i_frm_interval;
5591 ps_cfg->u4_idr_frm_interval = ps_ip->s_ive_ip.u4_idr_frm_interval;
5592 if (ps_cfg->u4_idr_frm_interval < ps_cfg->u4_i_frm_interval)
5593 ps_cfg->u4_i_frm_interval = ps_cfg->u4_idr_frm_interval;
5594
5595 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5596 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5597
5598 return IV_SUCCESS;
5599 }
5600
5601 /**
5602 *******************************************************************************
5603 *
5604 * @brief
5605 * Sets profile parameters
5606 *
5607 * @par Description:
5608 * Sets profile parameters
5609 *
5610 * @param[in] pv_api_ip
5611 * Pointer to input argument structure
5612 *
5613 * @param[out] pv_api_op
5614 * Pointer to output argument structure
5615 *
5616 * @param[out] ps_cfg
5617 * Pointer to config structure to be updated
5618 *
5619 * @returns error status
5620 *
5621 * @remarks none
5622 *
5623 *******************************************************************************
5624 */
ih264_set_profile_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5625 static IV_STATUS_T ih264_set_profile_params(void *pv_api_ip,
5626 void *pv_api_op,
5627 cfg_params_t *ps_cfg)
5628 {
5629 /* ctrl call I/O structures */
5630 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
5631 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op;
5632
5633 ps_op->s_ive_op.u4_error_code = 0;
5634
5635 ps_cfg->e_profile = ps_ip->s_ive_ip.e_profile;
5636 ps_cfg->u4_entropy_coding_mode = ps_ip->s_ive_ip.u4_entropy_coding_mode;
5637
5638 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5639 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5640
5641 return IV_SUCCESS;
5642 }
5643
5644 /**
5645 *******************************************************************************
5646 *
5647 * @brief
5648 * Sets disable deblock level
5649 *
5650 * @par Description:
5651 * Sets disable deblock level. Level 0 means no disabling and level 4 means
5652 * disable completely. 1, 2, 3 are intermediate levels that control amount
5653 * of deblocking done.
5654 *
5655 * @param[in] ps_codec_obj
5656 * Pointer to codec object at API level
5657 *
5658 * @param[in] pv_api_ip
5659 * Pointer to input argument structure
5660 *
5661 * @param[out] pv_api_op
5662 * Pointer to output argument structure
5663 *
5664 * @returns error status
5665 *
5666 * @remarks none
5667 *
5668 *******************************************************************************
5669 */
ih264_set_deblock_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5670 static WORD32 ih264_set_deblock_params(void *pv_api_ip,
5671 void *pv_api_op,
5672 cfg_params_t *ps_cfg)
5673 {
5674 /* ctrl call I/O structures */
5675 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
5676 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
5677
5678 ps_op->s_ive_op.u4_error_code = 0;
5679
5680 ps_cfg->u4_disable_deblock_level = ps_ip->s_ive_ip.u4_disable_deblock_level;
5681
5682 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5683 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5684
5685 return IV_SUCCESS;
5686 }
5687 /**
5688 *******************************************************************************
5689 *
5690 * @brief
5691 * Sets vui params
5692 *
5693 * @par Description:
5694 * Video usability information
5695 *
5696 * @param[in] pv_api_ip
5697 * Pointer to input argument structure
5698 *
5699 * @param[out] pv_api_op
5700 * Pointer to output argument structure
5701 *
5702 * @param[out] ps_cfg
5703 * Pointer to config structure to be updated
5704 *
5705 * @returns error status
5706 *
5707 * @remarks none
5708 *
5709 *******************************************************************************
5710 */
ih264e_set_vui_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5711 static WORD32 ih264e_set_vui_params(void *pv_api_ip,
5712 void *pv_api_op,
5713 cfg_params_t *ps_cfg)
5714 {
5715 /* ctrl call I/O structures */
5716 ih264e_vui_ip_t *ps_ip = pv_api_ip;
5717 ih264e_vui_op_t *ps_op = pv_api_op;
5718 vui_t *ps_vui = &ps_cfg->s_vui;
5719
5720 ps_op->u4_error_code = 0;
5721
5722 ps_vui->u1_aspect_ratio_info_present_flag = ps_ip->u1_aspect_ratio_info_present_flag;
5723 ps_vui->u1_aspect_ratio_idc = ps_ip->u1_aspect_ratio_idc;
5724 ps_vui->u2_sar_width = ps_ip->u2_sar_width;
5725 ps_vui->u2_sar_height = ps_ip->u2_sar_height;
5726 ps_vui->u1_overscan_info_present_flag = ps_ip->u1_overscan_info_present_flag;
5727 ps_vui->u1_overscan_appropriate_flag = ps_ip->u1_overscan_appropriate_flag;
5728 ps_vui->u1_video_signal_type_present_flag = ps_ip->u1_video_signal_type_present_flag;
5729 ps_vui->u1_video_format = ps_ip->u1_video_format;
5730 ps_vui->u1_video_full_range_flag = ps_ip->u1_video_full_range_flag;
5731 ps_vui->u1_colour_description_present_flag = ps_ip->u1_colour_description_present_flag;
5732 ps_vui->u1_colour_primaries = ps_ip->u1_colour_primaries;
5733 ps_vui->u1_transfer_characteristics = ps_ip->u1_transfer_characteristics;
5734 ps_vui->u1_matrix_coefficients = ps_ip->u1_matrix_coefficients;
5735 ps_vui->u1_chroma_loc_info_present_flag = ps_ip->u1_chroma_loc_info_present_flag;
5736 ps_vui->u1_chroma_sample_loc_type_top_field = ps_ip->u1_chroma_sample_loc_type_top_field;
5737 ps_vui->u1_chroma_sample_loc_type_bottom_field = ps_ip->u1_chroma_sample_loc_type_bottom_field;
5738 ps_vui->u1_vui_timing_info_present_flag = ps_ip->u1_vui_timing_info_present_flag;
5739 ps_vui->u4_vui_num_units_in_tick = ps_ip->u4_vui_num_units_in_tick;
5740 ps_vui->u4_vui_time_scale = ps_ip->u4_vui_time_scale;
5741 ps_vui->u1_fixed_frame_rate_flag = ps_ip->u1_fixed_frame_rate_flag;
5742 ps_vui->u1_nal_hrd_parameters_present_flag = ps_ip->u1_nal_hrd_parameters_present_flag;
5743 ps_vui->u1_vcl_hrd_parameters_present_flag = ps_ip->u1_vcl_hrd_parameters_present_flag;
5744 ps_vui->u1_low_delay_hrd_flag = ps_ip->u1_low_delay_hrd_flag;
5745 ps_vui->u1_pic_struct_present_flag = ps_ip->u1_pic_struct_present_flag;
5746 ps_vui->u1_bitstream_restriction_flag = ps_ip->u1_bitstream_restriction_flag;
5747 ps_vui->u1_motion_vectors_over_pic_boundaries_flag = ps_ip->u1_motion_vectors_over_pic_boundaries_flag;
5748 ps_vui->u1_max_bytes_per_pic_denom = ps_ip->u1_max_bytes_per_pic_denom;
5749 ps_vui->u1_max_bits_per_mb_denom = ps_ip->u1_max_bits_per_mb_denom;
5750 ps_vui->u1_log2_max_mv_length_horizontal = ps_ip->u1_log2_max_mv_length_horizontal;
5751 ps_vui->u1_log2_max_mv_length_vertical = ps_ip->u1_log2_max_mv_length_vertical;
5752 ps_vui->u1_num_reorder_frames = ps_ip->u1_num_reorder_frames;
5753 ps_vui->u1_max_dec_frame_buffering = ps_ip->u1_max_dec_frame_buffering;
5754
5755 ps_cfg->u4_timestamp_high = -1;
5756 ps_cfg->u4_timestamp_low = -1;
5757
5758 return IV_SUCCESS;
5759 }
5760
5761 /**
5762 *******************************************************************************
5763 *
5764 * @brief
5765 * Sets Mastering display color volume sei params
5766 *
5767 * @par Description:
5768 * Supplemental enhancement information
5769 *
5770 * @param[in] pv_api_ip
5771 * Pointer to input argument structure
5772 *
5773 * @param[out] pv_api_op
5774 * Pointer to output argument structure
5775 *
5776 * @param[out] ps_cfg
5777 * Pointer to config structure to be updated
5778 *
5779 * @return error status
5780 *
5781 * @remarks none
5782 *
5783 *******************************************************************************
5784 */
ih264e_set_sei_mdcv_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5785 static WORD32 ih264e_set_sei_mdcv_params(void *pv_api_ip,
5786 void *pv_api_op,
5787 cfg_params_t *ps_cfg)
5788 {
5789 WORD32 i4_count;
5790 /* ctrl call I/O structures */
5791 ih264e_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip;
5792 ih264e_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op;
5793 sei_params_t *ps_sei = &ps_cfg->s_sei;
5794
5795 ps_op->u4_error_code = 0;
5796
5797 ps_sei->u1_sei_mdcv_params_present_flag = ps_ip->u1_sei_mdcv_params_present_flag;
5798 for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++)
5799 {
5800 ps_sei->s_sei_mdcv_params.au2_display_primaries_x[i4_count] =
5801 ps_ip->au2_display_primaries_x[i4_count];
5802 ps_sei->s_sei_mdcv_params.au2_display_primaries_y[i4_count] =
5803 ps_ip->au2_display_primaries_y[i4_count];
5804 }
5805
5806 ps_sei->s_sei_mdcv_params.u2_white_point_x = ps_ip->u2_white_point_x;
5807 ps_sei->s_sei_mdcv_params.u2_white_point_y = ps_ip->u2_white_point_y;
5808 ps_sei->s_sei_mdcv_params.u4_max_display_mastering_luminance =
5809 ps_ip->u4_max_display_mastering_luminance;
5810 ps_sei->s_sei_mdcv_params.u4_min_display_mastering_luminance =
5811 ps_ip->u4_min_display_mastering_luminance;
5812
5813 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5814 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5815
5816 return IV_SUCCESS;
5817 }
5818
5819 /**
5820 *******************************************************************************
5821 *
5822 * @brief
5823 * Sets content light level sei params
5824 *
5825 * @par Description:
5826 * Supplemental enhancement information
5827 *
5828 * @param[in] pv_api_ip
5829 * Pointer to input argument structure
5830 *
5831 * @param[out] pv_api_op
5832 * Pointer to output argument structure
5833 *
5834 * @param[out] ps_cfg
5835 * Pointer to config structure to be updated
5836 *
5837 * @return error status
5838 *
5839 * @remarks none
5840 *
5841 *******************************************************************************
5842 */
ih264e_set_sei_cll_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5843 static WORD32 ih264e_set_sei_cll_params(void *pv_api_ip,
5844 void *pv_api_op,
5845 cfg_params_t *ps_cfg)
5846 {
5847 /* ctrl call I/O structures */
5848 ih264e_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip;
5849 ih264e_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op;
5850 sei_params_t *ps_sei = &ps_cfg->s_sei;
5851
5852 ps_op->u4_error_code = 0;
5853
5854 ps_sei->u1_sei_cll_params_present_flag = ps_ip->u1_sei_cll_params_present_flag;
5855
5856 ps_sei->s_sei_cll_params.u2_max_content_light_level = ps_ip->u2_max_content_light_level;
5857 ps_sei->s_sei_cll_params.u2_max_pic_average_light_level =
5858 ps_ip->u2_max_pic_average_light_level;
5859
5860 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5861 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5862
5863 return IV_SUCCESS;
5864 }
5865
5866 /**
5867 *******************************************************************************
5868 *
5869 * @brief
5870 * Sets ambient viewing environment sei params
5871 *
5872 * @par Description:
5873 * Supplemental enhancement information
5874 *
5875 * @param[in] pv_api_ip
5876 * Pointer to input argument structure
5877 *
5878 * @param[out] pv_api_op
5879 * Pointer to output argument structure
5880 *
5881 * @param[out] ps_cfg
5882 * Pointer to config structure to be updated
5883 *
5884 * @return error status
5885 *
5886 * @remarks none
5887 *
5888 *******************************************************************************
5889 */
ih264e_set_sei_ave_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5890 static WORD32 ih264e_set_sei_ave_params(void *pv_api_ip,
5891 void *pv_api_op,
5892 cfg_params_t *ps_cfg)
5893 {
5894 /* ctrl call I/O structures */
5895 ih264e_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip;
5896 ih264e_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op;
5897 sei_params_t *ps_sei = &ps_cfg->s_sei;
5898
5899 ps_op->u4_error_code = 0;
5900
5901 ps_sei->u1_sei_ave_params_present_flag = ps_ip->u1_sei_ave_params_present_flag;
5902
5903 ps_sei->s_sei_ave_params.u4_ambient_illuminance = ps_ip->u4_ambient_illuminance;
5904 ps_sei->s_sei_ave_params.u2_ambient_light_x = ps_ip->u2_ambient_light_x;
5905 ps_sei->s_sei_ave_params.u2_ambient_light_y = ps_ip->u2_ambient_light_y;
5906
5907 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5908 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5909
5910 return IV_SUCCESS;
5911 }
5912
5913 /**
5914 *******************************************************************************
5915 *
5916 * @brief
5917 * Sets content color volume sei params
5918 *
5919 * @par Description:
5920 * Supplemental enhancement information
5921 *
5922 * @param[in] pv_api_ip
5923 * Pointer to input argument structure
5924 *
5925 * @param[out] pv_api_op
5926 * Pointer to output argument structure
5927 *
5928 * @param[out] ps_cfg
5929 * Pointer to config structure to be updated
5930 *
5931 * @return error status
5932 *
5933 * @remarks none
5934 *
5935 *******************************************************************************
5936 */
ih264e_set_sei_ccv_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5937 static WORD32 ih264e_set_sei_ccv_params(void *pv_api_ip,
5938 void *pv_api_op,
5939 cfg_params_t *ps_cfg)
5940 {
5941 WORD32 i4_count;
5942 /* ctrl call I/O structures */
5943 ih264e_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip;
5944 ih264e_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op;
5945 sei_params_t *ps_sei = &ps_cfg->s_sei;
5946
5947 ps_op->u4_error_code = 0;
5948
5949 ps_sei->u1_sei_ccv_params_present_flag = ps_ip->u1_sei_ccv_params_present_flag;
5950
5951 ps_sei->s_sei_ccv_params.u1_ccv_cancel_flag = ps_ip->u1_ccv_cancel_flag;
5952 ps_sei->s_sei_ccv_params.u1_ccv_persistence_flag = ps_ip->u1_ccv_persistence_flag;
5953 ps_sei->s_sei_ccv_params.u1_ccv_primaries_present_flag =
5954 ps_ip->u1_ccv_primaries_present_flag;
5955 ps_sei->s_sei_ccv_params.u1_ccv_min_luminance_value_present_flag =
5956 ps_ip->u1_ccv_min_luminance_value_present_flag;
5957 ps_sei->s_sei_ccv_params.u1_ccv_max_luminance_value_present_flag =
5958 ps_ip->u1_ccv_max_luminance_value_present_flag;
5959 ps_sei->s_sei_ccv_params.u1_ccv_avg_luminance_value_present_flag =
5960 ps_ip->u1_ccv_avg_luminance_value_present_flag;
5961 ps_sei->s_sei_ccv_params.u1_ccv_reserved_zero_2bits =
5962 ps_ip->u1_ccv_reserved_zero_2bits;
5963
5964 for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++)
5965 {
5966 ps_sei->s_sei_ccv_params.ai4_ccv_primaries_x[i4_count] =
5967 ps_ip->ai4_ccv_primaries_x[i4_count];
5968 ps_sei->s_sei_ccv_params.ai4_ccv_primaries_y[i4_count] =
5969 ps_ip->ai4_ccv_primaries_y[i4_count];
5970 }
5971
5972 ps_sei->s_sei_ccv_params.u4_ccv_min_luminance_value = ps_ip->u4_ccv_min_luminance_value;
5973 ps_sei->s_sei_ccv_params.u4_ccv_max_luminance_value = ps_ip->u4_ccv_max_luminance_value;
5974 ps_sei->s_sei_ccv_params.u4_ccv_avg_luminance_value = ps_ip->u4_ccv_avg_luminance_value;
5975
5976 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5977 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5978
5979 return IV_SUCCESS;
5980 }
5981
5982 /**
5983 *******************************************************************************
5984 *
5985 * @brief
5986 * Sets shutter interval info sei params
5987 *
5988 * @par Description:
5989 * Supplemental enhancement information
5990 *
5991 * @param[in] pv_api_ip
5992 * Pointer to input argument structure
5993 *
5994 * @param[out] pv_api_op
5995 * Pointer to output argument structure
5996 *
5997 * @param[out] ps_cfg
5998 * Pointer to config structure to be updated
5999 *
6000 * @return error status
6001 *
6002 * @remarks none
6003 *
6004 *******************************************************************************
6005 */
ih264e_set_sei_sii_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)6006 static WORD32 ih264e_set_sei_sii_params(void *pv_api_ip, void *pv_api_op, cfg_params_t *ps_cfg)
6007 {
6008 /* ctrl call I/O structures */
6009 ih264e_ctl_set_sei_sii_params_ip_t *ps_ip = pv_api_ip;
6010 ih264e_ctl_set_sei_sii_params_op_t *ps_op = pv_api_op;
6011 sei_params_t *ps_sei = &ps_cfg->s_sei;
6012
6013 ps_op->u4_error_code = 0;
6014 ps_sei->u1_sei_sii_params_present_flag = ps_ip->u1_shutter_interval_info_present_flag;
6015 ps_sei->s_sei_sii_params.u4_sii_sub_layer_idx = ps_ip->u4_sii_sub_layer_idx;
6016
6017 if(0 == ps_sei->s_sei_sii_params.u4_sii_sub_layer_idx)
6018 {
6019 ps_sei->s_sei_sii_params.u1_shutter_interval_info_present_flag =
6020 ps_ip->u1_shutter_interval_info_present_flag;
6021
6022 if(1 == ps_sei->s_sei_sii_params.u1_shutter_interval_info_present_flag)
6023 {
6024 ps_sei->s_sei_sii_params.u4_sii_time_scale = ps_ip->u4_sii_time_scale;
6025 ps_sei->s_sei_sii_params.u1_fixed_shutter_interval_within_cvs_flag =
6026 ps_ip->u1_fixed_shutter_interval_within_cvs_flag;
6027
6028 if(1 == ps_sei->s_sei_sii_params.u1_fixed_shutter_interval_within_cvs_flag)
6029 {
6030 ps_sei->s_sei_sii_params.u4_sii_num_units_in_shutter_interval =
6031 ps_ip->u4_sii_num_units_in_shutter_interval;
6032 }
6033 else
6034 {
6035 int i;
6036 ps_sei->s_sei_sii_params.u1_sii_max_sub_layers_minus1 =
6037 ps_ip->u1_sii_max_sub_layers_minus1;
6038
6039 for(i = 0; i <= ps_ip->u1_sii_max_sub_layers_minus1; i++)
6040 {
6041 ps_sei->s_sei_sii_params.au4_sub_layer_num_units_in_shutter_interval[i] =
6042 ps_ip->au4_sub_layer_num_units_in_shutter_interval[i];
6043 }
6044 }
6045 }
6046 }
6047
6048 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
6049 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
6050
6051 return IV_SUCCESS;
6052 }
6053
6054 /**
6055 *******************************************************************************
6056 *
6057 * @brief
6058 * Sets number of cores
6059 *
6060 * @par Description:
6061 * Sets number of cores
6062 *
6063 * @param[in] ps_codec_obj
6064 * Pointer to codec object at API level
6065 *
6066 * @param[in] pv_api_ip
6067 * Pointer to input argument structure
6068 *
6069 * @param[out] pv_api_op
6070 * Pointer to output argument structure
6071 *
6072 * @returns error status
6073 *
6074 * @remarks The number of encoder threads is limited to MAX_PROCESS_THREADS
6075 *
6076 *******************************************************************************
6077 */
ih264e_set_num_cores(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)6078 static WORD32 ih264e_set_num_cores(void *pv_api_ip,
6079 void *pv_api_op,
6080 cfg_params_t *ps_cfg)
6081 {
6082 /* ctrl call I/O structures */
6083 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
6084 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op;
6085
6086 ps_op->s_ive_op.u4_error_code = 0;
6087
6088 ps_cfg->u4_num_cores = MIN(ps_ip->s_ive_ip.u4_num_cores, MAX_PROCESS_THREADS);
6089
6090 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
6091 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
6092
6093 return IV_SUCCESS;
6094 }
6095
6096 /**
6097 *******************************************************************************
6098 *
6099 * @brief
6100 * Resets encoder state
6101 *
6102 * @par Description:
6103 * Resets encoder state by calling ih264e_init()
6104 *
6105 * @param[in] ps_codec_obj
6106 * Pointer to codec object at API level
6107 *
6108 * @param[in] pv_api_ip
6109 * Pointer to input argument structure
6110 *
6111 * @param[out] pv_api_op
6112 * Pointer to output argument structure
6113 *
6114 * @returns error status
6115 *
6116 * @remarks none
6117 *
6118 *******************************************************************************
6119 */
ih264e_reset(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)6120 static WORD32 ih264e_reset(iv_obj_t *ps_codec_obj,
6121 void *pv_api_ip,
6122 void *pv_api_op)
6123 {
6124 /* codec ctxt */
6125 codec_t * ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle);
6126
6127 /* ctrl call I/O structures */
6128 ih264e_ctl_reset_op_t *ps_op = pv_api_op;
6129
6130 UNUSED(pv_api_ip);
6131
6132 ps_op->s_ive_op.u4_error_code = 0;
6133
6134 if (ps_codec != NULL)
6135 {
6136 ih264e_init(ps_codec);
6137 }
6138 else
6139 {
6140 ps_op->s_ive_op.u4_error_code = IH264E_INIT_NOT_DONE;
6141 }
6142
6143 return IV_SUCCESS;
6144 }
6145
6146 /**
6147 *******************************************************************************
6148 *
6149 * @brief
6150 * Codec control call
6151 *
6152 * @par Description:
6153 * Codec control call which in turn calls appropriate calls based on sub-command
6154 *
6155 * @param[in] ps_codec_obj
6156 * Pointer to codec object at API level
6157 *
6158 * @param[in] pv_api_ip
6159 * Pointer to input argument structure
6160 *
6161 * @param[out] pv_api_op
6162 * Pointer to output argument structure
6163 *
6164 * @returns error status
6165 *
6166 * @remarks none
6167 *
6168 *******************************************************************************
6169 */
ih264e_ctl(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)6170 static WORD32 ih264e_ctl(iv_obj_t *ps_codec_obj,
6171 void *pv_api_ip,
6172 void *pv_api_op)
6173 {
6174 /* codec ctxt */
6175 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
6176
6177 /* ctrl call I/O structures */
6178 ih264e_ctl_setdefault_ip_t *ps_ctl_ip = pv_api_ip;
6179 ih264e_ctl_setdefault_op_t *ps_ctl_op = pv_api_op;
6180
6181 /* ctrl call sub cmd */
6182 IVE_CONTROL_API_COMMAND_TYPE_T sub_cmd = ps_ctl_ip->s_ive_ip.e_sub_cmd;
6183
6184 /* error status */
6185 IV_STATUS_T ret = IV_SUCCESS;
6186
6187 /* temp var */
6188 WORD32 i;
6189 cfg_params_t *ps_cfg = NULL;
6190
6191 /* control call is for configuring encoding params, this is not to be called
6192 * before a successful init call */
6193 if (ps_codec->i4_init_done != 1)
6194 {
6195 ps_ctl_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
6196 ps_ctl_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
6197 return IV_FAIL;
6198 }
6199
6200 /* make it thread safe */
6201 ithread_mutex_lock(ps_codec->pv_ctl_mutex);
6202
6203 /* find a free config param set to hold current parameters */
6204 for (i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++)
6205 {
6206 if (0 == ps_codec->as_cfg[i].u4_is_valid)
6207 {
6208 ps_cfg = &ps_codec->as_cfg[i];
6209 break;
6210 }
6211 }
6212
6213 /* If all are invalid, then start overwriting from the head config params */
6214 if (NULL == ps_cfg)
6215 {
6216 ps_cfg = &ps_codec->as_cfg[0];
6217 }
6218
6219 ps_cfg->u4_is_valid = 1;
6220
6221 ps_cfg->e_cmd = sub_cmd;
6222
6223 switch (sub_cmd)
6224 {
6225 case IVE_CMD_CTL_SET_DIMENSIONS:
6226 ret = ih264e_set_dimensions(pv_api_ip, pv_api_op, ps_cfg);
6227 break;
6228
6229 case IVE_CMD_CTL_SET_FRAMERATE:
6230 ret = ih264e_set_frame_rate(pv_api_ip, pv_api_op, ps_cfg);
6231 break;
6232
6233 case IVE_CMD_CTL_SET_BITRATE:
6234 ret = ih264e_set_bit_rate(pv_api_ip, pv_api_op, ps_cfg);
6235 break;
6236
6237 case IVE_CMD_CTL_SET_FRAMETYPE:
6238 ret = ih264e_set_frame_type(pv_api_ip, pv_api_op, ps_cfg);
6239 break;
6240
6241 case IVE_CMD_CTL_SET_QP:
6242 ret = ih264e_set_qp(pv_api_ip, pv_api_op, ps_cfg);
6243 break;
6244
6245 case IVE_CMD_CTL_SET_ENC_MODE:
6246 ret = ih264e_set_enc_mode(pv_api_ip, pv_api_op, ps_cfg);
6247 break;
6248
6249 case IVE_CMD_CTL_SET_VBV_PARAMS:
6250 ret = ih264e_set_vbv_params(pv_api_ip, pv_api_op, ps_cfg);
6251 break;
6252
6253 case IVE_CMD_CTL_SET_AIR_PARAMS:
6254 ret = ih264_set_air_params(pv_api_ip, pv_api_op, ps_cfg);
6255 break;
6256
6257 case IVE_CMD_CTL_SET_ME_PARAMS:
6258 ret = ih264_set_me_params(pv_api_ip, pv_api_op, ps_cfg);
6259 break;
6260
6261 case IVE_CMD_CTL_SET_IPE_PARAMS:
6262 ret = ih264_set_ipe_params(pv_api_ip, pv_api_op, ps_cfg);
6263 break;
6264
6265 case IVE_CMD_CTL_SET_GOP_PARAMS:
6266 ret = ih264_set_gop_params(pv_api_ip, pv_api_op, ps_cfg);
6267 break;
6268
6269 case IVE_CMD_CTL_SET_PROFILE_PARAMS:
6270 ret = ih264_set_profile_params(pv_api_ip, pv_api_op, ps_cfg);
6271 break;
6272
6273 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS:
6274 ret = ih264_set_deblock_params(pv_api_ip, pv_api_op, ps_cfg);
6275 break;
6276
6277 case IVE_CMD_CTL_SET_VUI_PARAMS:
6278 ret = ih264e_set_vui_params(pv_api_ip, pv_api_op, ps_cfg);
6279 break;
6280
6281 case IVE_CMD_CTL_SET_SEI_MDCV_PARAMS:
6282 ret = ih264e_set_sei_mdcv_params(pv_api_ip, pv_api_op, ps_cfg);
6283 break;
6284
6285 case IVE_CMD_CTL_SET_SEI_CLL_PARAMS:
6286 ret = ih264e_set_sei_cll_params(pv_api_ip, pv_api_op, ps_cfg);
6287 break;
6288
6289 case IVE_CMD_CTL_SET_SEI_AVE_PARAMS:
6290 ret = ih264e_set_sei_ave_params(pv_api_ip, pv_api_op, ps_cfg);
6291 break;
6292
6293 case IVE_CMD_CTL_SET_SEI_CCV_PARAMS:
6294 ret = ih264e_set_sei_ccv_params(pv_api_ip, pv_api_op, ps_cfg);
6295 break;
6296
6297 case IVE_CMD_CTL_SET_SEI_SII_PARAMS:
6298 ret = ih264e_set_sei_sii_params(pv_api_ip, pv_api_op, ps_cfg);
6299 break;
6300
6301 case IVE_CMD_CTL_RESET:
6302
6303 /* invalidate config param struct as it is being served right away */
6304 ps_codec->as_cfg[i].u4_is_valid = 0;
6305
6306 ret = ih264e_reset(ps_codec_obj, pv_api_ip, pv_api_op);
6307 break;
6308
6309 case IVE_CMD_CTL_SETDEFAULT:
6310 {
6311 /* ctrl call I/O structures */
6312 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op;
6313
6314 /* invalidate config param struct as it is being served right away */
6315 ps_codec->as_cfg[i].u4_is_valid = 0;
6316
6317 /* error status */
6318 ret = ih264e_set_default_params(ps_cfg);
6319
6320 ps_op->s_ive_op.u4_error_code = ret;
6321
6322 break;
6323 }
6324
6325 case IVE_CMD_CTL_FLUSH:
6326
6327 /* invalidate config param struct as it is being served right away */
6328 ps_codec->as_cfg[i].u4_is_valid = 0;
6329
6330 ret = ih264e_set_flush_mode(ps_codec_obj, pv_api_ip, pv_api_op);
6331 break;
6332
6333 case IVE_CMD_CTL_GETBUFINFO:
6334
6335 /* invalidate config param struct as it is being served right away */
6336 ps_codec->as_cfg[i].u4_is_valid = 0;
6337
6338 ret = ih264e_get_buf_info(ps_codec_obj, pv_api_ip, pv_api_op);
6339 break;
6340
6341 case IVE_CMD_CTL_GETVERSION:
6342 {
6343 /* ctrl call I/O structures */
6344 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
6345 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op;
6346
6347 /* invalidate config param struct as it is being served right away */
6348 ps_codec->as_cfg[i].u4_is_valid = 0;
6349
6350 /* error status */
6351 ps_op->s_ive_op.u4_error_code = IV_SUCCESS;
6352
6353 if (ps_ip->s_ive_ip.u4_version_bufsize <= 0)
6354 {
6355 ps_op->s_ive_op.u4_error_code =
6356 IH264E_CXA_VERS_BUF_INSUFFICIENT;
6357 ret = IV_FAIL;
6358 }
6359 else
6360 {
6361 ret = ih264e_get_version((CHAR *) ps_ip->s_ive_ip.pu1_version,
6362 ps_ip->s_ive_ip.u4_version_bufsize);
6363
6364 if (ret != IV_SUCCESS)
6365 {
6366 ps_op->s_ive_op.u4_error_code =
6367 IH264E_CXA_VERS_BUF_INSUFFICIENT;
6368 ret = IV_FAIL;
6369 }
6370 }
6371 break;
6372 }
6373
6374 case IVE_CMD_CTL_SET_NUM_CORES:
6375 ret = ih264e_set_num_cores(pv_api_ip, pv_api_op, ps_cfg);
6376 break;
6377
6378 default:
6379 /* invalidate config param struct as it is being served right away */
6380 ps_codec->as_cfg[i].u4_is_valid = 0;
6381
6382 DEBUG("Warning !! unrecognized control api command \n");
6383 break;
6384 }
6385
6386 ithread_mutex_unlock(ps_codec->pv_ctl_mutex);
6387
6388 return ret;
6389 }
6390
6391 /**
6392 *******************************************************************************
6393 *
6394 * @brief
6395 * Codec entry point function. All the function calls to the codec are done
6396 * using this function with different values specified in command
6397 *
6398 * @par Description:
6399 * Arguments are tested for validity and then based on the command
6400 * appropriate function is called
6401 *
6402 * @param[in] ps_handle
6403 * API level handle for codec
6404 *
6405 * @param[in] pv_api_ip
6406 * Input argument structure
6407 *
6408 * @param[out] pv_api_op
6409 * Output argument structure
6410 *
6411 * @returns error_status
6412 *
6413 * @remarks
6414 *
6415 *******************************************************************************
6416 */
ih264e_api_function(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)6417 IV_STATUS_T ih264e_api_function(iv_obj_t *ps_handle,
6418 void *pv_api_ip,
6419 void *pv_api_op)
6420 {
6421 /* api command */
6422 WORD32 command = IV_CMD_NA;
6423
6424 /* error status */
6425 IV_STATUS_T e_status;
6426 WORD32 ret;
6427
6428 /* tmp var */
6429 WORD32 *pu4_ptr_cmd = (WORD32 *) pv_api_ip;
6430
6431 /* validate input / output structures */
6432 e_status = api_check_struct_sanity(ps_handle, pv_api_ip, pv_api_op);
6433
6434 if (e_status != IV_SUCCESS)
6435 {
6436 DEBUG("error code = %d\n", *((UWORD32 *)pv_api_op + 1));
6437 return IV_FAIL;
6438 }
6439
6440 pu4_ptr_cmd++;
6441
6442 command = *pu4_ptr_cmd;
6443
6444 switch (command)
6445 {
6446 case IV_CMD_GET_NUM_MEM_REC:
6447 ret = ih264e_get_num_rec(pv_api_ip, pv_api_op);
6448 break;
6449
6450 case IV_CMD_FILL_NUM_MEM_REC:
6451 ret = ih264e_fill_num_mem_rec(pv_api_ip, pv_api_op);
6452 break;
6453
6454 case IV_CMD_INIT:
6455 ret = ih264e_init_mem_rec(ps_handle, pv_api_ip, pv_api_op);
6456 break;
6457
6458 case IV_CMD_RETRIEVE_MEMREC:
6459 ret = ih264e_retrieve_memrec(ps_handle, pv_api_ip, pv_api_op);
6460 break;
6461
6462 case IVE_CMD_VIDEO_CTL:
6463 ret = ih264e_ctl(ps_handle, pv_api_ip, pv_api_op);
6464 break;
6465
6466 case IVE_CMD_VIDEO_ENCODE:
6467 ret = ih264e_encode(ps_handle, pv_api_ip, pv_api_op);
6468 break;
6469
6470 default:
6471 ret = IV_FAIL;
6472 break;
6473 }
6474
6475 return (IV_STATUS_T) ret;
6476 }
6477