1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _if_subsystem_defs_h__ 8 #define _if_subsystem_defs_h__ 9 10 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 0 11 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1 1 12 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2 2 13 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3 3 14 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4 15 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5 16 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6 17 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7 18 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8 19 #define HIVE_IFMT_GP_REGS_SRST_IDX 9 20 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10 21 22 #define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX 11 23 24 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 25 26 /* order of the input bits for the ifmt irq controller */ 27 #define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID 0 28 #define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID 1 29 #define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID 2 30 #define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID 3 31 #define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID 4 32 33 /* order of the input bits for the ifmt Soft reset register */ 34 #define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX 0 35 #define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX 1 36 #define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX 2 37 #define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX 3 38 39 /* order of the input bits for the ifmt Soft reset register */ 40 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX 0 41 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX 1 42 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX 2 43 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX 3 44 45 #endif /* _if_subsystem_defs_h__ */ 46