1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include "msrtool.h"
4
intel_core2_early_probe(const struct targetdef * target,const struct cpuid_t * id)5 int intel_core2_early_probe(const struct targetdef *target, const struct cpuid_t *id) {
6 return ((VENDOR_INTEL == id->vendor) &&
7 (0x6 == id->family) &&
8 (0xf == id->model));
9 }
10
11 const struct msrdef intel_core2_early_msrs[] = {
12 {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", {
13 { BITS_EOT }
14 }},
15 {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", {
16 { BITS_EOT }
17 }},
18 {0x3f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TEMPERATURE_OFFSET", "", {
19 { BITS_EOT }
20 }},
21 {0xa8, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE0", "", {
22 { BITS_EOT }
23 }},
24 {0xa9, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE1", "", {
25 { BITS_EOT }
26 }},
27 {0xaa, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE2", "", {
28 { BITS_EOT }
29 }},
30 {0xab, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE3", "", {
31 { BITS_EOT }
32 }},
33 {0xac, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE4", "", {
34 { BITS_EOT }
35 }},
36 {0xad, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE5", "", {
37 { BITS_EOT }
38 }},
39 {0xcd, MSRTYPE_RDWR, MSR2(0, 0), "FSB_CLOCK_STS", "", {
40 { BITS_EOT }
41 }},
42 {0xe2, MSRTYPE_RDWR, MSR2(0, 0), "PMG_CST_CONFIG_CONTROL", "", {
43 { BITS_EOT }
44 }},
45 {0xe3, MSRTYPE_RDWR, MSR2(0, 0), "PMG_IO_BASE_ADDR", "", {
46 { BITS_EOT }
47 }},
48 {0xe4, MSRTYPE_RDWR, MSR2(0, 0), "PMG_IO_CAPTURE_ADDR", "", {
49 { BITS_EOT }
50 }},
51 {0xee, MSRTYPE_RDWR, MSR2(0, 0), "EXT_CONFIG", "", {
52 { BITS_EOT }
53 }},
54 {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", {
55 { BITS_EOT }
56 }},
57 {0x194, MSRTYPE_RDWR, MSR2(0, 0), "CLOCK_FLEX_MAX", "", {
58 { BITS_EOT }
59 }},
60 {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
61 { BITS_EOT }
62 }},
63 {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", {
64 { BITS_EOT }
65 }},
66 {0x1aa, MSRTYPE_RDWR, MSR2(0, 0), "PIC_SENS_CFG", "", {
67 { BITS_EOT }
68 }},
69 {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
70 { BITS_EOT }
71 }},
72 {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
73 { BITS_EOT }
74 }},
75 {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
76 { BITS_EOT }
77 }},
78 {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
79 { BITS_EOT }
80 }},
81 {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
82 { BITS_EOT }
83 }},
84 {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
85 { BITS_EOT }
86 }},
87 {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", {
88 { BITS_EOT }
89 }},
90 {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", {
91 { BITS_EOT }
92 }},
93 {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL", "", {
94 { BITS_EOT }
95 }},
96 {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", {
97 { BITS_EOT }
98 }},
99 {0xe1, MSRTYPE_RDWR, MSR2(0, 0), "SMM_CST_MISC_INFO", "", {
100 { BITS_EOT }
101 }},
102 {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", {
103 { BITS_EOT }
104 }},
105 {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", {
106 { BITS_EOT }
107 }},
108 {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {
109 { BITS_EOT }
110 }},
111 {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {
112 { BITS_EOT }
113 }},
114 {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
115 { BITS_EOT }
116 }},
117 {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CONTROL", "", {
118 { BITS_EOT }
119 }},
120 {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_CTL", "", {
121 { BITS_EOT }
122 }},
123 {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", {
124 { BITS_EOT }
125 }},
126 {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", {
127 { BITS_EOT }
128 }},
129 {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", {
130 { BITS_EOT }
131 }},
132 {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", {
133 { BITS_EOT }
134 }},
135 {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", {
136 { BITS_EOT }
137 }},
138 {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", {
139 { BITS_EOT }
140 }},
141 {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", {
142 { BITS_EOT }
143 }},
144 {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", {
145 { BITS_EOT }
146 }},
147 {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", {
148 { BITS_EOT }
149 }},
150 {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", {
151 { BITS_EOT }
152 }},
153 {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", {
154 { BITS_EOT }
155 }},
156 {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", {
157 { BITS_EOT }
158 }},
159 {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", {
160 { BITS_EOT }
161 }},
162 {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", {
163 { BITS_EOT }
164 }},
165 {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", {
166 { BITS_EOT }
167 }},
168 {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", {
169 { BITS_EOT }
170 }},
171 {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", {
172 { BITS_EOT }
173 }},
174 {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", {
175 { BITS_EOT }
176 }},
177 {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", {
178 { BITS_EOT }
179 }},
180 {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", {
181 { BITS_EOT }
182 }},
183 {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
184 { BITS_EOT }
185 }},
186 {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
187 { BITS_EOT }
188 }},
189 {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
190 { BITS_EOT }
191 }},
192 {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
193 { BITS_EOT }
194 }},
195 {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
196 { BITS_EOT }
197 }},
198 {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
199 { BITS_EOT }
200 }},
201 {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
202 { BITS_EOT }
203 }},
204 {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
205 { BITS_EOT }
206 }},
207 {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
208 { BITS_EOT }
209 }},
210 {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
211 { BITS_EOT }
212 }},
213 {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
214 { BITS_EOT }
215 }},
216 {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", {
217 { BITS_EOT }
218 }},
219 { MSR_EOT }
220 };
221