1 /*
2 * Copyright (c) 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef INTEL_L3_CONFIG_H
25 #define INTEL_L3_CONFIG_H
26
27 #include <stdio.h>
28
29 #include "dev/intel_device_info.h"
30
31 /**
32 * Chunk of L3 cache reserved for some specific purpose.
33 */
34 enum intel_l3_partition {
35 /** Shared local memory. */
36 INTEL_L3P_SLM = 0,
37 /** Unified return buffer. */
38 INTEL_L3P_URB,
39 /** Union of DC and RO. */
40 INTEL_L3P_ALL,
41 /** Data cluster RW partition. */
42 INTEL_L3P_DC,
43 /** Union of IS, C and T. */
44 INTEL_L3P_RO,
45 /** Instruction and state cache. */
46 INTEL_L3P_IS,
47 /** Constant cache. */
48 INTEL_L3P_C,
49 /** Texture cache. */
50 INTEL_L3P_T,
51 /** Unified tile cache. */
52 INTEL_L3P_TC,
53 /** Number of supported L3 partitions. */
54 INTEL_NUM_L3P
55 };
56
57 /**
58 * L3 configuration represented as the number of ways allocated for each
59 * partition. \sa get_l3_way_size().
60 */
61 struct intel_l3_config {
62 unsigned n[INTEL_NUM_L3P];
63 };
64
65 /**
66 * L3 configuration represented as a vector of weights giving the desired
67 * relative size of each partition. The scale is arbitrary, only the ratios
68 * between weights will have an influence on the selection of the closest L3
69 * configuration.
70 */
71 struct intel_l3_weights {
72 float w[INTEL_NUM_L3P];
73 };
74
75 float intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights w1);
76
77 struct intel_l3_weights
78 intel_get_default_l3_weights(const struct intel_device_info *devinfo,
79 bool needs_dc, bool needs_slm);
80
81 struct intel_l3_weights
82 intel_get_l3_config_weights(const struct intel_l3_config *cfg);
83
84 const struct intel_l3_config *
85 intel_get_default_l3_config(const struct intel_device_info *devinfo);
86
87 const struct intel_l3_config *
88 intel_get_l3_config(const struct intel_device_info *devinfo,
89 struct intel_l3_weights w0);
90
91 unsigned
92 intel_get_l3_config_urb_size(const struct intel_device_info *devinfo,
93 const struct intel_l3_config *cfg);
94
95 unsigned
96 intel_get_l3_partition_size(const struct intel_device_info *devinfo,
97 const struct intel_l3_config *cfg,
98 enum intel_l3_partition i);
99
100 void intel_dump_l3_config(const struct intel_l3_config *cfg, FILE *fp);
101
102 enum intel_urb_deref_block_size {
103 INTEL_URB_DEREF_BLOCK_SIZE_32 = 0,
104 INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY = 1,
105 INTEL_URB_DEREF_BLOCK_SIZE_8 = 2,
106 INTEL_URB_DEREF_BLOCK_SIZE_MESH = 3,
107 };
108
109 struct intel_urb_config {
110 unsigned size[5];
111 unsigned entries[5];
112 unsigned start[5];
113 };
114
115 void intel_get_urb_config(const struct intel_device_info *devinfo,
116 const struct intel_l3_config *l3_cfg,
117 bool tess_present, bool gs_present,
118 struct intel_urb_config *urb_cfg,
119 enum intel_urb_deref_block_size *deref_block_size,
120 bool *constrained);
121
122 /* Returns if URB changed for given shader stage. */
123 static inline bool
intel_urb_setup_changed(const struct intel_urb_config * a,const struct intel_urb_config * b,gl_shader_stage stage)124 intel_urb_setup_changed(const struct intel_urb_config *a,
125 const struct intel_urb_config *b,
126 gl_shader_stage stage)
127 {
128 if (a->size[stage] != b->size[stage] ||
129 a->entries[stage] != b->entries[stage] ||
130 a->start[stage] != b->start[stage])
131 return true;
132
133 return false;
134 }
135
136 struct intel_mesh_urb_allocation {
137 unsigned task_entries;
138 unsigned task_entry_size_64b;
139 unsigned task_starting_address_8kb;
140
141 unsigned mesh_entries;
142 unsigned mesh_entry_size_64b;
143 unsigned mesh_starting_address_8kb;
144
145 enum intel_urb_deref_block_size deref_block_size;
146 };
147
148 struct intel_mesh_urb_allocation
149 intel_get_mesh_urb_config(const struct intel_device_info *devinfo,
150 const struct intel_l3_config *l3_cfg,
151 unsigned tue_size_dw, unsigned mue_size_dw);
152
153 #endif /* INTEL_L3_CONFIG_H */
154