1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include "msrtool.h"
4
intel_nehalem_probe(const struct targetdef * target,const struct cpuid_t * id)5 int intel_nehalem_probe(const struct targetdef *target, const struct cpuid_t *id) {
6 return ((VENDOR_INTEL == id->vendor) &&
7 (0x6 == id->family) && (
8 (0x1a == id->model) ||
9 (0x1e == id->model) ||
10 (0x1f == id->model) ||
11 (0x2e == id->model) ||
12 (0x25 == id->model) || /* westmere */
13 (0x2c == id->model) || /* westmere */
14 (0x2f == id->model) /* westmere */
15 ));
16 }
17
18 const struct msrdef intel_nehalem_msrs[] = {
19 {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID Register",
20 "Model Specific Platform ID", {
21 { 63, 11, RESERVED },
22 { 52, 3, RESERVED },
23 { 49, 37, RESERVED },
24 { 12, 5, "Maximum Qualified Ratio:", "The maximum allowed bus ratio",
25 PRESENT_DEC, {
26 { BITVAL_EOT }
27 }},
28 { 7, 8, RESERVED },
29 { BITS_EOT }
30 }},
31 /* FIXME: This MSR not documented for Nehalem */
32 {0xcd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_FSB_FREQ", "Scalable Bus Speed", {
33 /* This field indicates the intended scalable bus clock speed */
34 { BITS_EOT }
35 }},
36 {0xce, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_PLATFORM_INFO", "", {
37 { 63, 16, RESERVED },
38 { 47, 8, "Maximum Efficiency Ratio", "R/O", PRESENT_DEC, {
39 { BITVAL_EOT }
40 }},
41 { 39, 10, RESERVED },
42 { 29, 1, "Programmable TDC-TDP Limit for Turbo Mode", "R/O", PRESENT_DEC, {
43 { MSR1(0), "TDC and TDP Limits for Turbo Mode are not programmable" },
44 { MSR1(1), "TDC and TDP Limits for Turbo Mode are programmable" },
45 { BITVAL_EOT }
46 }},
47 { 28, 1, "Programmable Ratio Limit for Turbo Mode", "R/O", PRESENT_DEC, {
48 { MSR1(0), "Programmable Ratio Limit for Turbo Mode is disabled" },
49 { MSR1(1), "Programmable Ratio Limit for Turbo Mode is enabled" },
50 { BITVAL_EOT }
51 }},
52 { 27, 12, RESERVED },
53 { 15, 8, "Maximum Non-Turbo Ratio", "R/O", PRESENT_DEC, {
54 /* The is ratio of the frequency that invariant TSC runs at. The invariant
55 * TSC requency can be computed by multipying this ratio by 133.33 Mhz
56 */
57 { BITVAL_EOT }
58 }},
59 { 7, 8, RESERVED },
60 { BITS_EOT }
61 }},
62 {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BBL_CR_CTL3", "", {
63 { BITS_EOT }
64 }},
65 /* FIXME: There is already two 0x1ad MSRs for Nehalem in the
66 * Intel 64 and IA-32 Architectures Software Developer's Manual
67 * Volume 3C 34-91. But from decimal value of this register,
68 * we can conclude, that it was just typo, and this register
69 * have address 0x1ac.
70 */
71 {0x1ac, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TURBO_POWER_CURRENT_LIMIT", "", {
72 { 63, 32, RESERVED },
73 { 31, 1, "TDC Limit Override Enable", "R/W", PRESENT_BIN, {
74 { MSR1(0), "TDC Limit Override is not active" },
75 { MSR1(1), "TDC Limit Override is active" },
76 { BITVAL_EOT }
77 }},
78 { 30, 15, "TDC Limit", "R/W", PRESENT_HEX, {
79 /* TDC Limit in 1/8 Amp granularity */
80 { BITVAL_EOT }
81 }},
82 { 15, 1, "TDP Limit Override Enable", "R/W", PRESENT_BIN, {
83 { MSR1(0), "TDP Limit Override is not active" },
84 { MSR1(1), "TDP Limit Override is active" },
85 { BITVAL_EOT }
86 }},
87 { 14, 15, "TDP Limit", "R/W", PRESENT_HEX, {
88 /* TDP Limit in 1/8 Watt granularity */
89 { BITVAL_EOT }
90 }},
91 { BITS_EOT }
92 }},
93 {0x1ad, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TURBO_RATIO_LIMIT",
94 "Maximum Ratio Limit of Turbo Mode", {
95 // "RO" if MSR_PLATFORM_INFO.[28] = 0
96 // "RW" if MSR_PLATFORM_INFO.[23] = 1
97 { 63, 32, RESERVED },
98 { 31, 8, "Maximum Ratio Limit for 4C", "R/O", PRESENT_HEX, {
99 // Maximum Turbo Ratio Limit of 4 core active
100 { BITVAL_EOT }
101 }},
102 { 23, 8, "Maximum Ratio Limit for 3C", "R/O", PRESENT_HEX, {
103 // Maximum Turbo Ratio Limit of 3 core active
104 { BITVAL_EOT }
105 }},
106 { 15, 8, "Maximum Ratio Limit for 2C", "R/O", PRESENT_HEX, {
107 // Maximum Turbo Ratio Limit of 2 core active
108 { BITVAL_EOT }
109 }},
110 { 7, 8, "Maximum Ratio Limit for 1C", "R/O", PRESENT_HEX, {
111 // Maximum Turbo Ratio Limit of 1 core active
112 { BITVAL_EOT }
113 }},
114 { BITS_EOT }
115 }},
116 {0x280, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL2", "", {
117 { 63, 33, RESERVED },
118 { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, {
119 { BITVAL_EOT }
120 }},
121 { 29, 15, RESERVED },
122 { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, {
123 { BITVAL_EOT }
124 }},
125 { BITS_EOT }
126 }},
127 {0x281, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL2", "", {
128 { 63, 33, RESERVED },
129 { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, {
130 { BITVAL_EOT }
131 }},
132 { 29, 15, RESERVED },
133 { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, {
134 { BITVAL_EOT }
135 }},
136 { BITS_EOT }
137 }},
138 {0x286, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_CTL2", "", {
139 { 63, 33, RESERVED },
140 { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, {
141 { BITVAL_EOT }
142 }},
143 { 29, 15, RESERVED },
144 { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, {
145 { BITVAL_EOT }
146 }},
147 { BITS_EOT }
148 }},
149 {0x287, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC7_CTL2", "", {
150 { 63, 33, RESERVED },
151 { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, {
152 { BITVAL_EOT }
153 }},
154 { 29, 15, RESERVED },
155 { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, {
156 { BITVAL_EOT }
157 }},
158 { BITS_EOT }
159 }},
160 {0x288, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC8_CTL2", "", {
161 { 63, 33, RESERVED },
162 { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, {
163 { BITVAL_EOT }
164 }},
165 { 29, 15, RESERVED },
166 { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, {
167 { BITVAL_EOT }
168 }},
169 { BITS_EOT }
170 }},
171 {0x3f8, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_PKG_C3_RESIDENCY", "", {
172 { 63, 64, "Package C3 Residency Counter", "R/O", PRESENT_DEC, {
173 /* Value since last reset that this package is in C3 states.
174 * Count at the same frequency as the TSC.
175 */
176 { BITVAL_EOT }
177 }},
178 { BITS_EOT }
179 }},
180 {0x3f9, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_PKG_C6_RESIDENCY", "", {
181 { BITS_EOT }
182 }},
183 {0x3fa, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_PKG_C7_RESIDENCY", "", {
184 { BITS_EOT }
185 }},
186 {0x418, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_CTL", "", {
187 { BITS_EOT }
188 }},
189 {0x419, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_STATUS", "", {
190 { BITS_EOT }
191 }},
192 {0x41a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_ADDR", "", {
193 { BITS_EOT }
194 }},
195 {0x41b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_MISC", "", {
196 { BITS_EOT }
197 }},
198 {0x41c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC7_CTL", "", {
199 { BITS_EOT }
200 }},
201 {0x41d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC7_STATUS", "", {
202 { BITS_EOT }
203 }},
204 {0x41e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC7_ADDR", "", {
205 { BITS_EOT }
206 }},
207 {0x41f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC7_MISC", "", {
208 { BITS_EOT }
209 }},
210 {0x420, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC8_CTL", "", {
211 { BITS_EOT }
212 }},
213 {0x421, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC8_STATUS", "", {
214 { BITS_EOT }
215 }},
216 {0x422, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC8_ADDR", "", {
217 { BITS_EOT }
218 }},
219 {0x423, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC8_MISC", "", {
220 { BITS_EOT }
221 }},
222
223 /* ==========================================================================
224 * Per core MSRs
225 * ==========================================================================
226 */
227
228 {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR",
229 "Pentium Processor Machine-Check Exception Address", {
230 { BITS_EOT }
231 }},
232 {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE",
233 "Pentium Processor Machine-Check Exception Type", {
234 { BITS_EOT }
235 }},
236 {0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", {
237 { BITS_EOT }
238 }},
239 {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", {
240 { BITS_EOT }
241 }},
242 {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "APIC BASE", {
243 /* In Intel's manual there is MAXPHYWID,
244 * which determine index of highest bit of
245 * APIC Base itself, so marking it as
246 * 'RESERVED'.
247 */
248 { 63, 52, RESERVED },
249 { 11, 1, "APIC Global Enable", "R/W", PRESENT_BIN, {
250 { BITVAL_EOT }
251 }},
252 { 10, 1, "x2APIC mode", "R/W", PRESENT_BIN, {
253 { MSR1(0), "x2APIC mode is disabled" },
254 { MSR1(1), "x2APIC mode is enabled" },
255 { BITVAL_EOT }
256 }},
257 { 9, 1, RESERVED },
258 { 8, 1, "BSP Flag", "R/W", PRESENT_BIN, {
259 { BITVAL_EOT }
260 }},
261 { 7, 8, RESERVED },
262 { BITS_EOT }
263 }},
264 {0x34, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_SMI_COUNT", "SMI Counter register", {
265 { 63, 32, RESERVED },
266 { 31, 32, "SMI Count", "R/O", PRESENT_HEX, {
267 { BITVAL_EOT }
268 }},
269 { BITS_EOT }
270 }},
271 /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */
272 {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL",
273 "Control features in Intel 64Processor", {
274 { 63, 48, RESERVED },
275 /* if CPUID.01H: ECX[6] = 1 */
276 { 15, 1, "SENTER Global Enable", "R/WL", PRESENT_BIN, {
277 { MSR1(0), "SENTER leaf functions are disabled" },
278 { MSR1(1), "SENTER leaf functions are enabled" },
279 { BITVAL_EOT }
280 }},
281 /* if CPUID.01H: ECX[6] = 1 */
282 { 14, 7, "SENTER Local Function Enables", "R/WL", PRESENT_BIN, {
283 { BITVAL_EOT }
284 }},
285 { 7, 5, RESERVED },
286 /* if CPUID.01H: ECX[5 or 6] = 1 */
287 { 2, 1, "VMX outside of SMX operation", "R/WL", PRESENT_BIN, {
288 /* This bit enables VMX for system executive
289 * that do not require SMX.
290 */
291 { MSR1(0), "VMX outside of SMX operation disabled" },
292 { MSR1(1), "VMX outside of SMX operation enabled" },
293 { BITVAL_EOT }
294 }},
295 { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
296 /* This bit enables a system executive to use
297 * VMX in conjunction with SMX to support Intel
298 * Trusted Execution Technology.
299 */
300 { MSR1(0), "VMX inside of SMX operation disabled" },
301 { MSR1(1), "VMX inside of SMX operation enabled" },
302 { BITVAL_EOT }
303 }},
304 /* if CPUID.01H: ECX[5 or 6] = 1 */
305 { 0, 1, "Lock bit", "R/WO", PRESENT_BIN, {
306 /* Once the Lock bit is set, the contents
307 * of this register cannot be modified.
308 * Therefore the lock bit must be set after
309 * configuring support for Intel Virtualization
310 * Technology and prior transferring control
311 * to an Option ROM or bootloader. Hence, once
312 * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR
313 * contents are preserved across RESET when
314 * PWRGOOD it not deasserted.
315 */
316 { MSR1(0), "IA32_FEATURE_CONTROL MSR can be modified" },
317 { MSR1(1), "IA32_FEATURE_CONTROL MSR cannot be modified" },
318 { BITVAL_EOT }
319 }},
320 { BITS_EOT }
321 }},
322 {0x40, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "", {
323 { BITS_EOT }
324 }},
325 {0x41, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_FROM_IP", "", {
326 { BITS_EOT }
327 }},
328 {0x42, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "", {
329 { BITS_EOT }
330 }},
331 {0x43, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_FROM_IP", "", {
332 { BITS_EOT }
333 }},
334 {0x60, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_LIP", "", {
335 { BITS_EOT }
336 }},
337 {0x61, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_TO_LIP", "", {
338 { BITS_EOT }
339 }},
340 {0x62, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_LIP", "", {
341 { BITS_EOT }
342 }},
343 {0x63, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_TO_LIP", "", {
344 { BITS_EOT }
345 }},
346 {0x79, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_UPDT_TRIG",
347 "BIOS Update Trigger Register (W)", {
348 { BITS_EOT }
349 }},
350 {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID",
351 "BIOS Update Signature ID (RO)", {
352 { BITS_EOT }
353 }},
354 {0xa0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SMRR_PHYS_BASE", "", {
355 { BITS_EOT }
356 }},
357 {0xa1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SMRR_PHYS_MASK", "", {
358 { BITS_EOT }
359 }},
360 {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC0",
361 "Performance counter register", {
362 { BITS_EOT }
363 }},
364 {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC1",
365 "Performance counter register", {
366 { BITS_EOT }
367 }},
368 {0xc3, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC2",
369 "Performance counter register", {
370 { BITS_EOT }
371 }},
372 {0xc4, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC3",
373 "Performance counter register", {
374 { BITS_EOT }
375 }},
376 {0xe2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PKG_CST_CONFIG_CONTROL",
377 "C-State Configuration Control", {
378 { 63, 37, RESERVED },
379 { 26, 1, "C1 state auto demotion", "R/W", PRESENT_DEC, {
380 { MSR1(0), "Demotion of C3/C6/C7 requests to C1 is disabled" },
381 { MSR1(1), "Demotion of C3/C6/C7 requests to C1 is enabled" },
382 { BITVAL_EOT }
383 }},
384 { 25, 1, "C3 state auto demotion", "R/W", PRESENT_DEC, {
385 { MSR1(0), "Demotion of C6/C7 requests to C3 is disabled" },
386 { MSR1(1), "Demotion of C6/C7 requests to C3 is enabled" },
387 { BITVAL_EOT }
388 }},
389 { 24, 1, "Interrupt filtering enabled/disabled", "R/W", PRESENT_DEC, {
390 { MSR1(0), "All CPU cores in deep C-State will wake for an "
391 "event message" },
392 { MSR1(1), "CPU in deep C-State will wake only when the event "
393 "message is destined for that core" },
394 { BITVAL_EOT }
395 }},
396 { 23, 8, RESERVED },
397 { 15, 1, "CFG Lock", "R/WO", PRESENT_DEC, {
398 { MSR1(0), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) "
399 "are writeable" },
400 { MSR1(1), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) "
401 "are locked until reset" },
402 { BITVAL_EOT }
403 }},
404 { 14, 4, RESERVED },
405 { 10, 1, "I/O MWAIT Redirection", "R/W", PRESENT_DEC, {
406 { MSR1(0), "I/O MWAIT Redirection disabled" },
407 { MSR1(1), "CPU will map IO_read instructions sent to "
408 "IO register specified by MSR_PMG_IO_CAPTURE_BASE "
409 "to MWAIT instructions" },
410 { BITVAL_EOT }
411 }},
412 { 9, 7, RESERVED },
413 { 2, 3, "Package C-State limit", "R/W", PRESENT_BIN, {
414 /* Specifies the lowest processor specific C-state code name
415 * (consuming the least power) for the package. The default is set
416 * as factory-configured package C-state limit.
417 */
418 { MSR1(0), "C0 (no package C-state support)" },
419 { MSR1(1), "C1 (behavior is the same as C0)" },
420 { MSR1(2), "C3" },
421 { MSR1(3), "C6" },
422 { MSR1(4), "C7" },
423 { MSR1(5), "Reserved" },
424 { MSR1(6), "Reserved" },
425 { MSR1(7), "No package C-state limit" },
426 { BITVAL_EOT }
427 /* Note: this field cannot be used to limit
428 * package C-state to C3
429 */
430 }},
431 { BITS_EOT }
432 }},
433 {0xe4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMG_IO_CAPTURE_BASE",
434 "Power Management IO Redirection in C-state", {
435 { 63, 45, RESERVED },
436 { 18, 3, "C-state Range", "R/W", PRESENT_BIN, {
437 /* Specifies the encoding value of the maximum C-State code name
438 * to be included when IO read to MWAIT redirection is enabled by
439 * MSR_PMG_CST_CONFIG_CONTROL[bit10].
440 */
441 { MSR1(0), "C3 is the max C-State to include" },
442 { MSR1(1), "C6 is the max C-State to include" },
443 { MSR1(2), "C7 is the max C-State to include" },
444 { BITVAL_EOT }
445 }},
446 { 15, 16, "LVL_2 Base Address", "R/W", PRESENT_HEX, {
447 /* Specifies the base address visible to software for IO redirection.
448 * If I/O MWAIT Redirection is enabled, reads to this address will be
449 * consumed by the power management logic and decoded to MWAIT
450 * instructions. When IO port address redirection is enabled,
451 * this is the I/O port address reported to the OS/software.
452 */
453 { BITVAL_EOT }
454 }},
455 { BITS_EOT }
456 }},
457 {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", {
458 { BITS_EOT }
459 }},
460 {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", {
461 { BITS_EOT }
462 }},
463 {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {
464 { BITS_EOT }
465 }},
466 {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", {
467 { BITS_EOT }
468 }},
469 {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", {
470 { BITS_EOT }
471 }},
472 {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", {
473 { BITS_EOT }
474 }},
475 {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {
476 { BITS_EOT }
477 }},
478 {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
479 { 63, 61, RESERVED },
480 { 2, 1, "MCIP", "R/W", PRESENT_BIN, {
481 /* When set, bit indicates that a machine check has been
482 * generated. If a second machine check is detected while
483 * this bit is still set, the processor enters a shutdown state.
484 * Software should write this bit to 0 after processing
485 * a machine check exception.
486 */
487 { MSR1(0), "Nothing" },
488 { MSR1(1), "Machine check has been generated" },
489 { BITVAL_EOT }
490 }},
491 { 1, 1, "EPIV", "R/W", PRESENT_BIN, {
492 /* When set, bit indicates that the instruction addressed
493 * by the instruction pointer pushed on the stack (when
494 * the machine check was generated) is directly associated
495 * with the error
496 */
497 { MSR1(0), "Nothing" },
498 { MSR1(1), "Instruction addressed directly associated with the error" },
499 { BITVAL_EOT }
500 }},
501 { 0, 1, "RIPV", "R/W", PRESENT_BIN, {
502 /* When set, bit indicates that the instruction addressed
503 * by the instruction pointer pushed on the stack (when
504 * the machine check was generated) can be used to restart
505 * the program. If cleared, the program cannot be reliably restarted
506 */
507 { MSR1(0), "Program cannot be reliably restarted" },
508 { MSR1(1), "Instruction addressed can be used to restart the program" },
509 { BITVAL_EOT }
510 }},
511 { BITS_EOT }
512 }},
513 /* if CPUID.0AH: EAX[15:8] > 0 */
514 {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL0",
515 "Performance Event Select Register 0", {
516 { 63, 32, RESERVED },
517 { 31, 8, "CMASK", "R/W", PRESENT_HEX, {
518 /* When CMASK is not zero, the corresponding performance
519 * counter 0 increments each cycle if the event count
520 * is greater than or equal to the CMASK.
521 */
522 { BITVAL_EOT }
523 }},
524 { 23, 1, "INV", "R/W", PRESENT_BIN, {
525 { MSR1(0), "CMASK using as is" },
526 { MSR1(1), "CMASK inerting" },
527 { BITVAL_EOT }
528 }},
529 { 22, 1, "EN", "R/W", PRESENT_BIN, {
530 { MSR1(0), "No commence counting" },
531 { MSR1(1), "Commence counting" },
532 { BITVAL_EOT }
533 }},
534 { 21, 1, "AnyThread", "R/W", PRESENT_BIN, {
535 { BITVAL_EOT }
536 }},
537 { 20, 1, "INT", "R/W", PRESENT_BIN, {
538 { MSR1(0), "Interrupt on counter overflow is disabled" },
539 { MSR1(1), "Interrupt on counter overflow is enabled" },
540 { BITVAL_EOT }
541 }},
542 { 19, 1, "PC", "R/W", PRESENT_BIN, {
543 { MSR1(0), "Disabled pin control" },
544 { MSR1(1), "Enabled pin control" },
545 { BITVAL_EOT }
546 }},
547 { 18, 1, "Edge", "R/W", PRESENT_BIN, {
548 { MSR1(0), "Disabled edge detection" },
549 { MSR1(1), "Enabled edge detection" },
550 { BITVAL_EOT }
551 }},
552 { 17, 1, "OS", "R/W", PRESENT_BIN, {
553 { MSR1(0), "Nothing" },
554 { MSR1(1), "Counts while in privilege level is ring 0" },
555 { BITVAL_EOT }
556 }},
557 { 16, 1, "USR", "R/W", PRESENT_BIN, {
558 { MSR1(0), "Nothing" },
559 { MSR1(1), "Counts while in privilege level is not ring 0" },
560 { BITVAL_EOT }
561 }},
562 { 15, 8, "UMask", "R/W", PRESENT_HEX, {
563 /* Qualifies the microarchitectural condition
564 * to detect on the selected event logic. */
565 { BITVAL_EOT }
566 }},
567 { 7, 8, "Event Select", "R/W", PRESENT_HEX, {
568 /* Selects a performance event logic unit. */
569 { BITVAL_EOT }
570 }},
571 { BITS_EOT }
572 }},
573 /* if CPUID.0AH: EAX[15:8] > 0 */
574 {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL1",
575 "Performance Event Select Register 1", {
576 { 63, 32, RESERVED },
577 { 31, 8, "CMASK", "R/W", PRESENT_HEX, {
578 /* When CMASK is not zero, the corresponding performance
579 * counter 1 increments each cycle if the event count
580 * is greater than or equal to the CMASK.
581 */
582 { BITVAL_EOT }
583 }},
584 { 23, 1, "INV", "R/W", PRESENT_BIN, {
585 { MSR1(0), "CMASK using as is" },
586 { MSR1(1), "CMASK inerting" },
587 { BITVAL_EOT }
588 }},
589 { 22, 1, "EN", "R/W", PRESENT_BIN, {
590 { MSR1(0), "No commence counting" },
591 { MSR1(1), "Commence counting" },
592 { BITVAL_EOT }
593 }},
594 { 21, 1, "AnyThread", "R/W", PRESENT_BIN, {
595 { BITVAL_EOT }
596 }},
597 { 20, 1, "INT", "R/W", PRESENT_BIN, {
598 { MSR1(0), "Interrupt on counter overflow is disabled" },
599 { MSR1(1), "Interrupt on counter overflow is enabled" },
600 { BITVAL_EOT }
601 }},
602 { 19, 1, "PC", "R/W", PRESENT_BIN, {
603 { MSR1(0), "Disabled pin control" },
604 { MSR1(1), "Enabled pin control" },
605 { BITVAL_EOT }
606 }},
607 { 18, 1, "Edge", "R/W", PRESENT_BIN, {
608 { MSR1(0), "Disabled edge detection" },
609 { MSR1(1), "Enabled edge detection" },
610 { BITVAL_EOT }
611 }},
612 { 17, 1, "OS", "R/W", PRESENT_BIN, {
613 { MSR1(0), "Nothing" },
614 { MSR1(1), "Counts while in privilege level is ring 0" },
615 { BITVAL_EOT }
616 }},
617 { 16, 1, "USR", "R/W", PRESENT_BIN, {
618 { MSR1(0), "Nothing" },
619 { MSR1(1), "Counts while in privilege level is not ring 0" },
620 { BITVAL_EOT }
621 }},
622 { 15, 8, "UMask", "R/W", PRESENT_HEX, {
623 /* Qualifies the microarchitectural condition
624 * to detect on the selected event logic. */
625 { BITVAL_EOT }
626 }},
627 { 7, 8, "Event Select", "R/W", PRESENT_HEX, {
628 /* Selects a performance event logic unit. */
629 { BITVAL_EOT }
630 }},
631 { BITS_EOT }
632 }},
633 /* if CPUID.0AH: EAX[15:8] > 0 */
634 {0x188, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL2",
635 "Performance Event Select Register 2", {
636 { 63, 32, RESERVED },
637 { 31, 8, "CMASK", "R/W", PRESENT_HEX, {
638 /* When CMASK is not zero, the corresponding performance
639 * counter 2 increments each cycle if the event count
640 * is greater than or equal to the CMASK.
641 */
642 { BITVAL_EOT }
643 }},
644 { 23, 1, "INV", "R/W", PRESENT_BIN, {
645 { MSR1(0), "CMASK using as is" },
646 { MSR1(1), "CMASK inerting" },
647 { BITVAL_EOT }
648 }},
649 { 22, 1, "EN", "R/W", PRESENT_BIN, {
650 { MSR1(0), "No commence counting" },
651 { MSR1(1), "Commence counting" },
652 { BITVAL_EOT }
653 }},
654 { 21, 1, "AnyThread", "R/W", PRESENT_BIN, {
655 { BITVAL_EOT }
656 }},
657 { 20, 1, "INT", "R/W", PRESENT_BIN, {
658 { MSR1(0), "Interrupt on counter overflow is disabled" },
659 { MSR1(1), "Interrupt on counter overflow is enabled" },
660 { BITVAL_EOT }
661 }},
662 { 19, 1, "PC", "R/W", PRESENT_BIN, {
663 { MSR1(0), "Disabled pin control" },
664 { MSR1(1), "Enabled pin control" },
665 { BITVAL_EOT }
666 }},
667 { 18, 1, "Edge", "R/W", PRESENT_BIN, {
668 { MSR1(0), "Disabled edge detection" },
669 { MSR1(1), "Enabled edge detection" },
670 { BITVAL_EOT }
671 }},
672 { 17, 1, "OS", "R/W", PRESENT_BIN, {
673 { MSR1(0), "Nothing" },
674 { MSR1(1), "Counts while in privilege level is ring 0" },
675 { BITVAL_EOT }
676 }},
677 { 16, 1, "USR", "R/W", PRESENT_BIN, {
678 { MSR1(0), "Nothing" },
679 { MSR1(1), "Counts while in privilege level is not ring 0" },
680 { BITVAL_EOT }
681 }},
682 { 15, 8, "UMask", "R/W", PRESENT_HEX, {
683 /* Qualifies the microarchitectural condition
684 * to detect on the selected event logic. */
685 { BITVAL_EOT }
686 }},
687 { 7, 8, "Event Select", "R/W", PRESENT_HEX, {
688 /* Selects a performance event logic unit. */
689 { BITVAL_EOT }
690 }},
691 { BITS_EOT }
692 }},
693 /* if CPUID.0AH: EAX[15:8] > 0 */
694 {0x189, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL3",
695 "Performance Event Select Register 3", {
696 { 63, 32, RESERVED },
697 { 31, 8, "CMASK", "R/W", PRESENT_HEX, {
698 /* When CMASK is not zero, the corresponding performance
699 * counter 3 increments each cycle if the event count
700 * is greater than or equal to the CMASK.
701 */
702 { BITVAL_EOT }
703 }},
704 { 23, 1, "INV", "R/W", PRESENT_BIN, {
705 { MSR1(0), "CMASK using as is" },
706 { MSR1(1), "CMASK inerting" },
707 { BITVAL_EOT }
708 }},
709 { 22, 1, "EN", "R/W", PRESENT_BIN, {
710 { MSR1(0), "No commence counting" },
711 { MSR1(1), "Commence counting" },
712 { BITVAL_EOT }
713 }},
714 { 21, 1, "AnyThread", "R/W", PRESENT_BIN, {
715 { BITVAL_EOT }
716 }},
717 { 20, 1, "INT", "R/W", PRESENT_BIN, {
718 { MSR1(0), "Interrupt on counter overflow is disabled" },
719 { MSR1(1), "Interrupt on counter overflow is enabled" },
720 { BITVAL_EOT }
721 }},
722 { 19, 1, "PC", "R/W", PRESENT_BIN, {
723 { MSR1(0), "Disabled pin control" },
724 { MSR1(1), "Enabled pin control" },
725 { BITVAL_EOT }
726 }},
727 { 18, 1, "Edge", "R/W", PRESENT_BIN, {
728 { MSR1(0), "Disabled edge detection" },
729 { MSR1(1), "Enabled edge detection" },
730 { BITVAL_EOT }
731 }},
732 { 17, 1, "OS", "R/W", PRESENT_BIN, {
733 { MSR1(0), "Nothing" },
734 { MSR1(1), "Counts while in privilege level is ring 0" },
735 { BITVAL_EOT }
736 }},
737 { 16, 1, "USR", "R/W", PRESENT_BIN, {
738 { MSR1(0), "Nothing" },
739 { MSR1(1), "Counts while in privilege level is not ring 0" },
740 { BITVAL_EOT }
741 }},
742 { 15, 8, "UMask", "R/W", PRESENT_HEX, {
743 /* Qualifies the microarchitectural condition
744 * to detect on the selected event logic. */
745 { BITVAL_EOT }
746 }},
747 { 7, 8, "Event Select", "R/W", PRESENT_HEX, {
748 /* Selects a performance event logic unit. */
749 { BITVAL_EOT }
750 }},
751 { BITS_EOT }
752 }},
753 {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
754 { 63, 48, RESERVED },
755 { 15, 16, "Current Performance State Value", "R/O", PRESENT_HEX, {
756 { BITVAL_EOT }
757 }},
758 { BITS_EOT }
759 }},
760 {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", {
761 { BITS_EOT }
762 }},
763 {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION",
764 "Clock Modulation", {
765 { 63, 59, RESERVED },
766 { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, {
767 { MSR1(0), "On demand Clock Modulation is disabled" },
768 { MSR1(1), "On demand Clock Modulation is enabled" },
769 { BITVAL_EOT }
770 }},
771 { 3, 3, "On demand Clock Modulation Duty Cycle", "R/W", PRESENT_HEX, {
772 { BITVAL_EOT }
773 }},
774 { 0, 1, RESERVED },
775 { BITS_EOT }
776 }},
777 {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT",
778 "Thermal Interrupt Control", {
779 { BITS_EOT }
780 }},
781 {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS",
782 "Thermal Monitor Status", {
783 { BITS_EOT }
784 }},
785 {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", {
786 { BITS_EOT }
787 }},
788 {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE",
789 "Enable miscellaneous processor features", {
790 { 63, 25, RESERVED },
791 /* Note: [38] bit using for whole package,
792 * while some other bits can be Core or Thread
793 * specific.
794 */
795 { 38, 1, "Turbo Mode", "R/W", PRESENT_BIN, {
796 /* When set to a 0 on processors that support IDA,
797 * CPUID.06H: EAX[1] reports the processor's
798 * support of turbo mode is enabled.
799 */
800 { MSR1(0), "Turbo Mode enabled" },
801 /* When set 1 on processors that support Intel Turbo Boost
802 * technology, the turbo mode feature is disabled and
803 * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
804 */
805 { MSR1(1), "Turbo Mode disabled" },
806 { BITVAL_EOT }
807 /* Note: the power-on default value is used by BIOS to detect
808 * hardware support of turbo mode. If power-on default value is 1,
809 * turbo mode is available in the processor. If power-on default
810 * value is 0, turbo mode not available.
811 */
812 }},
813 { 37, 3, RESERVED },
814 { 34, 1, "XD Bit Disable", "R/W", PRESENT_BIN, {
815 { BITVAL_EOT }
816 }},
817 { 33, 10, RESERVED },
818 { 23, 1, "xTPR Message Disable", "R/W", PRESENT_BIN, {
819 { BITVAL_EOT }
820 }},
821 { 22, 1, "Limit CPUID Maxval", "R/W", PRESENT_BIN, {
822 { BITVAL_EOT }
823 }},
824 { 21, 3, RESERVED },
825 { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, {
826 { BITVAL_EOT }
827 }},
828 { 17, 1, "UNDOCUMENTED", "R/W", PRESENT_BIN, {
829 { BITVAL_EOT }
830 }},
831 /* Note: [16] bit using for whole package,
832 * while some other bits can be Core or Thread
833 * specific.
834 */
835 { 16, 1, "Enhanced Intel SpeedStep Technology Enable", "R/W",
836 PRESENT_BIN, {
837 { BITVAL_EOT }
838 }},
839 { 15, 3, RESERVED },
840 { 12, 1, "Precise Event Based Sampling Unavailable", "R/O",
841 PRESENT_BIN, {
842 { BITVAL_EOT }
843 }},
844 { 11, 1, "Branch Trace Storage Unavailable", "R/O", PRESENT_BIN, {
845 { BITVAL_EOT }
846 }},
847 { 10, 3, RESERVED },
848 { 7, 1, "Performance Monitoring Available", "R", PRESENT_BIN, {
849 { BITVAL_EOT }
850 }},
851 { 6, 3, RESERVED },
852 { 3, 1, "Automatic Thermal Control Circuit Enable", "R/W"
853 , PRESENT_BIN, {
854 { BITVAL_EOT }
855 }},
856 { 2, 2, RESERVED },
857 { 0, 1, "Fast-Strings Enable", "R/W", PRESENT_BIN, {
858 { BITVAL_EOT }
859 }},
860 { BITS_EOT }
861 }},
862 {0x1a2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TEMPERATURE_TARGET", "", {
863 { 63, 40, RESERVED },
864 { 23, 8, "Temperature Target", "R", PRESENT_DEC, {
865 /* The minimum temperature at which PROCHOT# will be
866 * asserted. The value in degree C.
867 */
868 { BITVAL_EOT }
869 }},
870 { 15, 16, RESERVED },
871 { BITS_EOT }
872 }},
873 {0x1a6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_OFFCORE_RSP_O",
874 "Offcore Response Event Select Register", {
875 { BITS_EOT }
876 }},
877 {0x1aa, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MISC_PWR_MGMT", "", {
878 { 63, 62, RESERVED },
879 { 1, 1, "Energy/Performance Bias Enable", "R/W", PRESENT_BIN, {
880 /* This bit status is also reflected
881 * by CPUID.(EAX=06h):ECX[3]
882 */
883 { MSR1(0), "IA32_ENERGY_PERF_BIAS (0x1b0) is invisible "
884 "for Ring 0 software" },
885 { MSR1(1), "IA32_ENERGY_PERF_BIAS (0x1b0) accessible "
886 "by Ring 0 software" },
887 { BITVAL_EOT }
888 }},
889 { 0, 1, "EIST Hardware Coordination Disable", "R/W", PRESENT_BIN, {
890 { MSR1(0), "Hardware Coordination of EIST request "
891 "from processor cores is enabled" },
892 { MSR1(1), "Hardware Coordination of EIST request "
893 "from processor cores is disabled" },
894 { BITVAL_EOT }
895 }},
896 { BITS_EOT }
897 }},
898 {0x1c8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LBR_SELECT",
899 "Last Branch Record Filtering Select Register", {
900 /* "Nehalem support filtering of LBR based on combination of CPL
901 * and branch type conditions. When LBR filtering is enabled,
902 * the LBR stack only captures the subset of branches
903 * that are specified by MSR_LBR_SELECT."
904 *
905 * -- Section 17.6.2 of Intel 64 and IA-32 Architectures Software
906 * Developer's Manual, Volume 3
907 */
908 { BITS_EOT }
909 }},
910 {0x1c9, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LASTBRANCH_TOS",
911 "Last Branch Record Stack TOS", {
912 /* Contains an index (bits 0-3) that points to the MSR containing
913 * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680).
914 */
915 { BITS_EOT }
916 }},
917 {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL",
918 "Debug/Trace/Profile Resource Control", {
919 /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */
920 { 63, 49, RESERVED },
921 /* Only if IA32_PERF_CAPABILITIES[12] = 1 */
922 { 14, 1, "FREEZE_WHILE_SMM", "R/O", PRESENT_BIN, {
923 { MSR1(0), "Nothing" },
924 { MSR1(1), "Freeze perfmon and trace messages while in SMM" },
925 { BITVAL_EOT }
926 }},
927 { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, {
928 { MSR1(0), "Nothing" },
929 { MSR1(1), "Logical processor can receive and generate PMI "
930 "on behalf of the uncore" },
931 { BITVAL_EOT }
932 }},
933 /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
934 { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, {
935 { MSR1(0), "Nothing" },
936 { MSR1(1), "Each ENABLE bit of the global counter control MSR "
937 "are frozen (address 0x3bf) on PMI request" },
938 { BITVAL_EOT }
939 }},
940 /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
941 { 11, 1, "FREEZE_LBRS_ON_PMI", "R/O", PRESENT_BIN, {
942 { MSR1(0), "Nothing" },
943 { MSR1(1), "LBR stack is frozen on PMI request" },
944 { BITVAL_EOT }
945 }},
946 { 10, 1, "BTS_OFF_USR", "R/O", PRESENT_BIN, {
947 { MSR1(0), "Nothing" },
948 { MSR1(1), "BTS or BTM is skipped if CPL > 0" },
949 { BITVAL_EOT }
950 }},
951 { 9, 1, "BTS_OFF_OS", "R/O", PRESENT_BIN, {
952 { MSR1(0), "Nothing" },
953 { MSR1(1), "BTS or BTM is skipped if CPL = 0" },
954 { BITVAL_EOT }
955 }},
956 { 8, 1, "BTINT", "R/O", PRESENT_BIN, {
957 { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" },
958 { MSR1(1), "An interrupt is generated by the BTS facility "
959 "when the BTS buffer is full" },
960 { BITVAL_EOT }
961 }},
962 { 7, 1, "BTS", "R/O", PRESENT_BIN, {
963 { MSR1(0), "Logging of BTMs (branch trace messages) "
964 "in BTS buffer is disabled" },
965 { MSR1(1), "Logging of BTMs (branch trace messages) "
966 "in BTS buffer is enabled" },
967 { BITVAL_EOT }
968 }},
969 { 6, 1, "TR", "R/O", PRESENT_BIN, {
970 { MSR1(0), "Branch trace messages are disabled" },
971 { MSR1(1), "Branch trace messages are enabled" },
972 { BITVAL_EOT }
973 }},
974 { 5, 4, RESERVED },
975 { 1, 1, "BTF", "R/O", PRESENT_BIN, {
976 { MSR1(0), "Nothing" },
977 { MSR1(1), "Enabled treating EFLAGS.TF as single-step on "
978 "branches instead of single-step on instructions" },
979 { BITVAL_EOT }
980 }},
981 { 0, 1, "LBR", "R/O", PRESENT_BIN, {
982 { MSR1(0), "Nothing" },
983 { MSR1(1), "Enabled recording a running trace of the most "
984 "recent branches taken by the processor in the LBR stack" },
985 { BITVAL_EOT }
986 }},
987 { BITS_EOT }
988 }},
989 {0x1dd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LER_FROM_LIP",
990 "Last Exception Record From Linear IP", {
991 /* Contains a pointer to the last branch instruction
992 * that the processor executed prior to the last exception
993 * that was generated or the last interrupt that was handled.
994 */
995 { BITS_EOT }
996 }},
997 {0x1de, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LER_TO_LIP",
998 "Last Exception Record To Linear IP", {
999 /* This area contains a pointer to the target of the
1000 * last branch instruction that the processor executed
1001 * prior to the last exception that was generated or
1002 * the last interrupt that was handled
1003 */
1004 { BITS_EOT }
1005 }},
1006 {0x1f2, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_SMRR_PHYS_BASE",
1007 "SMRR Base Address", {
1008 /* Base address of SMM memory range.
1009 * Writeable only in SMM, so marking it as read-only */
1010 { 63, 32, RESERVED },
1011 { 31, 20, "SMRR physical Base Address", "R/O", PRESENT_HEX, {
1012 { BITVAL_EOT }
1013 }},
1014 { 11, 4, RESERVED },
1015 { 7, 8, "Memory type of the range", "R/O", PRESENT_HEX, {
1016 { BITVAL_EOT }
1017 }},
1018 { BITS_EOT }
1019 }},
1020 {0x1f3, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_SMRR_PHYS_MASK",
1021 "SMRR Range Mask", {
1022 /* Range Mask of SMM memory range.
1023 * Writeable only in SMM, so marking it as read-only */
1024 { 63, 32, RESERVED },
1025 { 31, 20, "SMRR address range mask", "R/O", PRESENT_HEX, {
1026 { BITVAL_EOT }
1027 }},
1028 { 11, 1, "Is Valid SMRR range mask", "R/O", PRESENT_BIN, {
1029 { MSR1(0), "SMRR range mask is disabled" },
1030 { MSR1(1), "SMRR range mask is enabled" },
1031 { BITVAL_EOT }
1032 }},
1033 { 10, 11, RESERVED },
1034 { BITS_EOT }
1035 }},
1036 {0x1f8, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PLATFORM_DCA_CAP",
1037 "DCA Capability", {
1038 { BITS_EOT }
1039 }},
1040 {0x1f9, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_CPU_DCA_CAP",
1041 "Support og Prefetch-Hint type", {
1042 /* If set, CPU supports Prefetch-Hint type.
1043 * TODO: As it is undocumented, which bit (or bits)
1044 * are needed to "be set", we need collect some
1045 * outputs of msrtool to understand possible msr values.
1046 */
1047 { BITS_EOT }
1048 }},
1049 {0x1fa, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DCA_0_CAP",
1050 "DCA type 0 Status and Control register", {
1051 /* This register defined as introduced only
1052 * in 06_2EH Nehalem model (latest), so be careful!
1053 */
1054 { 31, 5, RESERVED },
1055 { 26, 1, "HW_BLOCK", "R/O", PRESENT_BIN, {
1056 /* Hardware block of DCA */
1057 { MSR1(0), "DCA is not blocked by HW" },
1058 { MSR1(1), "DCA is blocked by HW (e.g. CR0.CD=1)" },
1059 { BITVAL_EOT }
1060 }},
1061 { 25, 1, RESERVED },
1062 { 24, 1, "SW_BLOCK", "R/W", PRESENT_BIN, {
1063 /* Software block of DCA */
1064 { MSR1(0), "DCA is not blocked by SW" },
1065 { MSR1(1), "DCA is blocked by SW" },
1066 { BITVAL_EOT }
1067 }},
1068 { 23, 7, RESERVED },
1069 { 16, 4, "DCA_RELAY", "R/W", PRESENT_HEX, {
1070 /* Writes will update the register
1071 * but have no HW side-effect */
1072 { BITVAL_EOT }
1073 }},
1074 { 12, 2, RESERVED },
1075 { 10, 4, "DCA_QUEUE_SIZE", "R/O", PRESENT_DEC, {
1076 { BITVAL_EOT }
1077 }},
1078 { 6, 4, "DCA_TYPE", "R/O", PRESENT_HEX, {
1079 { BITVAL_EOT }
1080 }},
1081 { 2, 2, "TRANSACTION", "R/O", PRESENT_HEX, {
1082 { BITVAL_EOT }
1083 }},
1084 { 0, 1, "DCA_ACTIVE", "R/O", PRESENT_BIN, {
1085 /* Set by HW when DCA is fuse-enabled and
1086 * no defeauteres are set */
1087 { MSR1(0), "DCA inactive" },
1088 { MSR1(1), "DCA inactive" },
1089 { BITVAL_EOT }
1090 }},
1091 { BITS_EOT }
1092 }},
1093 {0x1fc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_POWER_CTL",
1094 "Power Control Register", {
1095 { 63, 62, RESERVED },
1096 /* Whole package bit */
1097 { 1, 1, "C1E Enable", "R/W", PRESENT_BIN, {
1098 { MSR1(0), "Nothing" },
1099 { MSR1(1), "CPU switch to the Minimum Enhanced Intel "
1100 "SpeedStep Technology operating point when all "
1101 "execution cores enter MWAIT (C1)" },
1102 { BITVAL_EOT }
1103 }},
1104 { 0, 1, RESERVED },
1105 { BITS_EOT }
1106 }},
1107 {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE0", "", {
1108 { BITS_EOT }
1109 }},
1110 {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK0", "", {
1111 { BITS_EOT }
1112 }},
1113 {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE1", "", {
1114 { BITS_EOT }
1115 }},
1116 {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK1", "", {
1117 { BITS_EOT }
1118 }},
1119 {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE2", "", {
1120 { BITS_EOT }
1121 }},
1122 {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK2", "", {
1123 { BITS_EOT }
1124 }},
1125 {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE3", "", {
1126 { BITS_EOT }
1127 }},
1128 {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK3", "", {
1129 { BITS_EOT }
1130 }},
1131 {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE4", "", {
1132 { BITS_EOT }
1133 }},
1134 {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK4", "", {
1135 { BITS_EOT }
1136 }},
1137 {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE5", "", {
1138 { BITS_EOT }
1139 }},
1140 {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK5", "", {
1141 { BITS_EOT }
1142 }},
1143 {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE6", "", {
1144 { BITS_EOT }
1145 }},
1146 {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK6", "", {
1147 { BITS_EOT }
1148 }},
1149 {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE7", "", {
1150 { BITS_EOT }
1151 }},
1152 {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK7", "", {
1153 { BITS_EOT }
1154 }},
1155 /* if IA32_MTRR_CAP[7:0] > 8 */
1156 {0x210, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE8", "", {
1157 { BITS_EOT }
1158 }},
1159 /* if IA32_MTRR_CAP[7:0] > 8 */
1160 {0x211, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK8", "", {
1161 { BITS_EOT }
1162 }},
1163 /* if IA32_MTRR_CAP[7:0] > 9 */
1164 {0x212, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE9", "", {
1165 { BITS_EOT }
1166 }},
1167 /* if IA32_MTRR_CAP[7:0] > 9 */
1168 {0x213, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK9", "", {
1169 { BITS_EOT }
1170 }},
1171 {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
1172 { BITS_EOT }
1173 }},
1174 {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
1175 { BITS_EOT }
1176 }},
1177 {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
1178 { BITS_EOT }
1179 }},
1180 {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
1181 { BITS_EOT }
1182 }},
1183 {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
1184 { BITS_EOT }
1185 }},
1186 {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
1187 { BITS_EOT }
1188 }},
1189 {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
1190 { BITS_EOT }
1191 }},
1192 {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
1193 { BITS_EOT }
1194 }},
1195 {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
1196 { BITS_EOT }
1197 }},
1198 {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
1199 { BITS_EOT }
1200 }},
1201 {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
1202 { BITS_EOT }
1203 }},
1204 {0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "IA32_PAT", {
1205 { 63, 5, RESERVED },
1206 { 58, 3, "PA7", "R/W", PRESENT_BIN, {
1207 { BITVAL_EOT }
1208 }},
1209 { 55, 5, RESERVED },
1210 { 40, 3, "PA6", "R/W", PRESENT_BIN, {
1211 { BITVAL_EOT }
1212 }},
1213 { 47, 5, RESERVED },
1214 { 42, 3, "PA5", "R/W", PRESENT_BIN, {
1215 { BITVAL_EOT }
1216 }},
1217 { 39, 5, RESERVED },
1218 { 34, 3, "PA4", "R/W", PRESENT_BIN, {
1219 { BITVAL_EOT }
1220 }},
1221 { 31, 5, RESERVED },
1222 { 26, 3, "PA3", "R/W", PRESENT_BIN, {
1223 { BITVAL_EOT }
1224 }},
1225 { 23, 5, RESERVED },
1226 { 18, 3, "PA2", "R/W", PRESENT_BIN, {
1227 { BITVAL_EOT }
1228 }},
1229 { 15, 5, RESERVED },
1230 { 10, 3, "PA1", "R/W", PRESENT_BIN, {
1231 { BITVAL_EOT }
1232 }},
1233 { 7, 5, RESERVED },
1234 { 2, 3, "PA0", "R/W", PRESENT_BIN, {
1235 { BITVAL_EOT }
1236 }},
1237 { BITS_EOT }
1238 }},
1239 {0x282, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL2", "", {
1240 { 63, 33, RESERVED },
1241 { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, {
1242 { BITVAL_EOT }
1243 }},
1244 { 29, 15, RESERVED },
1245 { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, {
1246 { BITVAL_EOT }
1247 }},
1248 { BITS_EOT }
1249 }},
1250 {0x283, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL2", "", {
1251 { 63, 33, RESERVED },
1252 { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, {
1253 { BITVAL_EOT }
1254 }},
1255 { 29, 15, RESERVED },
1256 { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, {
1257 { BITVAL_EOT }
1258 }},
1259 { BITS_EOT }
1260 }},
1261 {0x284, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL2", "", {
1262 { 63, 33, RESERVED },
1263 { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, {
1264 { BITVAL_EOT }
1265 }},
1266 { 29, 15, RESERVED },
1267 { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, {
1268 { BITVAL_EOT }
1269 }},
1270 { BITS_EOT }
1271 }},
1272 {0x285, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_CTL2", "", {
1273 { 63, 33, RESERVED },
1274 { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, {
1275 { BITVAL_EOT }
1276 }},
1277 { 29, 15, RESERVED },
1278 { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, {
1279 { BITVAL_EOT }
1280 }},
1281 { BITS_EOT }
1282 }},
1283 {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE",
1284 "Default Memory Types", {
1285 { 63, 52, RESERVED },
1286 { 11, 1, "MTRR Enable", "R/W", PRESENT_BIN, {
1287 { BITVAL_EOT }
1288 }},
1289 { 10, 1, "Fixed Range MTRR Enable", "R/W", PRESENT_BIN, {
1290 { BITVAL_EOT }
1291 }},
1292 { 9, 7, RESERVED },
1293 { 2, 3, "Default Memory Type", "R/W", PRESENT_HEX, {
1294 { BITVAL_EOT }
1295 }},
1296 { BITS_EOT }
1297 }},
1298 /* if CPUID.0AH: EDX[4:0] > 0 */
1299 {0x309, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR0", "Fixed-Function "
1300 "Performance Counter Register 0: Counts Instr_Retired.Any", {
1301 /* Also known as MSR_PERF_FIXED_CTR0 */
1302 { BITS_EOT }
1303 }},
1304 /* if CPUID.0AH: EDX[4:0] > 1 */
1305 {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "Fixed-Function "
1306 "Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", {
1307 /* Also known as MSR_PERF_FIXED_CTR1 */
1308 { BITS_EOT }
1309 }},
1310 /* if CPUID.0AH: EDX[4:0] > 2 */
1311 {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR2", "Fixed-Function "
1312 "Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", {
1313 /* Also known as MSR_PERF_FIXED_CTR2 */
1314 { BITS_EOT }
1315 }},
1316 /* if CPUID.01H: ECX[15] = 1 */
1317 {0x345, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_CAPABILITIES", "", {
1318 /* Additional info available at Section 17.4.1 of
1319 * Intel 64 and IA-32 Architectures Software Developer's
1320 * Manual, Volume 3.
1321 */
1322 { 63, 50, RESERVED },
1323 { 13, 1, "Counter width", "R/O", PRESENT_BIN, {
1324 { MSR1(0), "Nothing" },
1325 { MSR1(1), "Full width of counter writable via IA32_A_PMCx" },
1326 { BITVAL_EOT }
1327 }},
1328 { 12, 1, "SMM_FREEZE", "R/O", PRESENT_BIN, {
1329 { MSR1(0), "Nothing" },
1330 { MSR1(1), "Freeze while SMM is supported" },
1331 { BITVAL_EOT }
1332 }},
1333 { 11, 4, "PEBS_REC_FORMAT", "R/O", PRESENT_HEX, {
1334 { BITVAL_EOT }
1335 }},
1336 { 7, 1, "PEBSSaveArchRegs", "R/O", PRESENT_BIN, {
1337 { BITVAL_EOT }
1338 }},
1339 { 6, 1, "PEBS Record Format", "R/O", PRESENT_BIN, {
1340 { BITVAL_EOT }
1341 }},
1342 { 5, 6, "LBR Format", "R/O", PRESENT_HEX, {
1343 { BITVAL_EOT }
1344 }},
1345 { BITS_EOT }
1346 }},
1347 /* if CPUID.0AH: EAX[7:0] > 1*/
1348 {0x38d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR_CTRL",
1349 "Fixed-Function-Counter Control Register", {
1350 /* Also known as MSR_PERF_FIXED_CTR_CTRL.
1351 * Counter increments while the results of ANDing respective enable bit
1352 * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits
1353 * in this MSR is true. */
1354 { 63, 52, RESERVED },
1355 { 11, 1, "EN2_PMI", "R/W", PRESENT_BIN, {
1356 { MSR1(0), "Nothing" },
1357 { MSR1(1), "PMI when fixed counter 2 overflows is enabled" },
1358 { BITVAL_EOT }
1359 }},
1360 /* if CPUID.0AH EAX[7:0] > 2 */
1361 { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
1362 { MSR1(0), "Counter only increments the associated event "
1363 "conditions occurring in the logical processor "
1364 "which programmed the MSR" },
1365 { MSR1(1), "Counting the associated event conditions "
1366 "occurring across all logical processors sharing "
1367 "a processor core" },
1368 { BITVAL_EOT }
1369 }},
1370 { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
1371 { MSR1(0), "Nothing" },
1372 { MSR1(1), "Fixed counter 2 is enabled to count while CPL > 0" },
1373 { BITVAL_EOT }
1374 }},
1375 { 8, 1, "EN2_OS", "R/W", PRESENT_BIN, {
1376 { MSR1(0), "Nothing" },
1377 { MSR1(1), "Fixed counter 2 is enabled to count while CPL = 0" },
1378 { BITVAL_EOT }
1379 }},
1380 { 7, 1, "EN1_PMI", "R/W", PRESENT_BIN, {
1381 { MSR1(0), "Nothing" },
1382 { MSR1(1), "PMI when fixed counter 1 overflows is enabled" },
1383 { BITVAL_EOT }
1384 }},
1385 /* if CPUID.0AH: EAX[7:0] > 2 */
1386 { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
1387 { MSR1(0), "Counter only increments the associated event "
1388 "conditions occurring in the logical processor "
1389 "which programmed the MSR" },
1390 { MSR1(1), "Counting the associated event conditions "
1391 "occurring across all logical processors sharing "
1392 "a processor core" },
1393 { BITVAL_EOT }
1394 }},
1395 { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
1396 { MSR1(0), "Nothing" },
1397 { MSR1(1), "Fixed counter 1 is enabled to count while CPL > 0" },
1398 { BITVAL_EOT }
1399 }},
1400 { 4, 1, "EN1_OS", "R/W", PRESENT_BIN, {
1401 { MSR1(0), "Nothing" },
1402 { MSR1(1), "Fixed counter 1 is enabled to count while CPL = 0" },
1403 { BITVAL_EOT }
1404 }},
1405 { 3, 1, "EN0_PMI", "R/W", PRESENT_BIN, {
1406 { MSR1(0), "Nothing" },
1407 { MSR1(1), "PMI when fixed counter 0 overflows is enabled" },
1408 { BITVAL_EOT }
1409 }},
1410 /* if CPUID.0AH: EAX[7:0] > 2 */
1411 { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
1412 { MSR1(0), "Counter only increments the associated event "
1413 "conditions occurring in the logical processor "
1414 "which programmed the MSR" },
1415 { MSR1(1), "Counting the associated event conditions "
1416 "occurring across all logical processors sharing "
1417 "a processor core" },
1418 { BITVAL_EOT }
1419 }},
1420 { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
1421 { MSR1(0), "Nothing" },
1422 { MSR1(1), "Fixed counter 0 is enabled to count while CPL > 0" },
1423 { BITVAL_EOT }
1424 }},
1425 { 0, 1, "EN0_OS", "R/W", PRESENT_BIN, {
1426 { MSR1(0), "Nothing" },
1427 { MSR1(1), "Fixed counter 0 is enabled to count while CPL = 0" },
1428 { BITVAL_EOT }
1429 }},
1430 { BITS_EOT }
1431 }},
1432 /* if CPUID.0AH: EAX[7:0] > 0 */
1433 {0x38e, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_GLOBAL_STATUS",
1434 "Global Performance Counter Status", {
1435 /* Also known as MSR_PERF_GLOBAL_STATUS */
1436 /* if CPUID.0AH: EAX[7:0] > 0 */
1437 { 63, 1, "CondChg: Status bits of this register has changed",
1438 "R/O", PRESENT_BIN, {
1439 { BITVAL_EOT }
1440 }},
1441 /* if CPUID.0AH: EAX[7:0] > 0 */
1442 { 62, 1, "OvfBuf: DS SAVE area Buffer overflow status",
1443 "R/O", PRESENT_BIN, {
1444 { BITVAL_EOT }
1445 }},
1446 /* if CPUID.0AH: EAX[7:0] > 2 */
1447 { 61, 1, "Ovf_Uncore: Uncore counter overflow status",
1448 "R/O", PRESENT_BIN, {
1449 { BITVAL_EOT }
1450 }},
1451 { 60, 26, RESERVED },
1452 /* if CPUID.0AH: EAX[7:0] > 1 */
1453 { 34, 1, "Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2",
1454 "R/O", PRESENT_BIN, {
1455 { BITVAL_EOT }
1456 }},
1457 /* if CPUID.0AH: EAX[7:0] > 1 */
1458 { 33, 1, "Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1",
1459 "R/O", PRESENT_BIN, {
1460 { BITVAL_EOT }
1461 }},
1462 /* if CPUID.0AH: EAX[7:0] > 1 */
1463 { 32, 1, "Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0",
1464 "R/O", PRESENT_BIN, {
1465 { BITVAL_EOT }
1466 }},
1467 { 31, 28, RESERVED },
1468 /* presented only in 06_2EH Nehalem model */
1469 { 3, 1, "Ovf_PMC3: Overflow status of IA32_PMC3", "R/O", PRESENT_BIN, {
1470 { BITVAL_EOT }
1471 }},
1472 /* presented only in 06_2EH Nehalem model */
1473 { 2, 1, "Ovf_PMC2: Overflow status of IA32_PMC2", "R/O", PRESENT_BIN, {
1474 { BITVAL_EOT }
1475 }},
1476 /* if CPUID.0AH: EAX[7:0] > 0 */
1477 { 1, 1, "Ovf_PMC1: Overflow status of IA32_PMC1", "R/O", PRESENT_BIN, {
1478 { BITVAL_EOT }
1479 }},
1480 /* if CPUID.0AH: EAX[7:0] > 0 */
1481 { 0, 1, "Ovf_PMC0: Overflow status of IA32_PMC0", "R/O", PRESENT_BIN, {
1482 { BITVAL_EOT }
1483 }},
1484 { BITS_EOT }
1485 }},
1486 /* if CPUID.0AH: EAX[7:0] > 0 */
1487 {0x38f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_CTL",
1488 "Global Performance Counter Control", {
1489 /* Counter increments while the result of ANDing respective
1490 * enable bit in this MSR with corresponding OS or USR bits
1491 * in general-purpose or fixed counter control MSR is true.
1492 */
1493 { 63, 29, RESERVED },
1494 /* if CPUID.0AH: EAX[7:0] > 1 */
1495 { 34, 1, "EN_FIXED_CTR2", "R/W", PRESENT_BIN, {
1496 { BITVAL_EOT }
1497 }},
1498 /* if CPUID.0AH: EAX[7:0] > 1 */
1499 { 33, 1, "EN_FIXED_CTR1", "R/W", PRESENT_BIN, {
1500 { BITVAL_EOT }
1501 }},
1502 /* if CPUID.0AH: EAX[7:0] > 1 */
1503 { 32, 1, "EN_FIXED_CTR0", "R/W", PRESENT_BIN, {
1504 { BITVAL_EOT }
1505 }},
1506 { 31, 30, RESERVED },
1507 /* if CPUID.0AH: EAX[7:0] > 0 */
1508 { 1, 1, "EN_PMC1", "R/W", PRESENT_BIN, {
1509 { BITVAL_EOT }
1510 }},
1511 /* if CPUID.0AH: EAX[7:0] > 0 */
1512 { 0, 1, "EN_PMC0", "R/W", PRESENT_BIN, {
1513 { BITVAL_EOT }
1514 }},
1515 { BITS_EOT }
1516 }},
1517 /* if CPUID.0AH: EAX[7:0] > 0 */
1518 {0x390, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_OVF_CTL",
1519 "Global Performance Counter Overflow Control", {
1520 /* if CPUID.0AH: EAX[7:0] > 0 */
1521 { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, {
1522 { BITVAL_EOT }
1523 }},
1524 /* if CPUID.0AH: EAX[7:0] > 0 */
1525 { 62, 1, "Clear OvfBuf bit", "R/W", PRESENT_BIN, {
1526 { BITVAL_EOT }
1527 }},
1528 /* Presented only in 06_2EH Nehalem model */
1529 { 61, 1, "Clear Ovf_Uncore bit", "R/W", PRESENT_BIN, {
1530 { BITVAL_EOT }
1531 }},
1532 { 60, 26, RESERVED },
1533 /* if CPUID.0AH: EAX[7:0] > 1 */
1534 { 34, 1, "Clear Ovf_FIXED_CTR2 bit", "R/W", PRESENT_BIN, {
1535 { BITVAL_EOT }
1536 }},
1537 /* if CPUID.0AH: EAX[7:0] > 1 */
1538 { 33, 1, "Clear Ovf_FIXED_CTR1 bit", "R/W", PRESENT_BIN, {
1539 { BITVAL_EOT }
1540 }},
1541 /* if CPUID.0AH: EAX[7:0] > 1 */
1542 { 32, 1, "Clear Ovf_FIXED_CTR0 bit", "R/W", PRESENT_BIN, {
1543 { BITVAL_EOT }
1544 }},
1545 { 31, 30, RESERVED },
1546 /* if CPUID.0AH: EAX[7:0] > 0 */
1547 { 1, 1, "Clear Ovf_PMC1 bit", "R/W", PRESENT_BIN, {
1548 { BITVAL_EOT }
1549 }},
1550 /* if CPUID.0AH: EAX[7:0] > 0 */
1551 { 0, 1, "Clear Ovf_PMC0 bit", "R/W", PRESENT_BIN, {
1552 { BITVAL_EOT }
1553 }},
1554 { BITS_EOT }
1555 }},
1556 /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures
1557 * Software Developer's Manual, Volume 3,
1558 * "Precise Event Based Sampling (PEBS)".
1559 */
1560 {0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PEBS_ENABLE", "PEBS Control", {
1561 { 63, 28, RESERVED },
1562 { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, {
1563 { MSR1(0), "Disabled" },
1564 { MSR1(1), "Enabled" },
1565 { BITVAL_EOT }
1566 }},
1567 { 34, 1, "Load Latency on IA32_PMC2", "R/W", PRESENT_BIN, {
1568 { MSR1(0), "Disabled" },
1569 { MSR1(1), "Enabled" },
1570 { BITVAL_EOT }
1571 }},
1572 { 33, 1, "Load Latency on IA32_PMC1", "R/W", PRESENT_BIN, {
1573 { MSR1(0), "Disabled" },
1574 { MSR1(1), "Enabled" },
1575 { BITVAL_EOT }
1576 }},
1577 { 32, 1, "Load Latency on IA32_PMC0", "R/W", PRESENT_BIN, {
1578 { MSR1(0), "Disabled" },
1579 { MSR1(1), "Enabled" },
1580 { BITVAL_EOT }
1581 }},
1582 { 31, 28, RESERVED },
1583 { 3, 1, "PEBS on IA32_PMC3", "R/W", PRESENT_BIN, {
1584 { MSR1(0), "Disabled" },
1585 { MSR1(1), "Enabled" },
1586 { BITVAL_EOT }
1587 }},
1588 { 2, 1, "PEBS on IA32_PMC2", "R/W", PRESENT_BIN, {
1589 { MSR1(0), "Disabled" },
1590 { MSR1(1), "Enabled" },
1591 { BITVAL_EOT }
1592 }},
1593 { 1, 1, "PEBS on IA32_PMC1", "R/W", PRESENT_BIN, {
1594 { MSR1(0), "Disabled" },
1595 { MSR1(1), "Enabled" },
1596 { BITVAL_EOT }
1597 }},
1598 { 0, 1, "PEBS on IA32_PMC0", "R/W", PRESENT_BIN, {
1599 { MSR1(0), "Disabled" },
1600 { MSR1(1), "Enabled" },
1601 { BITVAL_EOT }
1602 }},
1603 { BITS_EOT }
1604 }},
1605 {0x3f6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_LD_LAT", "", {
1606 /* See Section 18.6.1.2 of Intel's manual
1607 * for additional information.
1608 */
1609 { 63, 28, RESERVED },
1610 { 35, 20, RESERVED },
1611 { 15, 16, "Minimum threshold latency value of tagged "
1612 "load operation that will be counted", "R/W", PRESENT_DEC, {
1613 { BITVAL_EOT }
1614 }},
1615 { BITS_EOT }
1616 }},
1617 {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
1618 { BITS_EOT }
1619 }},
1620 {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
1621 { BITS_EOT }
1622 }},
1623 {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
1624 { BITS_EOT }
1625 }},
1626 {0x403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", {
1627 { BITS_EOT }
1628 }},
1629 {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", {
1630 { BITS_EOT }
1631 }},
1632 {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", {
1633 { BITS_EOT }
1634 }},
1635 {0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", {
1636 { BITS_EOT }
1637 }},
1638 {0x407, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_MISC", "", {
1639 { BITS_EOT }
1640 }},
1641 {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", {
1642 { BITS_EOT }
1643 }},
1644 {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", {
1645 { BITS_EOT }
1646 }},
1647 {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", {
1648 { BITS_EOT }
1649 }},
1650 {0x40b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_MISC", "", {
1651 { BITS_EOT }
1652 }},
1653 {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
1654 { BITS_EOT }
1655 }},
1656 {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
1657 { BITS_EOT }
1658 }},
1659 {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
1660 { BITS_EOT }
1661 }},
1662 {0x40f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", {
1663 { BITS_EOT }
1664 }},
1665 {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", {
1666 { BITS_EOT }
1667 }},
1668 {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", {
1669 { BITS_EOT }
1670 }},
1671 {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", {
1672 { BITS_EOT }
1673 }},
1674 {0x413, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_MISC", "", {
1675 { BITS_EOT }
1676 }},
1677 {0x414, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_CTL", "", {
1678 { BITS_EOT }
1679 }},
1680 {0x415, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_STATUS", "", {
1681 { BITS_EOT }
1682 }},
1683 {0x416, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_ADDR", "", {
1684 { BITS_EOT }
1685 }},
1686 {0x417, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_MISC", "", {
1687 { BITS_EOT }
1688 }},
1689 {0x480, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_BASIC",
1690 "Reporting Register of Basic VMX Capabilities", {
1691 /* Additional info available at
1692 * Appendix A.1, "Basic VMX Information" */
1693 { 63, 10, RESERVED },
1694 { 53, 4, "Memory type for VMREAD and VMWRITE", "R/O", PRESENT_HEX, {
1695 { BITVAL_EOT }
1696 }},
1697 { 49, 1, "Support of dual-treatment of system-management functions",
1698 "R/O", PRESENT_BIN, {
1699 { BITVAL_EOT }
1700 }},
1701 { 48, 1, "Enable full linear address access", "R/O", PRESENT_BIN, {
1702 { BITVAL_EOT }
1703 }},
1704 { 47, 3, RESERVED },
1705 { 44, 13, "VMXON region allocation size", "R/O", PRESENT_DEC, {
1706 { BITVAL_EOT }
1707 }},
1708 { 31, 32, "VMCS Revision Identifier", "R/O", PRESENT_HEX, {
1709 { BITVAL_EOT }
1710 }},
1711 { BITS_EOT }
1712 }},
1713 {0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS",
1714 "Capability Reporting Register of "
1715 "Pin-based VM-execution Controls", {
1716 /* Additional info available at Appendix A.3,
1717 * "VM-Execution Controls" */
1718 { BITS_EOT }
1719 }},
1720 {0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS",
1721 "Capability Reporting Register of "
1722 "Primary Processor-based VM-execution Controls", {
1723 /* Additional info available at Appendix A.3,
1724 * "VM-Execution Controls" */
1725 { BITS_EOT }
1726 }},
1727 {0x483, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_EXIT_CTLS",
1728 "Capability Reporting Register of VM-exit Controls", {
1729 /* Additional info available at Appendix A.4,
1730 * "VM-Exit Controls" */
1731 { BITS_EOT }
1732 }},
1733 {0x484, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_ENTRY_CTLS",
1734 "Capability Reporting Register of VM-entry Controls", {
1735 /* Additional info available at Appendix A.5,
1736 * "VM-Entry Controls" */
1737 { BITS_EOT }
1738 }},
1739 {0x485, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_MISC",
1740 "Reporting Register of Miscellaneous VMX Capabilities", {
1741 /* Additional info available at Appendix A.6,
1742 * "Miscellaneous Data" */
1743 { BITS_EOT }
1744 }},
1745 {0x486, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED0",
1746 "Capability Reporting Register of CR0 Bits Fixed to 0", {
1747 /* Additional info available at Appendix A.7,
1748 * "VMX-Fixed Bits in CR0" */
1749 { BITS_EOT }
1750 }},
1751 {0x487, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED1",
1752 "Capability Reporting Register of CR0 Bits Fixed to 1", {
1753 /* Additional info available at Appendix A.7,
1754 * "VMX-Fixed Bits in CR0" */
1755 { BITS_EOT }
1756 }},
1757 {0x488, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED0",
1758 "Capability Reporting Register of CR4 Bits Fixed to 0", {
1759 /* Additional info available at Appendix A.8,
1760 * "VMX-Fixed Bits in CR4" */
1761 { BITS_EOT }
1762 }},
1763 {0x489, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED1",
1764 "Capability Reporting Register of CR4 Bits Fixed to 1", {
1765 /* Additional info available at Appendix A.8,
1766 * "VMX-Fixed Bits in CR4" */
1767 { BITS_EOT }
1768 }},
1769 {0x48a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_VMCS_ENUM",
1770 "Capability Reporting Register of VMCS Field Enumeration", {
1771 /* Additional info available at Appendix A.9,
1772 * "VMCS Enumeration" */
1773 { BITS_EOT }
1774 }},
1775 {0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2",
1776 "Capability Reporting Register of Secondary "
1777 "Processor-based VM-execution Controls", {
1778 /* Additional info available at Appendix A.3,
1779 * "VM-Execution Controls" */
1780 { BITS_EOT }
1781 }},
1782 /* Undocumented PECI control register */
1783 {0x5a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PECI_CTL",
1784 "PECI Control Register", {
1785 { BITS_EOT }
1786 }},
1787 {0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "DS Save Area", {
1788 /* Additional info available at Section 18.10.4 of Intel 64
1789 * and IA-32 Architectures Software Developer's Manual,
1790 * "Debug Store (DS) Mechanism".
1791 */
1792 { 63, 32, RESERVED }, // reserved if not in IA-32e mode
1793 { 31, 32, "Linear address of DS buffer management area",
1794 "R/W", PRESENT_HEX, {
1795 { BITVAL_EOT }
1796 }},
1797 { BITS_EOT }
1798 }},
1799
1800 /* 16 registers - first
1801 * registers in sixteen pairs
1802 * of last branch record registers
1803 * on the last branch record stack
1804 */
1805 {0x680, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "R/W", {
1806 { BITS_EOT }
1807 }},
1808 {0x681, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_FROM_IP", "R/W", {
1809 { BITS_EOT }
1810 }},
1811 {0x682, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "R/W", {
1812 { BITS_EOT }
1813 }},
1814 {0x683, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_FROM_IP", "R/W", {
1815 { BITS_EOT }
1816 }},
1817 {0x684, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_FROM_IP", "R/W", {
1818 { BITS_EOT }
1819 }},
1820 {0x685, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_5_FROM_IP", "R/W", {
1821 { BITS_EOT }
1822 }},
1823 {0x686, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_FROM_IP", "R/W", {
1824 { BITS_EOT }
1825 }},
1826 {0x687, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_7_FROM_IP", "R/W", {
1827 { BITS_EOT }
1828 }},
1829 {0x688, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_8_FROM_IP", "R/W", {
1830 { BITS_EOT }
1831 }},
1832 {0x689, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_9_FROM_IP", "R/W", {
1833 { BITS_EOT }
1834 }},
1835 {0x68a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_10_FROM_IP", "R/W", {
1836 { BITS_EOT }
1837 }},
1838 {0x68b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_11_FROM_IP", "R/W", {
1839 { BITS_EOT }
1840 }},
1841 {0x68c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_12_FROM_IP", "R/W", {
1842 { BITS_EOT }
1843 }},
1844 {0x68d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_13_FROM_IP", "R/W", {
1845 { BITS_EOT }
1846 }},
1847 {0x68e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_14_FROM_IP", "R/W", {
1848 { BITS_EOT }
1849 }},
1850 {0x68f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_15_FROM_IP", "R/W", {
1851 { BITS_EOT }
1852 }},
1853
1854 /* 16 registers - second
1855 * registers in sixteen pairs
1856 * of last branch record registers
1857 * on the last branch record stack
1858 */
1859 {0x6c0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_LIP", "R/W", {
1860 { BITS_EOT }
1861 }},
1862 {0x6c1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_TO_LIP", "R/W", {
1863 { BITS_EOT }
1864 }},
1865 {0x6c2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_LIP", "R/W", {
1866 { BITS_EOT }
1867 }},
1868 {0x6c3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_TO_LIP", "R/W", {
1869 { BITS_EOT }
1870 }},
1871 {0x6c4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_TO_LIP", "R/W", {
1872 { BITS_EOT }
1873 }},
1874 {0x6c5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_5_TO_LIP", "R/W", {
1875 { BITS_EOT }
1876 }},
1877 {0x6c6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_TO_LIP", "R/W", {
1878 { BITS_EOT }
1879 }},
1880 {0x6c7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_7_TO_LIP", "R/W", {
1881 { BITS_EOT }
1882 }},
1883 {0x6c8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_8_TO_LIP", "R/W", {
1884 { BITS_EOT }
1885 }},
1886 {0x6c9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_9_TO_LIP", "R/W", {
1887 { BITS_EOT }
1888 }},
1889 {0x6ca, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_10_TO_LIP", "R/W", {
1890 { BITS_EOT }
1891 }},
1892 {0x6cb, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_11_TO_LIP", "R/W", {
1893 { BITS_EOT }
1894 }},
1895 {0x6cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_12_TO_LIP", "R/W", {
1896 { BITS_EOT }
1897 }},
1898 {0x6cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_13_TO_LIP", "R/W", {
1899 { BITS_EOT }
1900 }},
1901 {0x6ce, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_14_TO_LIP", "R/W", {
1902 { BITS_EOT }
1903 }},
1904 {0x6cf, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_15_TO_LIP", "R/W", {
1905 { BITS_EOT }
1906 }},
1907
1908 /* x2APIC registers - see Intel 64 Architecture x2APIC Specification */
1909
1910 {0x802, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_APICID",
1911 "x2APIC ID register", {
1912 { BITS_EOT }
1913 }},
1914 {0x803, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_VERSION",
1915 /* Same version between extended and legacy modes.
1916 * Bit 24 is available only to an x2APIC unit. */
1917 "x2APIC Version register", {
1918 { 31, 7, RESERVED },
1919 { 24, 1, "Directed EOI Support", "R/W", PRESENT_BIN, {
1920 { BITVAL_EOT }
1921 }},
1922 { 23, 8, "Max LVT Entry", "R/W", PRESENT_HEX, {
1923 { BITVAL_EOT }
1924 }},
1925 { 15, 8, RESERVED },
1926 { 7, 8, "Vector", "R/W", PRESENT_HEX, {
1927 { BITVAL_EOT }
1928 }},
1929 { BITS_EOT }
1930 }},
1931 {0x808, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_TPR",
1932 "x2APIC Task Priority register", {
1933 { 31, 24, RESERVED },
1934 { 7, 8, "TPR", "R/W", PRESENT_HEX, {
1935 { BITVAL_EOT }
1936 }},
1937 { BITS_EOT }
1938 }},
1939 {0x80a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_PPR",
1940 "x2APIC Processor Priority register", {
1941 { BITS_EOT }
1942 }},
1943 {0x80b, MSRTYPE_WRONLY, MSR2(0, 0), "IA32_X2APIC_EOI",
1944 /* 0 is the only valid value to write. GP fault
1945 * on non-zero write. */
1946 "x2APIC EOI register", {
1947 { BITS_EOT }
1948 }},
1949 {0x80d, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_LDR",
1950 /* Read Only in x2APIC mode, Read-Write in xAPIC mode. */
1951 "x2APIC Logical Destination register", {
1952 { BITS_EOT }
1953 }},
1954 {0x80f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_SIVR",
1955 "x2APIC Spurious Interrupt Vector register", {
1956 { 31, 19, RESERVED },
1957 { 12, 1, "EOI Broadcast Disable", "R/W", PRESENT_BIN, {
1958 { BITVAL_EOT }
1959 }},
1960 { 11, 3, RESERVED },
1961 { 8, 1, "APIC Software Enable/Disable", "R/W", PRESENT_BIN, {
1962 { MSR1(0), "APIC Disabled" },
1963 { MSR1(1), "APIC Enabled" },
1964 { BITVAL_EOT }
1965 }},
1966 { 7, 8, "Spurious Vector", "R/W", PRESENT_HEX, {
1967 { BITVAL_EOT }
1968 }},
1969 { BITS_EOT }
1970 }},
1971 {0x810, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_0",
1972 "x2APIC In-Service register bits [31:0]", {
1973 { BITS_EOT }
1974 }},
1975 {0x811, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_1",
1976 "x2APIC In-Service register bits [63:32]", {
1977 { BITS_EOT }
1978 }},
1979 {0x812, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_2",
1980 "x2APIC In-Service register bits [95:64]", {
1981 { BITS_EOT }
1982 }},
1983 {0x813, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_3",
1984 "x2APIC In-Service register bits [127:96]", {
1985 { BITS_EOT }
1986 }},
1987 {0x814, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_4",
1988 "x2APIC In-Service register bits [159:128]", {
1989 { BITS_EOT }
1990 }},
1991 {0x815, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_5",
1992 "x2APIC In-Service register bits [191:160]", {
1993 { BITS_EOT }
1994 }},
1995 {0x816, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_6",
1996 "x2APIC In-Service register bits [223:192]", {
1997 { BITS_EOT }
1998 }},
1999 {0x817, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_7",
2000 "x2APIC In-Service register bits [255:224]", {
2001 { BITS_EOT }
2002 }},
2003 {0x818, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR0",
2004 "x2APIC Trigger Mode register bits [31:0]", {
2005 { BITS_EOT }
2006 }},
2007 {0x819, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR1",
2008 "x2APIC Trigger Mode register bits [63:32]", {
2009 { BITS_EOT }
2010 }},
2011 {0x81a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR2",
2012 "x2APIC Trigger Mode register bits [95:64]", {
2013 { BITS_EOT }
2014 }},
2015 {0x81b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR3",
2016 "x2APIC Trigger Mode register bits [127:96]", {
2017 { BITS_EOT }
2018 }},
2019 {0x81c, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR4",
2020 "x2APIC Trigger Mode register bits [159:128]", {
2021 { BITS_EOT }
2022 }},
2023 {0x81d, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR5",
2024 "x2APIC Trigger Mode register bits [191:160]", {
2025 { BITS_EOT }
2026 }},
2027 {0x81e, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR6",
2028 "x2APIC Trigger Mode register bits [223:192]", {
2029 { BITS_EOT }
2030 }},
2031 {0x81f, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR7",
2032 "x2APIC Trigger Mode register bits [255:224]", {
2033 { BITS_EOT }
2034 }},
2035 {0x820, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR0",
2036 "x2APIC Interrupt Request register bits [31:0]", {
2037 { BITS_EOT }
2038 }},
2039 {0x821, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR1",
2040 "x2APIC Trigger Mode register bits [63:32]", {
2041 { BITS_EOT }
2042 }},
2043 {0x822, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR2",
2044 "x2APIC Trigger Mode register bits [95:64]", {
2045 { BITS_EOT }
2046 }},
2047 {0x823, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR3",
2048 "x2APIC Trigger Mode register bits [127:96]", {
2049 { BITS_EOT }
2050 }},
2051 {0x824, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR4",
2052 "x2APIC Trigger Mode register bits [159:128]", {
2053 { BITS_EOT }
2054 }},
2055 {0x825, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR5",
2056 "x2APIC Trigger Mode register bits [191:160]", {
2057 { BITS_EOT }
2058 }},
2059 {0x826, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR6",
2060 "x2APIC Trigger Mode register bits [223:192]", {
2061 { BITS_EOT }
2062 }},
2063 {0x827, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR7",
2064 "x2APIC Trigger Mode register bits [255:224]", {
2065 { BITS_EOT }
2066 }},
2067 {0x828, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_ESR",
2068 /* GP fault on non-zero writes. */
2069 "x2APIC Error Status register", {
2070 { 31, 24, RESERVED },
2071 { 7, 1, "Illegal Register Address", "R/O", PRESENT_BIN, {
2072 { BITVAL_EOT }
2073 }},
2074 { 6, 1, "Received Illegal Vector", "R/O", PRESENT_BIN, {
2075 { BITVAL_EOT }
2076 }},
2077 { 5, 1, "Send Illegal Vector", "R/O", PRESENT_BIN, {
2078 { BITVAL_EOT }
2079 }},
2080 { 4, 1, "Redirectible IPI", "R/O", PRESENT_BIN, {
2081 { BITVAL_EOT }
2082 }},
2083 { 3, 4, RESERVED },
2084 { BITS_EOT }
2085 }},
2086 {0x82f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_CMCI",
2087 "x2APIC LVT Corrected Machine Check Interrupt register", {
2088 { BITS_EOT }
2089 }},
2090 {0x830, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_ICR",
2091 "x2APIC Interrupt Command register", {
2092 { 63, 32, "Destination field", "R/W", PRESENT_HEX, {
2093 { BITVAL_EOT }
2094 }},
2095 { 31, 12, RESERVED },
2096 { 19, 2, "Destination Shorthand", "R/W", PRESENT_BIN, {
2097 { MSR1(0), "No Shorthand" },
2098 { MSR1(1), "Self" },
2099 { MSR1(2), "All including Self" },
2100 { MSR1(3), "All excluding Self" },
2101 { BITVAL_EOT }
2102 }},
2103 { 17, 2, RESERVED },
2104 { 15, 1, "Trigger Mode", "R/W", PRESENT_BIN, {
2105 { MSR1(0), "Edge" },
2106 { MSR1(1), "Level" },
2107 { BITVAL_EOT }
2108 }},
2109 { 14, 1, "Level", "R/W", PRESENT_BIN, {
2110 { MSR1(0), "De-assert" },
2111 { MSR1(1), "Assert" },
2112 { BITVAL_EOT }
2113 }},
2114 { 13, 2, RESERVED },
2115 { 11, 1, "Destination Mode", "R/W", PRESENT_BIN, {
2116 { MSR1(0), "Physical" },
2117 { MSR1(1), "Logical" },
2118 { BITVAL_EOT }
2119 }},
2120 { 10, 3, "Delivery Mode", "R/W", PRESENT_BIN, {
2121 { MSR1(0), "Fixed" },
2122 { MSR1(1), "Reserved" },
2123 { MSR1(2), "SMI" },
2124 { MSR1(3), "Reserved" },
2125 { MSR1(4), "NMI" },
2126 { MSR1(5), "INIT" },
2127 { MSR1(6), "Start Up" },
2128 { MSR1(7), "Reserved" },
2129 { BITVAL_EOT }
2130 }},
2131 { 7, 8, "Vector", "R/W", PRESENT_HEX, {
2132 { BITVAL_EOT }
2133 }},
2134 { BITS_EOT }
2135 }},
2136 {0x832, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_TIMER",
2137 "x2APIC LVT Timer Interrupt register", {
2138 { BITS_EOT }
2139 }},
2140 {0x833, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_THERMAL",
2141 "x2APIC LVT Thermal Sensor Interrupt register", {
2142 { BITS_EOT }
2143 }},
2144 {0x834, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_PMI",
2145 "x2APIC LVT Performance Monitor register", {
2146 { BITS_EOT }
2147 }},
2148 {0x835, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_LINT0",
2149 "x2APIC LVT LINT0 register", {
2150 { BITS_EOT }
2151 }},
2152 {0x836, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_LINT1",
2153 "x2APIC LVT LINT1 register", {
2154 { BITS_EOT }
2155 }},
2156 {0x837, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_ERROR",
2157 "x2APIC LVT Error register", {
2158 { BITS_EOT }
2159 }},
2160 {0x838, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_INIT_COUNT",
2161 "x2APIC Initial Count register", {
2162 { BITS_EOT }
2163 }},
2164 {0x839, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_CUR_COUNT",
2165 "x2APIC Current Count register", {
2166 { BITS_EOT }
2167 }},
2168 {0x83e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_DIV_CONF",
2169 "x2APIC Divide Configuration register", {
2170 { BITS_EOT }
2171 }},
2172 {0x83f, MSRTYPE_WRONLY, MSR2(0, 0), "IA32_X2APIC_SELF_IPI",
2173 "x2APIC Self IPI register", {
2174 /* Only in x2APIC mode. */
2175 { 31, 24, RESERVED },
2176 { 7, 8, "Vector", "R/W", PRESENT_HEX, {
2177 { BITVAL_EOT }
2178 }},
2179 { BITS_EOT }
2180 }},
2181 {0x107cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL0", "", {
2182 { BITS_EOT }
2183 }},
2184 {0x107cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL1", "", {
2185 { BITS_EOT }
2186 }},
2187 {0x107ce, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL2", "", {
2188 { BITS_EOT }
2189 }},
2190 {0x107cf, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL3", "", {
2191 { BITS_EOT }
2192 }},
2193 {0x107d0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL4", "", {
2194 { BITS_EOT }
2195 }},
2196 {0x107d1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL5", "", {
2197 { BITS_EOT }
2198 }},
2199 {0x107d2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL6", "", {
2200 { BITS_EOT }
2201 }},
2202 {0x107d3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL7", "", {
2203 { BITS_EOT }
2204 }},
2205 {0x107d8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_GL_CTL", "", {
2206 { BITS_EOT }
2207 }},
2208 /* if CPUID.80000001H: EDX[29] = 1 or CPUID.80000001H: EDX[27] = 1 */
2209 {0xc0000080, MSRTYPE_RDWR, MSR2(0, 0), "IA32_EFER",
2210 "Extended Feature Enables", {
2211 { 63, 52, RESERVED },
2212 { 11, 1, "Execute Disable Bit", "R/O", PRESENT_BIN, {
2213 { MSR1(0), "NX bit disabled" },
2214 { MSR1(1), "NX bit enabled" },
2215 { BITVAL_EOT }
2216 }},
2217 { 10, 1, "IA-32e Mode", "R/O", PRESENT_BIN, {
2218 { MSR1(0), "IA-32e Mode Inactive" },
2219 { MSR1(1), "IA-32e Mode Active" },
2220 { BITVAL_EOT }
2221 }},
2222 { 9, 1, RESERVED },
2223 { 8, 1, "IA-32e Mode Control", "R/W", PRESENT_BIN, {
2224 /* Enable IA-32e Mode operation */
2225 { BITVAL_EOT }
2226 }},
2227 { 7, 7, RESERVED },
2228 { 0, 1, "SYSCALL Control", "R/W", PRESENT_BIN, {
2229 /* Enable SYSCALL/SYSRET instructions
2230 * in 64-bit mode. */
2231 { BITVAL_EOT }
2232 }},
2233 { BITS_EOT }
2234 }},
2235 /* if CPUID.80000001H: EDX[29] = 1 */
2236 {0xc0000081, MSRTYPE_RDWR, MSR2(0, 0), "IA32_STAR",
2237 "System Call Target Address", {
2238 { BITS_EOT }
2239 }},
2240 /* if CPUID.80000001H: EDX[29] = 1 */
2241 {0xc0000082, MSRTYPE_RDWR, MSR2(0, 0), "IA32_LSTAR",
2242 "IA32e Mode System Call Target Address", {
2243 { BITS_EOT }
2244 }},
2245 /* if CPUID.80000001H: EDX[29] = 1 */
2246 {0xc0000084, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FMASK",
2247 "System Call Flag Mask", {
2248 { BITS_EOT }
2249 }},
2250 /* if CPUID.80000001H: EDX[29] = 1 */
2251 {0xc0000100, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FS_BASE",
2252 "Map of BASE Address of FS", {
2253 { BITS_EOT }
2254 }},
2255 /* if CPUID.80000001H: EDX[29] = 1 */
2256 {0xc0000101, MSRTYPE_RDWR, MSR2(0, 0), "IA32_GS_BASE",
2257 "Map of BASE Address of GS", {
2258 { BITS_EOT }
2259 }},
2260 /* if CPUID.80000001H: EDX[29] = 1 */
2261 {0xc0000102, MSRTYPE_RDWR, MSR2(0, 0), "IA32_KERNEL_GS_BASE",
2262 "Swap Target of BASE Address of GS", {
2263 { BITS_EOT }
2264 }},
2265 /* if CPUID.80000001H: EDX[27] = 1 */
2266 {0xc0000103, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TSC_AUX",
2267 "AUXILIARY TSC Signature", {
2268 { BITS_EOT }
2269 }},
2270 { MSR_EOT }
2271 };
2272