1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_H 4 #define SOC_INTEL_COMMON_BLOCK_FAST_SPI_H 5 6 #include <types.h> 7 8 /* Clear any SPI outstanding status bits, i.e., FCERR, FDONE etc. */ 9 void fast_spi_clear_outstanding_status(void); 10 /* Check if SPI transaction is pending */ 11 int fast_spi_cycle_in_progress(void); 12 /* 13 * Disable the BIOS write protect and Enable Prefetching and Caching. 14 */ 15 void fast_spi_init(void); 16 /* 17 * Set FAST_SPIBAR BIOS Control BILD bit. 18 */ 19 void fast_spi_set_bios_interface_lock_down(void); 20 /* 21 * Set FAST_SPIBAR BIOS Control LE bit. 22 */ 23 void fast_spi_set_lock_enable(void); 24 /* 25 * Set FAST_SPIBAR BIOS Control Ext Bios LE bit. 26 */ 27 void fast_spi_set_ext_bios_lock_enable(void); 28 /* 29 * Set FAST_SPIBAR BIOS Control EISS bit. 30 */ 31 void fast_spi_set_eiss(void); 32 /* 33 * Set FAST_SPI opcode menu. 34 */ 35 void fast_spi_set_opcode_menu(void); 36 /* 37 * Lock FAST_SPIBAR. 38 */ 39 void fast_spi_lock_bar(void); 40 /* 41 * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the 42 * FAST_SPI Protected Range (PR) registers. 43 */ 44 void fast_spi_pr_dlock(void); 45 /* 46 * Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30). 47 */ 48 void fast_spi_vscc0_lock(void); 49 /* 50 * Set FAST_SPIBAR Soft Reset Data Register value. 51 */ 52 void fast_spi_set_strap_msg_data(uint32_t soft_reset_data); 53 /* 54 * Returns bios_start and fills in size of the BIOS region. 55 */ 56 size_t fast_spi_get_bios_region(size_t *bios_size); 57 /* 58 * Cache the memory-mapped BIOS region as write-protect type. In ramstage 59 * this function needs to be called after the final MTRR solution has been 60 * calculated. 61 */ 62 void fast_spi_cache_bios_region(void); 63 /* 64 * Program temporary BAR for FAST_SPI in case any of the stages before ramstage 65 * need to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI 66 * enumeration. Also, Disable the BIOS write protect and Enable Prefetching and 67 * Caching. 68 */ 69 void fast_spi_early_init(uintptr_t spi_base_address); 70 /* 71 * Fast SPI flash controller structure to allow SoCs to define bus-controller 72 * mapping. 73 */ 74 extern const struct spi_ctrlr fast_spi_flash_ctrlr; 75 /* 76 * Clear SPI Synchronous SMI status bit and return its value. 77 */ 78 bool fast_spi_clear_sync_smi_status(void); 79 /* 80 * Read SPI Write protect disable bit. 81 */ 82 bool fast_spi_wpd_status(void); 83 /* 84 * Enable SPI Write protect. 85 */ 86 void fast_spi_enable_wp(void); 87 /* 88 * Disable SPI Write protect. 89 */ 90 void fast_spi_disable_wp(void); 91 /* 92 * Get base and size of extended BIOS decode window used at runtime in host address space. If 93 * the BIOS region is not greater than 16MiB, then this function returns 0 for both base and 94 * size. 95 */ 96 void fast_spi_get_ext_bios_window(uintptr_t *base, size_t *size); 97 /* 98 * SOC function to get SPI PSF Destination Id 99 */ 100 uint32_t soc_get_spi_psf_destination_id(void); 101 /* 102 * Add MTRR for extended BIOS region(when supported) to postcar frame 103 */ 104 struct postcar_frame; 105 void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf); 106 /* 107 * Set FAST_SPIBAR BIOS Decode Lock bit 108 */ 109 void fast_spi_set_bde(void); 110 /* 111 * Set FAST_SPIBAR Vendor Component Lock bit. 112 */ 113 void fast_spi_set_vcl(void); 114 115 #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */ 116