xref: /aosp_15_r20/external/coreboot/src/soc/intel/common/block/include/intelblocks/p2sb.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef SOC_INTEL_COMMON_BLOCK_P2SB_H
4 #define SOC_INTEL_COMMON_BLOCK_P2SB_H
5 
6 #include <stddef.h>
7 #include <stdint.h>
8 
9 #define PCH_P2SB_E0		0xe0
10 #define   P2SB_E0_MASKLOCK	(1 << 1)
11 #define PCH_P2SB_IBDF		0x6c
12 #define PCH_P2SB_HBDF		0x70
13 
14 enum {
15 	P2SB_EP_MASK_0_REG,
16 	P2SB_EP_MASK_1_REG,
17 	P2SB_EP_MASK_2_REG,
18 	P2SB_EP_MASK_3_REG,
19 	P2SB_EP_MASK_4_REG,
20 	P2SB_EP_MASK_5_REG,
21 	P2SB_EP_MASK_6_REG,
22 	P2SB_EP_MASK_7_REG,
23 	P2SB_EP_MASK_MAX_REG,
24 };
25 
26 void p2sb_unhide(void);
27 void p2sb_hide(void);
28 void p2sb_disable_sideband_access(void);
29 void p2sb_enable_bar(void);
30 void p2sb_configure_hpet(void);
31 
32 /*
33  * Functions to access IOE P2SB.
34  * pid argument: SBI port Id
35  */
36 void ioe_p2sb_enable_bar(void);
37 uint32_t ioe_p2sb_sbi_read(uint8_t pid, uint16_t reg);
38 void ioe_p2sb_sbi_write(uint8_t pid, uint16_t reg, uint32_t val);
39 
40 union p2sb_bdf {
41 	struct {
42 		uint16_t fn  : 3;
43 		uint16_t dev : 5;
44 		uint16_t bus : 8;
45 	};
46 	uint16_t raw;
47 };
48 
49 union p2sb_bdf p2sb_get_hpet_bdf(void);
50 void p2sb_set_hpet_bdf(union p2sb_bdf bdf);
51 union p2sb_bdf p2sb_get_ioapic_bdf(void);
52 void p2sb_set_ioapic_bdf(union p2sb_bdf bdf);
53 
54 /* SOC overrides */
55 /*
56  * Each SoC should implement EP Mask register to disable SB access
57  * Input:
58  * ep_mask: An array to be filled by SoC code with EP mask register.
59  * count: number of element in EP mask array.
60  */
61 void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count);
62 
63 #endif	/* SOC_INTEL_COMMON_BLOCK_P2SB_H */
64