1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
4 #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
5
6 #include <stdint.h>
7
8 /*
9 * In schematic PCIe root port numbers are 1-based, but FSP use 0-based indexes for
10 * the configuration arrays and so this macro subtracts 1 to convert RP# to array index.
11 */
12 #define PCIE_RP(x) ((x) - 1)
13 #define PCH_RP(x) PCIE_RP(x)
14 #define CPU_RP(x) PCIE_RP(x)
15
16 enum pcie_rp_flags {
17 PCIE_RP_HOTPLUG = (1 << 0),
18 /* PCIE RP Latency Tolerance Report */
19 PCIE_RP_LTR = (1 << 1),
20 /* PCIE RP Advanced Error Report */
21 PCIE_RP_AER = (1 << 2),
22 /* Clock source is not used by the root port. */
23 PCIE_RP_CLK_SRC_UNUSED = (1 << 3),
24 /*
25 * Clock request signal requires probing before enabling CLKREQ# based power
26 * management.
27 */
28 PCIE_RP_CLK_REQ_DETECT = (1 << 4),
29 /* Clock request signal is not used by the root port. */
30 PCIE_RP_CLK_REQ_UNUSED = (1 << 5),
31 /* indicates that this root port is built-in. */
32 PCIE_RP_BUILT_IN = (1 << 6),
33 };
34
35 enum pcie_clk_src_flags {
36 PCIE_CLK_FREE_RUNNING = (1 << 0),
37 PCIE_CLK_LAN = (1 << 1),
38 };
39
40 /* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */
41 enum L1_substates_control {
42 L1_SS_FSP_DEFAULT,
43 L1_SS_DISABLED,
44 L1_SS_L1_1,
45 L1_SS_L1_2,
46 };
47
48 /* This enum is for passing into an FSP UPD, typically ASPM */
49 enum ASPM_control {
50 ASPM_DEFAULT,
51 ASPM_DISABLE,
52 ASPM_L0S,
53 ASPM_L1,
54 ASPM_L0S_L1,
55 ASPM_AUTO,
56 };
57
58 /* PCIe Root Ports */
59 struct pcie_rp_config {
60 /* CLKOUT_PCIE_P/N# used by this root port as per schematics. */
61 uint8_t clk_src;
62 /* SRCCLKREQ# used by this root port as per schematics. */
63 uint8_t clk_req;
64 enum pcie_rp_flags flags;
65 /* PCIe RP L1 substate */
66 enum L1_substates_control PcieRpL1Substates;
67 /* PCIe RP ASPM */
68 enum ASPM_control pcie_rp_aspm;
69 /* timeout for device detect */
70 uint32_t pcie_rp_detect_timeout_ms;
71 };
72
73 /*
74 * The PCIe Root Ports usually come in groups of up to 8 PCI-device
75 * functions.
76 *
77 * `slot` is the PCI device/slot number of such a group.
78 * `start` is the initial PCI function number within the group. This is useful
79 * in case the root port numbers are not contiguous within the slot.
80 * `count` is the number of functions within the group starting with the `start`
81 * function number.
82 * `lcap_port_base` is the starting index of physical port as described in LCAP
83 * register in PCIe config space. coreboot always uses 0 based indexing while
84 * referring to the PCIe port but LCAP registers uses 1-based indexing in
85 * most of the cases. Remapping logic needs to correctly map LCAP port number
86 * (1-based or n-based) to coreboot indexing (0-based).
87 */
88 struct pcie_rp_group {
89 unsigned int slot;
90 unsigned int start;
91 unsigned int count;
92 unsigned int lcap_port_base;
93 };
94
rp_start_fn(const struct pcie_rp_group * group)95 static inline unsigned int rp_start_fn(const struct pcie_rp_group *group)
96 {
97 return group->start;
98 }
99
rp_end_fn(const struct pcie_rp_group * group)100 static inline unsigned int rp_end_fn(const struct pcie_rp_group *group)
101 {
102 return group->start + group->count - 1;
103 }
104
105 /*
106 * Update PCI paths of the root ports in the devicetree.
107 *
108 * Depending on the board layout and physical presence of downstream
109 * devices, individual root-port functions can be hidden and reordered.
110 * If we have device nodes for root ports in the static `devicetree.cb`,
111 * we need to update their PCI paths, so the nodes still control the
112 * correct root port. Device nodes for disabled root ports will be
113 * unlinked from the bus, to not interfere with PCI enumeration.
114 *
115 * Call this once, after root ports have been reordered, but before PCI
116 * enumeration.
117 *
118 * `groups` points to a list of groups terminated by an entry with `count == 0`.
119 * It is assumed that the first group includes the RPs 1 to the first group's
120 * `count` and that adjacent groups follow without gaps in the numbering.
121 */
122 void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
123
124 /*
125 * Return mask of PCIe root ports that are enabled by mainboard. Mask is set in
126 * the same order as the root ports in pcie_rp_group groups table.
127 *
128 * Thus, the status of first root port in the groups table is indicated by bit 0
129 * in the returned mask, second root port by bit 1 and so on.
130
131 * 1 in the bit position indicates root port is enabled, whereas 0 indicates root
132 * port is disabled. This function assumes that the maximum count of root ports
133 * in the groups table is <= 32.
134 */
135 uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
136
137 /* Get PCH root port groups */
138 const struct pcie_rp_group *soc_get_pch_rp_groups(void);
139
140 enum pcie_rp_type {
141 PCIE_RP_UNKNOWN,
142 PCIE_RP_CPU,
143 PCIE_RP_PCH,
144 };
145
146 /* For PCIe RTD3 support, each SoC that uses it must implement this function. */
147 struct device; /* Not necessary to include all of device/device.h */
148 enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev);
149
150 /* Return the virtual wire index that represents CPU-side PCIe root ports */
151 int soc_get_cpu_rp_vw_idx(const struct device *dev);
152
153 #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */
154