1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_INTEL_COMMON_BLOCK_PMCLIB_H 4 #define SOC_INTEL_COMMON_BLOCK_PMCLIB_H 5 6 #include <device/pci_type.h> 7 #include <types.h> 8 9 #define PCH_PMC_EPOC 0x18EC 10 11 /** 12 * enum pch_pmc_xtal - External crystal oscillator frequency. 13 * @XTAL_24_MHZ: 24 MHz external crystal. 14 * @XTAL_19_2_MHZ: 19.2 MHz external crystal. 15 * @XTAL_38_4_MHZ: 38.4 MHz external crystal. 16 * @XTAL_UNKNOWN_FREQ: Unsupported external crystal. 17 */ 18 enum pch_pmc_xtal { 19 XTAL_24_MHZ, 20 XTAL_19_2_MHZ, 21 XTAL_38_4_MHZ, 22 XTAL_UNKNOWN_FREQ = 0xf, 23 }; 24 25 /* 26 * pmc_get_xtal_freq() - Return &enum pch_pmc_xtal corresponding to 27 * frequency of external oscillator. 28 */ 29 enum pch_pmc_xtal pmc_get_xtal_freq(void); 30 31 /* 32 * pmc_send_pci_enum_done() - send PMC IPC to inform both BIOS Reset 33 * and PCI enumeration is done. 34 */ 35 void pmc_send_bios_reset_pci_enum_done(void); 36 37 /* Forward declare the power state struct here */ 38 struct chipset_power_state; 39 40 /* 41 * This is implemented as weak function in common pmc lib. 42 * Clears all power management related registers as the boot 43 * flow is past the point of needing to maintain the values. 44 */ 45 void soc_clear_pm_registers(uintptr_t pmc_bar); 46 47 /* 48 * This is implemented as weak function in common pmc lib and deals with any 49 * soc specific quarks. Returns SMI status bits. 50 */ 51 uint32_t soc_get_smi_status(uint32_t generic_sts); 52 53 /* 54 * This function is specific to soc and is defined as weak in common 55 * pmclib file. SOC code can implement it for any special condition 56 * specific to the soc e.g. in SKL in handles deep S3 scenario. 57 * Return ACPI_SX values to indicate the previous sleep state. 58 */ 59 int soc_prev_sleep_state(const struct chipset_power_state *ps, 60 int prev_sleep_state); 61 62 /* PM1 */ 63 void pmc_update_pm1_enable(uint16_t events); 64 uint16_t pmc_read_pm1_enable(void); 65 66 uint32_t pmc_read_pm1_control(void); 67 void pmc_write_pm1_control(uint32_t pm1_cnt); 68 69 /* 70 * Function to print, clear, and return SMI status bits in SMI_STS 71 * register. This function internally calls pmc_reset_smi_status with 72 * extra functionality of printing the set smi_sts bits. 73 */ 74 uint32_t pmc_clear_smi_status(void); 75 76 /* 77 * Function to return the 32 bit value of SMI control and enable register 78 * used to check which smi's are enabled. 79 */ 80 uint32_t pmc_get_smi_en(void); 81 82 /* Enable SMI event in SMI control and enable register */ 83 void pmc_enable_smi(uint32_t mask); 84 85 /* Disable SMI event */ 86 void pmc_disable_smi(uint32_t mask); 87 88 /* Enable events in PM1 control register */ 89 void pmc_enable_pm1_control(uint32_t mask); 90 91 /* Disable events in PM1 control register*/ 92 void pmc_disable_pm1_control(uint32_t mask); 93 94 /* Set the PM1 register to events in PM1_STS_EN register */ 95 void pmc_enable_pm1(uint16_t events); 96 97 /* Print, clear, and return PM1 status */ 98 uint16_t pmc_clear_pm1_status(void); 99 100 /* TCO */ 101 102 /* Print, clear, and return TCO status */ 103 uint32_t pmc_clear_tco_status(void); 104 105 /* 106 * This function returns array of string which represents 107 * names for the TCO status bits. Size of the array is 108 * returned as an output parameter. 109 */ 110 const char *const *soc_tco_sts_array(size_t *a); 111 112 /* GPE */ 113 114 /* 115 * We have symmetrical pairs of GPE0_EN/STS registers for Standard(STD) and GPIO 116 * events. STD events are specific to SoC and one of the GPE0_EN/STS pairs 117 * handles the STD events. Other GPE0_EN/STS pairs are used for GPIO events 118 * based on the GPE0_DWx mappings. 119 * 120 * STS registers are symmetrical to event enable registers. 121 * In case of STD events, for GPE0_STS register if the corresponding _EN bit is 122 * set in GPE0_EN, then when the STS bit gets set, the PMC will generate a Wake 123 * Event. Once back in an S0 state (or if already in an S0 state when the event 124 * occurs), the PMC will also generate an SCI if the SCI_EN bit is set, 125 * or an SMI# if the SCI_EN bit is not set. 126 * 127 * GPIO GPE registers are symmetrical to STD GPE registers and reads/writes to 128 * those register will result in the transaction being forwarded to the 129 * corresponding GPIO community based on the GPIO_GPE_CFG.gpe0_dwX register 130 * configuration. 131 */ 132 /* Enable a standard GPE. */ 133 void pmc_enable_std_gpe(uint32_t mask); 134 /* Disable a standard GPE. */ 135 void pmc_disable_std_gpe(uint32_t mask); 136 /* Disable all GPE's in STD and GPIO GPE registers. */ 137 void pmc_disable_all_gpe(void); 138 /* Clear STD and GPIO GPE status registers. */ 139 void pmc_clear_all_gpe_status(void); 140 141 /* Write PMC MMIO register value with the provided bitmask. */ 142 void pmc_or_mmio32(uint32_t offset, uint32_t ormask); 143 /* Clear status bits in Power and Reset Status (PRSTS) register */ 144 void pmc_clear_prsts(void); 145 146 /* 147 * Enable or disable global reset. If global reset is enabled, hard reset and 148 * soft reset will trigger global reset, where both host and TXE are reset. 149 * This is cleared on cold boot, hard reset, soft reset and Sx. 150 */ 151 void pmc_global_reset_enable(bool enable); 152 /* 153 * Disable global reset and lock the CF9 global reset register in accordance to PCH ME BWG 154 * sections 4.4.1, 4.5.1 and 18.4 and the PCH datasheet(s) (Intel doc e.g. 332691-002EN, 155 * 332996-002EN). Deviate from the BGW we don't depend on the Intel ME state because Intel 156 * FPT (Flash Programming Tool) normally is not used with coreboot. 157 * 158 * Once the register is locked, it can't be changed. This lock is reset on cold boot, hard 159 * reset, soft reset and Sx. 160 */ 161 void pmc_global_reset_disable_and_lock(void); 162 163 /* Returns the power state structure */ 164 struct chipset_power_state *pmc_get_power_state(void); 165 166 /* 167 * Reads, fills(chipset_power_state) and prints ACPI specific PM registers. This 168 * function does not check the previous sleep state. 169 */ 170 void pmc_fill_pm_reg_info(struct chipset_power_state *ps); 171 172 /* 173 * Reads and prints ACPI specific PM registers which are common across 174 * chipsets. Returns the previous sleep state which is one of ACPI_SX 175 * values. Additionally, it also disables all GPEs after GPE_EN 176 * registers are read. 177 */ 178 int pmc_fill_power_state(struct chipset_power_state *ps); 179 180 /* 181 * Sets the gpe routing table by properly programming the GPE_CFG 182 * and the MISCCFG registers. This function calls soc specific 183 * soc_get_gpi_gpe_configs which reads the devicetree info 184 * and populates the dw variables and also returns the bit offset 185 * in GPIO_CFG register which is assigned to ACPI register. 186 */ 187 void pmc_gpe_init(void); 188 189 /* Clear PMC GEN_PMCON_X register power failure status bits */ 190 void pmc_clear_pmcon_pwr_failure_sts(void); 191 192 /* Clear PMC GEN_PMCON_A register status bits */ 193 void pmc_clear_pmcon_sts(void); 194 195 /* Power Management Utility Functions. */ 196 197 /* Returns PMC base address */ 198 uintptr_t soc_read_pmc_base(void); 199 200 /* Returns pointer to the ETR register */ 201 uint32_t *soc_pmc_etr_addr(void); 202 203 /* 204 * This function returns array of string which represents 205 * names for the SMI status register bits. Size of the array is 206 * returned as an output parameter. 207 */ 208 const char *const *soc_smi_sts_array(size_t *a); 209 210 /* 211 * This function returns array of string which represents 212 * names for the STD GPE status register bits. 213 * Size of the array is returned as an output parameter. 214 */ 215 const char *const *soc_std_gpe_sts_array(size_t *a); 216 217 /* 218 * This function gets the gpe0 dwX values from devicetree 219 * for pmc_gpe_init which will use those to set the GPE_CFG 220 * register. 221 */ 222 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2); 223 224 /* 225 * Reads soc specific power management critical registers, fills 226 * chipset_power_state structure variable and prints. 227 */ 228 void soc_fill_power_state(struct chipset_power_state *ps); 229 230 /* 231 * Which state do we want to goto after g3 (power restored)? 232 * 0 == S5 Soft Off 233 * 1 == S0 Full On 234 * 2 == Keep Previous State 235 * Keep in sync with `config MAINBOARD_POWER_FAILURE_STATE`. 236 */ 237 enum { 238 MAINBOARD_POWER_STATE_OFF, 239 MAINBOARD_POWER_STATE_ON, 240 MAINBOARD_POWER_STATE_PREVIOUS, 241 }; 242 243 /* 244 * Implemented by SoC code to set PMC register to know which state 245 * system should go into after power is reapplied. 246 */ 247 void pmc_soc_set_afterg3_en(bool on); 248 /* 249 * Configure power state to go into when power is reapplied. 250 * 251 * To be called by SoC code once during boot and will be called by 252 * the "sleep" SMI handler when going into S5. 253 * 254 * `target_on` signifies that we are currently powering on, so that 255 * MAINBOARD_POWER_STATE_PREVIOUS can be handled accordingly. 256 */ 257 void pmc_set_power_failure_state(bool target_on); 258 259 /* 260 * This function ensures that the duration programmed in the PchPmPwrCycDur will never be 261 * smaller than the SLP_Sx assertion widths. 262 * If the pm_pwr_cyc_dur is less than any of the SLP_Sx assertion widths then it returns the 263 * default value PCH_PM_PWR_CYC_DUR. 264 */ 265 uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, 266 uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur); 267 268 /* API to set ACPI mode */ 269 void pmc_set_acpi_mode(void); 270 271 #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ 272