1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ 4 #define _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ 5 6 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 7 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 8 #define MCH_DDR_POWER_LIMIT_LO 0x58e0 9 #define MCH_DDR_POWER_LIMIT_HI 0x58e4 10 11 #define MSR_VR_CURRENT_CONFIG 0x601 12 #define MSR_PL3_CONTROL 0x615 13 #define MSR_PLATFORM_POWER_LIMIT 0x65c 14 15 /* Default power limit value in secs */ 16 #define MOBILE_SKU_PL1_TIME_SEC 28 17 18 #define MILLIWATTS_TO_WATTS 1000 19 20 struct soc_power_limits_config { 21 /* PL1 Override value in Watts */ 22 uint16_t tdp_pl1_override; 23 /* PL2 Override value in Watts */ 24 uint16_t tdp_pl2_override; 25 /* SysPL2 Value in Watts */ 26 uint16_t tdp_psyspl2; 27 /* SysPL3 Value in Watts */ 28 uint16_t tdp_psyspl3; 29 /* SysPL3 window size */ 30 uint32_t tdp_psyspl3_time; 31 /* SysPL3 duty cycle */ 32 uint32_t tdp_psyspl3_dutycycle; 33 /* PL4 Value in Watts */ 34 uint16_t tdp_pl4; 35 /* Estimated maximum platform power in Watts */ 36 uint16_t psys_pmax; 37 }; 38 39 /* Configure power limits for turbo mode */ 40 void set_power_limits(u8 power_limit_1_time, 41 struct soc_power_limits_config *config); 42 43 u8 get_cpu_tdp(void); 44 45 struct cpu_tdp_power_limits { 46 uint16_t mch_id; 47 uint8_t cpu_tdp; 48 unsigned int pl1_min_power; 49 unsigned int pl1_max_power; 50 unsigned int pl2_min_power; 51 unsigned int pl2_max_power; 52 unsigned int pl4_power; 53 }; 54 55 /* Modify Power Limit devictree settings during ramstage */ 56 void variant_update_cpu_power_limits(const struct cpu_tdp_power_limits *limits, 57 size_t num_entries); 58 59 #endif /* _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ */ 60