1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_INTEL_COMMON_BLOCK_SA_H 4 #define SOC_INTEL_COMMON_BLOCK_SA_H 5 6 #include <device/device.h> 7 #include <soc/iomap.h> 8 #include <soc/nvs.h> 9 #include <stddef.h> 10 11 /* Device 0:0.0 PCI configuration space */ 12 #define MCHBAR 0x48 13 #define GGC 0x50 /* GMCH Graphics Control Register */ 14 #define G_GMS_OFFSET 0x8 15 #define G_GMS_MASK 0xff00 16 #define G_GGMS_OFFSET 0x6 17 #define G_GGMS_MASK 0xc0 18 #define DPR 0x5C /* DMA Protected Range Register */ 19 #define PCIEXBAR 0x60 20 #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ 21 #define BDSM 0xb0 /* Base Data Stolen Memory */ 22 #define BGSM 0xb4 /* Base GTT Stolen Memory */ 23 #define TSEG 0xb8 /* TSEG base */ 24 #define TOLUD 0xbc /* Top of Low Used Memory */ 25 26 /* PCIEXBAR register fields */ 27 #define PCIEXBAR_LENGTH_4096MB 6 28 #define PCIEXBAR_LENGTH_2048MB 5 29 #define PCIEXBAR_LENGTH_1024MB 4 30 #define PCIEXBAR_LENGTH_512MB 3 31 #define PCIEXBAR_LENGTH_64MB 2 32 #define PCIEXBAR_LENGTH_128MB 1 33 #define PCIEXBAR_LENGTH_256MB 0 34 #define PCIEXBAR_PCIEXBAREN (1 << 0) 35 36 /* MCHBAR */ 37 #define MCHBAR8(x) (*(volatile u8 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) 38 #define MCHBAR16(x) (*(volatile u16 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) 39 #define MCHBAR32(x) (*(volatile u32 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) 40 #define MCHBAR64(x) (*(volatile u64 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) 41 42 /* REGBAR */ 43 #define REGBAR_OFFSET(pid, x) (REG_BASE_ADDRESS + ((pid) << 16) + (x)) 44 #define REGBAR8(pid, x) (*(volatile u8 *)(uintptr_t)REGBAR_OFFSET(pid, x)) 45 #define REGBAR16(pid, x) (*(volatile u16 *)(uintptr_t)REGBAR_OFFSET(pid, x)) 46 #define REGBAR32(pid, x) (*(volatile u32 *)(uintptr_t)REGBAR_OFFSET(pid, x)) 47 #define REGBAR64(pid, x) (*(volatile u64 *)(uintptr_t)REGBAR_OFFSET(pid, x)) 48 49 /* Perform System Agent Initialization during Bootblock phase */ 50 void bootblock_systemagent_early_init(void); 51 52 /* 53 * Fixed MMIO range 54 * INDEX = Either PCI configuration space registers or MMIO offsets 55 * mapped from REG. 56 * BASE = 64 bit Address. 57 * SIZE = 64 bit base length 58 * DESCRIPTION = Name of the register/offset. 59 */ 60 struct sa_mmio_descriptor { 61 unsigned int index; 62 uint64_t base; 63 uint64_t size; 64 const char *description; 65 }; 66 67 /* API to set Fixed MMIO address into PCI configuration space */ 68 void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources, 69 size_t count); 70 /* API to set Fixed MMIO address into MCH base address */ 71 void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources, 72 size_t count); 73 /* 74 * API to program fixed mmio resource range based on SoC input 75 * struct sa_mmio_descriptor 76 */ 77 void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt, 78 const struct sa_mmio_descriptor *sa_fixed_resources, size_t count); 79 /* 80 * API to set BIOS Reset CPL through MCHBAR 81 * SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h 82 */ 83 void enable_bios_reset_cpl(void); 84 /* API to enable PAM registers */ 85 void enable_pam_region(void); 86 /* API to enable Power Aware Interrupt Routing through MCHBAR */ 87 void enable_power_aware_intr(void); 88 /* API to get TOLUD base address */ 89 uintptr_t sa_get_tolud_base(void); 90 /* API to get GSM base address */ 91 uintptr_t sa_get_gsm_base(void); 92 /* API to get TSEG base address */ 93 uintptr_t sa_get_tseg_base(void); 94 /* API to get TSEG size */ 95 size_t sa_get_tseg_size(void); 96 /* API to lock PAM registers */ 97 void sa_lock_pam(void); 98 /* API to get MMIO config size */ 99 uint64_t sa_get_mmcfg_size(void); 100 /* API to get DSM size */ 101 uint64_t sa_get_dsm_size(void); 102 /* API to get GSM size */ 103 uint64_t sa_get_gsm_size(void); 104 /* API to get DPR size */ 105 uint64_t sa_get_dpr_size(void); 106 107 /* 108 * SoC overrides 109 * 110 * All new SoC must implement below functionality for ramstage. 111 */ 112 113 /* Perform System Agent Initialization during Ramstage phase */ 114 void soc_systemagent_init(struct device *dev); 115 /* 116 * SoC call to provide all known fixed memory ranges for Device 0:0.0. 117 * SoC function should provide fixed resource ranges in form of 118 * struct sa_mmio_descriptor along with resource count. 119 */ 120 void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt); 121 122 /* 123 * SoC call to provide all known configurable memory ranges for Device 0:0.0. 124 * SoC function should provide configurable resource ranges in form of 125 * struct sa_mmio_descriptor along with resource count. 126 */ 127 void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt); 128 129 /* SoC specific APIs to get UNCORE PRMRR base and mask values 130 * returns 0, if able to get base and mask values; otherwise returns -1 */ 131 int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask); 132 133 /* Returns the maximum supported capacity of a channel as encoded by DDRSZ in MiB */ 134 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz); 135 136 /* To be called in the acpi_fill_ssdt op of the domain */ 137 void ssdt_set_above_4g_pci(const struct device *dev); 138 139 #endif /* SOC_INTEL_COMMON_BLOCK_SA_H */ 140