1 /*
2 * Copyright 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef IRIS_RESOURCE_H
24 #define IRIS_RESOURCE_H
25
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "util/u_range.h"
29 #include "util/u_threaded_context.h"
30 #include "intel/isl/isl.h"
31 #include "iris_bufmgr.h"
32
33 struct iris_batch;
34 struct iris_context;
35 struct shader_info;
36
37 #define IRIS_MAX_MIPLEVELS 15
38
39 struct iris_format_info {
40 enum isl_format fmt;
41 struct isl_swizzle swizzle;
42 };
43
44 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
45 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
46 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
47 #define IRIS_RESOURCE_FLAG_SCRATCH_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
48 #define IRIS_RESOURCE_FLAG_DEVICE_MEM (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
49
50 /**
51 * Resources represent a GPU buffer object or image (mipmap tree).
52 *
53 * They contain the storage (BO) and layout information (ISL surface).
54 */
55 struct iris_resource {
56 struct threaded_resource base;
57 enum pipe_format internal_format;
58
59 /**
60 * The ISL surface layout information for this resource.
61 *
62 * This is not filled out for PIPE_BUFFER resources, but is guaranteed
63 * to be zeroed. Note that this also guarantees that res->surf.tiling
64 * will be ISL_TILING_LINEAR, so it's safe to check that.
65 */
66 struct isl_surf surf;
67
68 /** Backing storage for the resource */
69 struct iris_bo *bo;
70
71 /** offset at which data starts in the BO */
72 uint64_t offset;
73
74 /**
75 * A bitfield of PIPE_BIND_* indicating how this resource was bound
76 * in the past. Only meaningful for PIPE_BUFFER; used for flushing.
77 */
78 unsigned bind_history;
79
80 /**
81 * A bitfield of MESA_SHADER_* stages indicating where this resource
82 * was bound.
83 */
84 unsigned bind_stages;
85
86 /**
87 * For PIPE_BUFFER resources, a range which may contain valid data.
88 *
89 * This is a conservative estimate of what part of the buffer contains
90 * valid data that we have to preserve. The rest of the buffer is
91 * considered invalid, and we can promote writes to that region to
92 * be unsynchronized writes, avoiding blit copies.
93 */
94 struct util_range valid_buffer_range;
95
96 /**
97 * Auxiliary buffer information (CCS, MCS, or HiZ).
98 */
99 struct {
100 /** The surface layout for the auxiliary buffer. */
101 struct isl_surf surf;
102
103 /** The buffer object containing the auxiliary data. */
104 struct iris_bo *bo;
105
106 /** Offset into 'bo' where the auxiliary surface starts. */
107 uint32_t offset;
108
109 /** Offset into 'bo' where the compression control surface starts. */
110 uint32_t comp_ctrl_surf_offset;
111
112 /**
113 * When importing resources with a clear color, we may not know the
114 * clear color on the CPU at first.
115 */
116 bool clear_color_unknown;
117
118 /**
119 * Fast clear color for this surface. For depth surfaces, the clear
120 * value is stored as a float32 in the red component.
121 *
122 * Do not rely on this value if clear_color_unknown is set.
123 */
124 union isl_color_value clear_color;
125
126 /** Buffer object containing the indirect clear color. */
127 struct iris_bo *clear_color_bo;
128
129 /** Offset into bo where the clear color can be found. */
130 uint64_t clear_color_offset;
131
132 /**
133 * \brief The type of auxiliary compression used by this resource.
134 *
135 * This describes the type of auxiliary compression that is intended to
136 * be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means
137 * that auxiliary compression is permanently disabled. An aux usage
138 * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
139 * compression will always be enabled for this surface.
140 */
141 enum isl_aux_usage usage;
142
143 /**
144 * \brief Maps miptree slices to their current aux state.
145 *
146 * This two-dimensional array is indexed as [level][layer] and stores an
147 * aux state for each slice.
148 */
149 enum isl_aux_state **state;
150 } aux;
151
152 /**
153 * For external surfaces, this is format that was used to create or import
154 * the surface. For internal surfaces, this will always be
155 * PIPE_FORMAT_NONE.
156 */
157 enum pipe_format external_format;
158
159 /**
160 * For external surfaces, this is DRM format modifier that was used to
161 * create or import the surface. For internal surfaces, this will always
162 * be DRM_FORMAT_MOD_INVALID.
163 */
164 const struct isl_drm_modifier_info *mod_info;
165
166 /**
167 * The screen the resource was originally created with, stored for refcounting.
168 */
169 struct pipe_screen *orig_screen;
170 };
171
172 /**
173 * A simple <resource, offset> tuple for storing a reference to a
174 * piece of state stored in a GPU buffer object.
175 */
176 struct iris_state_ref {
177 struct pipe_resource *res;
178 uint32_t offset;
179 };
180
181 /**
182 * The SURFACE_STATE descriptors for a resource.
183 */
184 struct iris_surface_state {
185 /**
186 * CPU-side copy of the packed SURFACE_STATE structures, already
187 * aligned so they can be uploaded as a contiguous pile of bytes.
188 *
189 * This can be updated and re-uploaded if (e.g.) addresses need to change.
190 */
191 uint32_t *cpu;
192
193 /**
194 * A bitfield of ISL_AUX_USAGE_* modes that are present in the surface
195 * states.
196 */
197 unsigned aux_usages;
198
199 /**
200 * How many states are there? (Each aux mode has its own state.)
201 */
202 unsigned num_states;
203
204 /**
205 * Address of the resource (res->bo->address). Note that "Surface
206 * Base Address" may be offset from this value.
207 */
208 uint64_t bo_address;
209
210 /** A reference to the GPU buffer holding our uploaded SURFACE_STATE */
211 struct iris_state_ref ref;
212 };
213
214 /**
215 * Gallium CSO for sampler views (texture views).
216 *
217 * In addition to the normal pipe_resource, this adds an ISL view
218 * which may reinterpret the format or restrict levels/layers.
219 *
220 * These can also be linear texture buffers.
221 */
222 struct iris_sampler_view {
223 struct pipe_sampler_view base;
224 struct isl_view view;
225
226 union isl_color_value clear_color;
227
228 /* A short-cut (not a reference) to the actual resource being viewed.
229 * Multi-planar (or depth+stencil) images may have multiple resources
230 * chained together; this skips having to traverse base->texture->*.
231 */
232 struct iris_resource *res;
233
234 /** The resource (BO) holding our SURFACE_STATE. */
235 struct iris_surface_state surface_state;
236 };
237
238 /**
239 * Image view representation.
240 */
241 struct iris_image_view {
242 struct pipe_image_view base;
243
244 /** The resource (BO) holding our SURFACE_STATE. */
245 struct iris_surface_state surface_state;
246 };
247
248 /**
249 * Gallium CSO for surfaces (framebuffer attachments).
250 *
251 * A view of a surface that can be bound to a color render target or
252 * depth/stencil attachment.
253 */
254 struct iris_surface {
255 struct pipe_surface base;
256 struct isl_view view;
257 struct isl_view read_view;
258 union isl_color_value clear_color;
259
260 /** The resource (BO) holding our SURFACE_STATE. */
261 struct iris_surface_state surface_state;
262 /** The resource (BO) holding our SURFACE_STATE for read. */
263 struct iris_surface_state surface_state_read;
264 };
265
266 /**
267 * Transfer object - information about a buffer mapping.
268 */
269 struct iris_transfer {
270 struct threaded_transfer base;
271 struct util_debug_callback *dbg;
272 void *buffer;
273 void *ptr;
274
275 /** A linear staging resource for GPU-based copy_region transfers. */
276 struct pipe_resource *staging;
277 struct blorp_context *blorp;
278 struct iris_batch *batch;
279
280 void (*unmap)(struct iris_transfer *);
281 };
282
283 /**
284 * Memory Object
285 */
286 struct iris_memory_object {
287 struct pipe_memory_object b;
288 struct iris_bo *bo;
289 uint64_t format;
290 unsigned stride;
291 };
292
293 /**
294 * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
295 */
296 static inline struct iris_bo *
iris_resource_bo(struct pipe_resource * p_res)297 iris_resource_bo(struct pipe_resource *p_res)
298 {
299 struct iris_resource *res = (void *) p_res;
300 return res->bo;
301 }
302
303 static inline uint32_t
iris_mocs(const struct iris_bo * bo,const struct isl_device * dev,isl_surf_usage_flags_t usage)304 iris_mocs(const struct iris_bo *bo,
305 const struct isl_device *dev,
306 isl_surf_usage_flags_t usage)
307 {
308 return isl_mocs(dev,
309 usage |
310 ((bo && bo->real.protected) ? ISL_SURF_USAGE_PROTECTED_BIT : 0),
311 bo && iris_bo_is_external(bo));
312 }
313
314 struct iris_format_info iris_format_for_usage(const struct intel_device_info *,
315 enum pipe_format pf,
316 isl_surf_usage_flags_t usage);
317
318 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
319
320 void iris_get_depth_stencil_resources(struct pipe_resource *res,
321 struct iris_resource **out_z,
322 struct iris_resource **out_s);
323 bool iris_resource_set_clear_color(struct iris_context *ice,
324 struct iris_resource *res,
325 union isl_color_value color);
326
327 void iris_replace_buffer_storage(struct pipe_context *ctx,
328 struct pipe_resource *dst,
329 struct pipe_resource *src,
330 unsigned num_rebinds,
331 uint32_t rebind_mask,
332 uint32_t delete_buffer_id);
333
334
335 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
336
337 void iris_dirty_for_history(struct iris_context *ice,
338 struct iris_resource *res);
339
340 unsigned iris_get_num_logical_layers(const struct iris_resource *res,
341 unsigned level);
342
343 void iris_resource_disable_aux(struct iris_resource *res);
344
345 #define INTEL_REMAINING_LAYERS UINT32_MAX
346 #define INTEL_REMAINING_LEVELS UINT32_MAX
347
348 void
349 iris_hiz_exec(struct iris_context *ice,
350 struct iris_batch *batch,
351 struct iris_resource *res,
352 unsigned int level, unsigned int start_layer,
353 unsigned int num_layers, enum isl_aux_op op);
354
355 /**
356 * Prepare a miptree for access
357 *
358 * This function should be called prior to any access to miptree in order to
359 * perform any needed resolves.
360 *
361 * \param[in] start_level The first mip level to be accessed
362 *
363 * \param[in] num_levels The number of miplevels to be accessed or
364 * INTEL_REMAINING_LEVELS to indicate every level
365 * above start_level will be accessed
366 *
367 * \param[in] start_layer The first array slice or 3D layer to be accessed
368 *
369 * \param[in] num_layers The number of array slices or 3D layers be
370 * accessed or INTEL_REMAINING_LAYERS to indicate
371 * every layer above start_layer will be accessed
372 *
373 * \param[in] aux_supported Whether or not the access will support the
374 * miptree's auxiliary compression format; this
375 * must be false for uncompressed miptrees
376 *
377 * \param[in] fast_clear_supported Whether or not the access will support
378 * fast clears in the miptree's auxiliary
379 * compression format
380 */
381 void
382 iris_resource_prepare_access(struct iris_context *ice,
383 struct iris_resource *res,
384 uint32_t start_level, uint32_t num_levels,
385 uint32_t start_layer, uint32_t num_layers,
386 enum isl_aux_usage aux_usage,
387 bool fast_clear_supported);
388
389 /**
390 * Complete a write operation
391 *
392 * This function should be called after any operation writes to a miptree.
393 * This will update the miptree's compression state so that future resolves
394 * happen correctly. Technically, this function can be called before the
395 * write occurs but the caller must ensure that they don't interlace
396 * iris_resource_prepare_access and iris_resource_finish_write calls to
397 * overlapping layer/level ranges.
398 *
399 * \param[in] level The mip level that was written
400 *
401 * \param[in] start_layer The first array slice or 3D layer written
402 *
403 * \param[in] num_layers The number of array slices or 3D layers
404 * written or INTEL_REMAINING_LAYERS to indicate
405 * every layer above start_layer was written
406 *
407 * \param[in] written_with_aux Whether or not the write was done with
408 * auxiliary compression enabled
409 */
410 void
411 iris_resource_finish_write(struct iris_context *ice,
412 struct iris_resource *res, uint32_t level,
413 uint32_t start_layer, uint32_t num_layers,
414 enum isl_aux_usage aux_usage);
415
416 /** Get the auxiliary compression state of a miptree slice */
417 enum isl_aux_state
418 iris_resource_get_aux_state(const struct iris_resource *res,
419 uint32_t level, uint32_t layer);
420
421 /**
422 * Set the auxiliary compression state of a miptree slice range
423 *
424 * This function directly sets the auxiliary compression state of a slice
425 * range of a miptree. It only modifies data structures and does not do any
426 * resolves. This should only be called by code which directly performs
427 * compression operations such as fast clears and resolves. Most code should
428 * use iris_resource_prepare_access or iris_resource_finish_write.
429 */
430 void
431 iris_resource_set_aux_state(struct iris_context *ice,
432 struct iris_resource *res, uint32_t level,
433 uint32_t start_layer, uint32_t num_layers,
434 enum isl_aux_state aux_state);
435
436 /**
437 * Prepare a miptree for raw access
438 *
439 * This helper prepares the miptree for access that knows nothing about any
440 * sort of compression whatsoever. This is useful when mapping the surface or
441 * using it with the blitter.
442 */
443 static inline void
iris_resource_access_raw(struct iris_context * ice,struct iris_resource * res,uint32_t level,uint32_t layer,uint32_t num_layers,bool write)444 iris_resource_access_raw(struct iris_context *ice,
445 struct iris_resource *res,
446 uint32_t level, uint32_t layer,
447 uint32_t num_layers,
448 bool write)
449 {
450 iris_resource_prepare_access(ice, res, level, 1, layer, num_layers,
451 ISL_AUX_USAGE_NONE, false);
452 if (write) {
453 iris_resource_finish_write(ice, res, level, layer, num_layers,
454 ISL_AUX_USAGE_NONE);
455 }
456 }
457
458 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
459 const struct iris_resource *res,
460 enum isl_format view_fmt,
461 unsigned start_level,
462 unsigned num_levels);
463 void iris_resource_prepare_texture(struct iris_context *ice,
464 struct iris_resource *res,
465 enum isl_format view_format,
466 uint32_t start_level, uint32_t num_levels,
467 uint32_t start_layer, uint32_t num_layers);
468
469 enum isl_aux_usage iris_image_view_aux_usage(struct iris_context *ice,
470 const struct pipe_image_view *pview,
471 const struct shader_info *info);
472 enum isl_format iris_image_view_get_format(struct iris_context *ice,
473 const struct pipe_image_view *img);
474
475 bool iris_has_invalid_primary(const struct iris_resource *res,
476 unsigned start_level, unsigned num_levels,
477 unsigned start_layer, unsigned num_layers);
478
479 void iris_resource_check_level_layer(const struct iris_resource *res,
480 uint32_t level, uint32_t layer);
481
482 bool iris_resource_level_has_hiz(const struct intel_device_info *devinfo,
483 const struct iris_resource *res,
484 uint32_t level);
485
486 bool iris_sample_with_depth_aux(const struct intel_device_info *devinfo,
487 const struct iris_resource *res);
488
489 bool iris_has_color_unresolved(const struct iris_resource *res,
490 unsigned start_level, unsigned num_levels,
491 unsigned start_layer, unsigned num_layers);
492
493 bool iris_render_formats_color_compatible(enum isl_format a,
494 enum isl_format b,
495 union isl_color_value color,
496 bool clear_color_unknown);
497 void iris_resource_update_indirect_color(struct iris_batch *batch,
498 struct iris_resource *res);
499 enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
500 struct iris_resource *res,
501 enum isl_format render_fmt,
502 uint32_t level,
503 bool draw_aux_disabled);
504 void iris_resource_prepare_render(struct iris_context *ice,
505 struct iris_resource *res,
506 enum isl_format render_fmt, uint32_t level,
507 uint32_t start_layer, uint32_t layer_count,
508 enum isl_aux_usage aux_usage);
509 void iris_resource_finish_render(struct iris_context *ice,
510 struct iris_resource *res, uint32_t level,
511 uint32_t start_layer, uint32_t layer_count,
512 enum isl_aux_usage aux_usage);
513 #endif
514