1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/io.h>
4 #include <pc80/isa-dma.h>
5
6 /* DMA controller registers */
7 #define DMA1_CMD_REG 0x08 /* command register (w) */
8 #define DMA1_STAT_REG 0x08 /* status register (r) */
9 #define DMA1_REQ_REG 0x09 /* request register (w) */
10 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
11 #define DMA1_MODE_REG 0x0B /* mode register (w) */
12 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
13 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
14 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
15 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
16 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
17
18 #define DMA2_CMD_REG 0xD0 /* command register (w) */
19 #define DMA2_STAT_REG 0xD0 /* status register (r) */
20 #define DMA2_REQ_REG 0xD2 /* request register (w) */
21 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
22 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
23 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
24 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
25 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
26 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
27 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
28
29 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
30 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
31 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
32
33 #define DMA_AUTOINIT 0x10
34
isa_dma_init(void)35 void isa_dma_init(void)
36 {
37 /* slave at 0x00 - 0x0f */
38 /* master at 0xc0 - 0xdf */
39 /* 0x80 - 0x8f DMA page registers */
40 /* DMA: 0x00, 0x02, 0x4, 0x06 base address for DMA channel */
41 outb(0, DMA1_RESET_REG);
42 outb(0, DMA2_RESET_REG);
43 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
44 outb(0, DMA2_MASK_REG);
45 }
46