1 /*
2 * Copyright 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdint.h>
25 #include <inttypes.h>
26
27 #define __gen_address_type uint64_t
28 #define __gen_user_data void
29
30 static uint64_t
__gen_combine_address(void * data,void * loc,uint64_t addr,uint32_t delta)31 __gen_combine_address(__attribute__((unused)) void *data,
32 __attribute__((unused)) void *loc, uint64_t addr,
33 uint32_t delta)
34 {
35 return addr + delta;
36 }
37
38 #include "genxml/gen_macros.h"
39 #include "genxml/genX_pack.h"
40 #include "util/log.h"
41
42 #include "isl_priv.h"
43 #include "isl_genX_helpers.h"
44
45 #if GFX_VER >= 8
46 static const uint8_t isl_encode_tiling[] = {
47 [ISL_TILING_LINEAR] = LINEAR,
48 [ISL_TILING_X] = XMAJOR,
49 #if GFX_VERx10 >= 125
50 [ISL_TILING_4] = TILE4,
51 [ISL_TILING_64] = TILE64,
52 [ISL_TILING_64_XE2] = TILE64,
53 #else
54 [ISL_TILING_Y0] = YMAJOR,
55 [ISL_TILING_ICL_Yf] = YMAJOR,
56 [ISL_TILING_ICL_Ys] = YMAJOR,
57 [ISL_TILING_SKL_Yf] = YMAJOR,
58 [ISL_TILING_SKL_Ys] = YMAJOR,
59 #endif /* GFX_VERx10 < 125 */
60 #if GFX_VER <= 11
61 [ISL_TILING_W] = WMAJOR,
62 #endif
63 };
64 #endif
65
66 #if GFX_VER >= 9 && GFX_VERx10 <= 120
67 static const uint8_t isl_tiling_encode_trmode[] = {
68 [ISL_TILING_Y0] = NONE,
69 [ISL_TILING_SKL_Yf] = TILEYF,
70 [ISL_TILING_SKL_Ys] = TILEYS,
71 [ISL_TILING_ICL_Yf] = TILEYF,
72 [ISL_TILING_ICL_Ys] = TILEYS,
73 };
74 #endif
75
76 #if GFX_VER >= 7
77 static const uint32_t isl_encode_multisample_layout[] = {
78 [ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS,
79 [ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL,
80 [ISL_MSAA_LAYOUT_ARRAY] = MSFMT_MSS,
81 };
82 #endif
83
84 #if GFX_VER >= 20
85 static const uint32_t isl_encode_aux_mode[] = {
86 [ISL_AUX_USAGE_NONE] = AUX_NONE,
87 [ISL_AUX_USAGE_MC] = AUX_NONE,
88 [ISL_AUX_USAGE_MCS] = AUX_MCS,
89 [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS,
90 [ISL_AUX_USAGE_STC_CCS] = AUX_NONE,
91 [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_NONE,
92 };
93 #elif GFX_VER >= 12
94 static const uint32_t isl_encode_aux_mode[] = {
95 [ISL_AUX_USAGE_NONE] = AUX_NONE,
96 [ISL_AUX_USAGE_MC] = AUX_NONE,
97 [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
98 [ISL_AUX_USAGE_FCV_CCS_E] = AUX_CCS_E,
99 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
100 [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
101 [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
102 [ISL_AUX_USAGE_STC_CCS] = AUX_CCS_E,
103 };
104 #elif GFX_VER >= 9
105 static const uint32_t isl_encode_aux_mode[] = {
106 [ISL_AUX_USAGE_NONE] = AUX_NONE,
107 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
108 [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
109 [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
110 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
111 };
112 #elif GFX_VER >= 8
113 static const uint32_t isl_encode_aux_mode[] = {
114 [ISL_AUX_USAGE_NONE] = AUX_NONE,
115 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
116 [ISL_AUX_USAGE_MCS] = AUX_MCS,
117 [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
118 };
119 #endif
120
121 static uint8_t
get_surftype(enum isl_surf_dim dim,isl_surf_usage_flags_t usage)122 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
123 {
124 switch (dim) {
125 default:
126 unreachable("bad isl_surf_dim");
127 case ISL_SURF_DIM_1D:
128 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
129 return SURFTYPE_1D;
130 case ISL_SURF_DIM_2D:
131 if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
132 (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
133 /* We need SURFTYPE_CUBE to make cube sampling work */
134 return SURFTYPE_CUBE;
135 } else {
136 /* Everything else (render and storage) treat cubes as plain
137 * 2D array textures
138 */
139 return SURFTYPE_2D;
140 }
141 case ISL_SURF_DIM_3D:
142 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
143 return SURFTYPE_3D;
144 }
145 }
146
147 #if GFX_VERx10 >= 125
148 static uint8_t
get_media_compression_format(enum isl_format format,enum isl_format lowered_format)149 get_media_compression_format(enum isl_format format,
150 enum isl_format lowered_format)
151 {
152 const uint32_t plane_bpb = isl_format_get_layout(lowered_format)->bpb;
153
154 /* From Bspec 43868, Enumeration_MediaCompressionFormat:
155 *
156 * Luma P010 has MSB of 0 while chroma P010 has MSB of 1.
157 * Luma P016 has MSB of 0 while chroma P016 has MSB of 1.
158 * Luma NV12 has MSB of 0 while chroma NV12 has MSB of 1.
159 */
160 switch (format) {
161 case ISL_FORMAT_PLANAR_420_8: /* NV12 */
162 assert(plane_bpb == 8 || plane_bpb == 16);
163 assert((isl_format_get_aux_map_encoding(format) & 0xf0) == 0);
164
165 /* drm_fourcc.h defines the chroma plane of NV12 as 16-bpb */
166 return (plane_bpb == 16) << 4 | isl_format_get_aux_map_encoding(format);
167 case ISL_FORMAT_PLANAR_420_10:
168 case ISL_FORMAT_PLANAR_420_12:
169 case ISL_FORMAT_PLANAR_420_16:
170 assert(plane_bpb == 16 || plane_bpb == 32);
171 assert((isl_format_get_aux_map_encoding(format) & 0xf0) == 0);
172
173 /* drm_fourcc.h defines the chroma plane of P01X as 32-bpb */
174 return (plane_bpb == 32) << 4 | isl_format_get_aux_map_encoding(format);
175 default:
176 return isl_format_get_aux_map_encoding(format);
177 }
178 }
179 #endif
180
181 static struct isl_swizzle
format_swizzle(enum isl_format format)182 format_swizzle(enum isl_format format)
183 {
184 struct isl_swizzle fmt_swz = {};
185
186 fmt_swz.r = isl_format_has_color_component(format, 0) ?
187 ISL_CHANNEL_SELECT_RED :
188 ISL_CHANNEL_SELECT_ZERO;
189
190 fmt_swz.g = isl_format_has_color_component(format, 1) ?
191 ISL_CHANNEL_SELECT_GREEN :
192 ISL_CHANNEL_SELECT_ZERO;
193
194 fmt_swz.b = isl_format_has_color_component(format, 2) ?
195 ISL_CHANNEL_SELECT_BLUE :
196 ISL_CHANNEL_SELECT_ZERO;
197
198 fmt_swz.a = isl_format_has_color_component(format, 3) ?
199 ISL_CHANNEL_SELECT_ALPHA :
200 ISL_CHANNEL_SELECT_ONE;
201
202 return fmt_swz;
203 }
204
205 static struct isl_swizzle
isl_get_shader_channel_select(enum isl_format format,struct isl_swizzle view_swizzle)206 isl_get_shader_channel_select(enum isl_format format,
207 struct isl_swizzle view_swizzle)
208 {
209 /* Currently we map both FXT1_RGB/FXT1_RGBA to single FXT1 format
210 * (supporting both 3/4 component) as a result we can use RGBA swizzle as it
211 * is.
212 */
213 if (format == ISL_FORMAT_FXT1)
214 return view_swizzle;
215
216 /* Bspec 12486: RENDER_SURFACE_STATE::Shader Channel Select Red
217 *
218 * "The output channel is undefined if the source is to a channel is not
219 * present for the current surface format. For example, If the surface
220 * format is R16_float and the shader channel select green specifies
221 * green as the source the output is undefined. It should instead select
222 * 0 which is the default for a missing color channel."
223 *
224 * Bspec 57023: RENDER_SURFACE_STATE::Shader Channel Select Red
225 *
226 * "For channels not present in the surface format, the corresponding
227 * Surface Channel Select is either SCS_ZERO or SCS_ONE."
228 *
229 * This restriction applies to alpha channel as well if associated resource
230 * is not used as render target.
231 */
232 return isl_swizzle_compose(view_swizzle, format_swizzle(format));
233 }
234
235 void
isl_genX(surf_fill_state_s)236 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
237 const struct isl_surf_fill_state_info *restrict info)
238 {
239 #ifndef NDEBUG
240 isl_surf_usage_flags_t _base_usage =
241 info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
242 ISL_SURF_USAGE_TEXTURE_BIT |
243 ISL_SURF_USAGE_STORAGE_BIT);
244 /* They may only specify one of the above bits at a time */
245 assert(__builtin_popcount(_base_usage) == 1);
246 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
247 assert((info->view->usage & ~(ISL_SURF_USAGE_CUBE_BIT |
248 ISL_SURF_USAGE_PROTECTED_BIT)) ==
249 _base_usage);
250 #endif
251
252 if (info->surf->dim == ISL_SURF_DIM_3D) {
253 assert(info->view->base_array_layer + info->view->array_len <=
254 info->surf->logical_level0_px.depth);
255 } else {
256 assert(info->view->base_array_layer + info->view->array_len <=
257 info->surf->logical_level0_px.array_len);
258 }
259
260 struct GENX(RENDER_SURFACE_STATE) s = { 0 };
261
262 s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
263
264 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
265 assert(isl_format_supports_rendering(dev->info, info->view->format));
266 else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
267 assert(isl_format_supports_sampling(dev->info, info->view->format));
268
269 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
270 *
271 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
272 * format if the Surface Type is SURFTYPE_1D
273 */
274 if (info->surf->dim == ISL_SURF_DIM_1D)
275 assert(!isl_format_is_compressed(info->view->format));
276
277 if (isl_format_is_compressed(info->surf->format)) {
278 /* You're not allowed to make a view of a compressed format with any
279 * format other than the surface format. None of the userspace APIs
280 * allow for this directly and doing so would mess up a number of
281 * surface parameters such as Width, Height, and alignments. Ideally,
282 * we'd like to assert that the two formats match. However, we have an
283 * S3TC workaround that requires us to do reinterpretation. So assert
284 * that they're at least the same bpb and block size.
285 */
286 ASSERTED const struct isl_format_layout *surf_fmtl =
287 isl_format_get_layout(info->surf->format);
288 ASSERTED const struct isl_format_layout *view_fmtl =
289 isl_format_get_layout(info->view->format);
290
291 assert(surf_fmtl->bpb == view_fmtl->bpb);
292
293 /* We could be attempting to upload blocks of compressed data via an
294 * uncompressed view, blocksize will not match there.
295 */
296 if (isl_format_is_compressed(info->view->format)) {
297 assert(surf_fmtl->bw == view_fmtl->bw);
298 assert(surf_fmtl->bh == view_fmtl->bh);
299 }
300 }
301
302 s.SurfaceFormat = info->view->format;
303
304 #if GFX_VER >= 12
305 /* The BSpec description of this field says:
306 *
307 * "This bit field, when set, indicates if the resource is created as
308 * Depth/Stencil resource."
309 *
310 * "SW must set this bit for any resource that was created with
311 * Depth/Stencil resource flag. Setting this bit allows HW to properly
312 * interpret the data-layout for various cases. For any resource that's
313 * created without Depth/Stencil resource flag, it must be reset."
314 *
315 * Even though the docs for this bit seem to imply that it's required for
316 * anything which might have been used for depth/stencil, empirical
317 * evidence suggests that it only affects CCS compression usage. There are
318 * a few things which back this up:
319 *
320 * 1. The docs are also pretty clear that this bit was added as part
321 * of enabling Gfx12 depth/stencil lossless compression.
322 *
323 * 2. The only new difference between depth/stencil and color images on
324 * Gfx12 (where the bit was added) is how they treat CCS compression.
325 * All other differences such as alignment requirements and MSAA layout
326 * are already covered by other bits.
327 *
328 * Under these assumptions, it makes sense for ISL to model this bit as
329 * being an extension of AuxiliarySurfaceMode where STC_CCS and HIZ_CCS_WT
330 * are indicated by AuxiliarySurfaceMode == CCS_E and DepthStencilResource
331 * == true.
332 */
333 s.DepthStencilResource = info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
334 info->aux_usage == ISL_AUX_USAGE_STC_CCS;
335 #endif
336
337 #if GFX_VER <= 5
338 s.ColorBufferComponentWriteDisables = info->write_disables;
339 s.ColorBlendEnable = info->blend_enable;
340 #else
341 assert(info->write_disables == 0);
342 #endif
343
344 #if GFX_VERx10 == 75
345 s.IntegerSurfaceFormat =
346 isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
347 #endif
348
349 assert(info->surf->logical_level0_px.width > 0 &&
350 info->surf->logical_level0_px.height > 0);
351
352 s.Width = info->surf->logical_level0_px.width - 1;
353 s.Height = info->surf->logical_level0_px.height - 1;
354
355 /* In the gfx6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
356 * (Surface Arrays For all surfaces other than separate stencil buffer):
357 *
358 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
359 * calculated in the equation above , for every other odd Surface Height
360 * starting from 1 i.e. 1,5,9,13"
361 *
362 * Since this Qpitch errata only impacts the sampler, we have to adjust the
363 * input for the rendering surface to achieve the same qpitch. For the
364 * affected heights, we increment the height by 1 for the rendering
365 * surface.
366 */
367 if (GFX_VER == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
368 info->surf->samples > 1 &&
369 (info->surf->logical_level0_px.height % 4) == 1)
370 s.Height++;
371
372 switch (s.SurfaceType) {
373 case SURFTYPE_1D:
374 case SURFTYPE_2D:
375 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
376 *
377 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
378 * must be set to zero if this surface is used with sampling engine
379 * messages."
380 *
381 * This restriction appears to exist only on Ivy Bridge.
382 */
383 if (GFX_VERx10 == 70 && !ISL_DEV_IS_BAYTRAIL(dev) &&
384 (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
385 info->surf->samples > 1)
386 assert(info->view->base_array_layer == 0);
387
388 s.MinimumArrayElement = info->view->base_array_layer;
389
390 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
391 *
392 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
393 * by one for each increase from zero of Minimum Array Element. For
394 * example, if Minimum Array Element is set to 1024 on a 2D surface,
395 * the range of this field is reduced to [0,1023].
396 *
397 * In other words, 'Depth' is the number of array layers.
398 */
399 s.Depth = info->view->array_len - 1;
400
401 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
402 *
403 * For Render Target and Typed Dataport 1D and 2D Surfaces:
404 * This field must be set to the same value as the Depth field.
405 */
406 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
407 ISL_SURF_USAGE_STORAGE_BIT))
408 s.RenderTargetViewExtent = s.Depth;
409 break;
410 case SURFTYPE_CUBE:
411 s.MinimumArrayElement = info->view->base_array_layer;
412 /* Same as SURFTYPE_2D, but divided by 6 */
413 s.Depth = info->view->array_len / 6 - 1;
414 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
415 ISL_SURF_USAGE_STORAGE_BIT))
416 s.RenderTargetViewExtent = s.Depth;
417 break;
418 case SURFTYPE_3D:
419 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
420 *
421 * If the volume texture is MIP-mapped, this field specifies the
422 * depth of the base MIP level.
423 */
424 s.Depth = info->surf->logical_level0_px.depth - 1;
425
426 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
427 *
428 * For Render Target and Typed Dataport 3D Surfaces: This field
429 * indicates the extent of the accessible 'R' coordinates minus 1 on
430 * the LOD currently being rendered to.
431 *
432 * The docs specify that this only matters for render targets and
433 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the
434 * Depth field has more bits than RenderTargetViewExtent so we can have
435 * textures with more levels than we can render to. In order to prevent
436 * assert-failures in the packing function below, we only set the field
437 * when it's actually going to be used by the hardware.
438 *
439 * The MinimumArrayElement field is ignored by all hardware
440 * prior to Sky Lake when texturing, and drivers are responsible
441 * for validating the correctness of this parameter.
442 * KHR_gl_texture_3D_image requires this functionality.
443 */
444 s.MinimumArrayElement = info->view->base_array_layer;
445 s.RenderTargetViewExtent = info->view->array_len - 1;
446 break;
447 default:
448 unreachable("bad SurfaceType");
449 }
450
451 #if GFX_VER >= 7
452 if (INTEL_NEEDS_WA_1806565034) {
453 /* Wa_1806565034:
454 *
455 * "Only set SurfaceArray if arrayed surface is > 1."
456 *
457 * Since this is a performance workaround, we only enable it when robust
458 * image access is disabled. Otherwise layered robust access is not
459 * specification compliant.
460 */
461 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
462 (info->robust_image_access || info->view->array_len > 1);
463 } else {
464 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
465 }
466 #endif
467
468 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
469 /* For render target surfaces, the hardware interprets field
470 * MIPCount/LOD as LOD. The Broadwell PRM says:
471 *
472 * MIPCountLOD defines the LOD that will be rendered into.
473 * SurfaceMinLOD is ignored.
474 */
475 s.MIPCountLOD = info->view->base_level;
476 s.SurfaceMinLOD = 0;
477 } else {
478 /* For non render target surfaces, the hardware interprets field
479 * MIPCount/LOD as MIPCount. The range of levels accessible by the
480 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
481 */
482 s.SurfaceMinLOD = info->view->base_level;
483 s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
484 }
485
486 #if GFX_VER >= 9
487 s.MipTailStartLOD = info->surf->miptail_start_level;
488 #endif
489
490 #if GFX_VERx10 >= 125
491 /* Setting L1 caching policy to Write-back mode. */
492 s.L1CacheControl = L1CC_WB;
493 #endif
494
495 #if GFX_VER >= 6
496 const struct isl_extent3d image_align =
497 isl_get_image_alignment(info->surf);
498 s.SurfaceVerticalAlignment = isl_encode_valign(image_align.height);
499 #if GFX_VER >= 7
500 s.SurfaceHorizontalAlignment = isl_encode_halign(image_align.width);
501 #endif
502 #endif
503
504 if (info->surf->dim_layout == ISL_DIM_LAYOUT_GFX9_1D) {
505 /* For gfx9 1-D textures, surface pitch is ignored */
506 s.SurfacePitch = 0;
507 } else {
508 s.SurfacePitch = info->surf->row_pitch_B - 1;
509 }
510
511 #if GFX_VER >= 8
512 s.SurfaceQPitch = isl_get_qpitch(info->surf) >> 2;
513 #elif GFX_VER == 7
514 s.SurfaceArraySpacing = info->surf->array_pitch_span ==
515 ISL_ARRAY_PITCH_SPAN_COMPACT;
516 #endif
517
518 #if GFX_VER >= 9 && GFX_VERx10 <= 120
519 assert(GFX_VER < 12 || info->surf->tiling != ISL_TILING_W);
520
521 /* From the SKL+ PRMs, RENDER_SURFACE_STATE:TileMode,
522 *
523 * If Surface Format is ASTC*, this field must be TILEMODE_YMAJOR.
524 */
525 if (isl_format_get_layout(info->view->format)->txc == ISL_TXC_ASTC)
526 assert(isl_tiling_is_any_y(info->surf->tiling));
527
528 s.TileMode = isl_encode_tiling[info->surf->tiling];
529 if (isl_tiling_is_std_y(info->surf->tiling))
530 s.TiledResourceMode = isl_tiling_encode_trmode[info->surf->tiling];
531 #elif GFX_VER >= 8
532 assert(isl_format_get_layout(info->view->format)->txc != ISL_TXC_ASTC);
533 assert(!isl_tiling_is_std_y(info->surf->tiling));
534 s.TileMode = isl_encode_tiling[info->surf->tiling];
535 #else
536 s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
537 s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
538 TILEWALK_XMAJOR,
539 #endif
540
541 #if GFX_VER >= 8
542 s.RenderCacheReadWriteMode = WriteOnlyCache;
543 #else
544 s.RenderCacheReadWriteMode = 0;
545 #endif
546
547 #if GFX_VER >= 11 && GFX_VERx10 < 125
548 /* From the TGL PRM,
549 *
550 * This bit should never be programmed to 0
551 */
552 s.EnableUnormPathInColorPipe = true;
553 #endif
554
555 s.CubeFaceEnablePositiveZ = 1;
556 s.CubeFaceEnableNegativeZ = 1;
557 s.CubeFaceEnablePositiveY = 1;
558 s.CubeFaceEnableNegativeY = 1;
559 s.CubeFaceEnablePositiveX = 1;
560 s.CubeFaceEnableNegativeX = 1;
561
562 #if GFX_VER >= 6
563 /* From the Broadwell PRM for "Number of Multisamples":
564 *
565 * "If this field is any value other than MULTISAMPLECOUNT_1, Surface
566 * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero."
567 *
568 * This is fine because no 3D API allows multisampling and mipmapping at
569 * the same time.
570 */
571 if (info->surf->samples > 1) {
572 assert(info->view->min_lod_clamp == 0);
573 assert(info->view->base_level == 0);
574 assert(info->view->levels == 1);
575 }
576 s.NumberofMultisamples = ffs(info->surf->samples) - 1;
577 #if GFX_VER >= 7
578 s.MultisampledSurfaceStorageFormat =
579 isl_encode_multisample_layout[info->surf->msaa_layout];
580 #endif
581 #endif
582
583 #if GFX_VER >= 7
584 s.ResourceMinLOD = info->view->min_lod_clamp;
585
586 #if GFX_VERx10 >= 200
587 s.EnableSamplerRoutetoLSC =
588 isl_format_support_sampler_route_to_lsc(info->view->format) &&
589 s.SurfaceType == SURFTYPE_2D && info->view->array_len == 1;
590
591 /* Wa_14018471104:
592 * For APIs that use ResourceMinLod, do the following: (remains same as before)
593 * 1. If ResourceMinLod == 0.0 then **Enable Sampler Route to LSC**
594 * in RENDER SURFACE STATE to 1 else to 0
595 */
596 #if INTEL_NEEDS_WA_14018471104
597 s.EnableSamplerRoutetoLSC &= info->view->min_lod_clamp == 0;
598 #endif
599
600 /* Per application override. */
601 s.EnableSamplerRoutetoLSC &= dev->sampler_route_to_lsc;
602 #endif /* if GFX_VERx10 >= 200 */
603
604 #else
605 assert(info->view->min_lod_clamp == 0);
606 #endif
607
608 #if (GFX_VERx10 >= 75)
609 struct isl_swizzle swz = info->view->swizzle;
610 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
611 assert(isl_swizzle_supports_rendering(dev->info, swz));
612 } else {
613 swz = isl_get_shader_channel_select(info->view->format, swz);
614 }
615
616 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) swz.r;
617 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) swz.g;
618 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) swz.b;
619 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) swz.a;
620 #else
621 assert(isl_swizzle_is_identity(info->view->swizzle));
622 #endif
623
624 assert(info->address % info->surf->alignment_B == 0);
625 s.SurfaceBaseAddress = info->address;
626
627 #if GFX_VER >= 6
628 s.MOCS = info->mocs;
629 #endif
630
631 #if GFX_VERx10 >= 45
632 if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
633 /* There are fairly strict rules about when the offsets can be used.
634 * These are mostly taken from the Sky Lake PRM documentation for
635 * RENDER_SURFACE_STATE.
636 */
637 assert(info->surf->tiling != ISL_TILING_LINEAR);
638 assert(info->surf->dim == ISL_SURF_DIM_2D);
639 assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
640 assert(info->surf->levels == 1);
641 assert(info->surf->logical_level0_px.array_len == 1);
642 assert(info->aux_usage == ISL_AUX_USAGE_NONE);
643
644 if (GFX_VER >= 8) {
645 /* Broadwell added more rules. */
646 assert(info->surf->samples == 1);
647 if (isl_format_get_layout(info->view->format)->bpb == 8)
648 assert(info->x_offset_sa % 16 == 0);
649 if (isl_format_get_layout(info->view->format)->bpb == 16)
650 assert(info->x_offset_sa % 8 == 0);
651 }
652
653 #if GFX_VER >= 7
654 s.SurfaceArray = false;
655 #endif
656 }
657
658 const unsigned x_div = 4;
659 const unsigned y_div = GFX_VER >= 8 ? 4 : 2;
660 assert(info->x_offset_sa % x_div == 0);
661 assert(info->y_offset_sa % y_div == 0);
662 s.XOffset = info->x_offset_sa / x_div;
663 s.YOffset = info->y_offset_sa / y_div;
664 #else
665 assert(info->x_offset_sa == 0);
666 assert(info->y_offset_sa == 0);
667 #endif
668
669 #if GFX_VER >= 7
670 if (info->aux_usage != ISL_AUX_USAGE_NONE) {
671 /* Check valid aux usages per-gen */
672 if (GFX_VER >= 12) {
673 assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
674 info->aux_usage == ISL_AUX_USAGE_CCS_E ||
675 info->aux_usage == ISL_AUX_USAGE_FCV_CCS_E ||
676 info->aux_usage == ISL_AUX_USAGE_MC ||
677 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
678 info->aux_usage == ISL_AUX_USAGE_MCS_CCS ||
679 info->aux_usage == ISL_AUX_USAGE_STC_CCS);
680 } else if (GFX_VER >= 9) {
681 assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
682 info->aux_usage == ISL_AUX_USAGE_MCS ||
683 info->aux_usage == ISL_AUX_USAGE_CCS_D ||
684 info->aux_usage == ISL_AUX_USAGE_CCS_E);
685 } else if (GFX_VER >= 8) {
686 assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
687 info->aux_usage == ISL_AUX_USAGE_MCS ||
688 info->aux_usage == ISL_AUX_USAGE_CCS_D);
689 } else if (GFX_VER >= 7) {
690 assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
691 info->aux_usage == ISL_AUX_USAGE_CCS_D);
692 }
693
694 /* The docs don't appear to say anything whatsoever about compression
695 * and the data port. Testing seems to indicate that the data port
696 * completely ignores the AuxiliarySurfaceMode field.
697 *
698 * On gfx12 HDC supports compression.
699 */
700 if (GFX_VER < 12)
701 assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
702
703 if (isl_surf_usage_is_depth(info->surf->usage))
704 assert(isl_aux_usage_has_hiz(info->aux_usage));
705
706 if (isl_surf_usage_is_stencil(info->surf->usage))
707 assert(info->aux_usage == ISL_AUX_USAGE_STC_CCS);
708
709 if (isl_aux_usage_has_hiz(info->aux_usage)) {
710 /* For Gfx8-11, there are some restrictions around sampling from HiZ.
711 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
712 * say:
713 *
714 * "If this field is set to AUX_HIZ, Number of Multisamples must
715 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
716 *
717 * On Gfx12, the docs are a bit less obvious but the restriction is
718 * the same. The limitation isn't called out explicitly but the docs
719 * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode
720 * say:
721 *
722 * "If Number of multisamples > 1, programming this value means
723 * MSAA compression is enabled for that surface. Auxiliary surface
724 * is MSC with tile y."
725 *
726 * Since this interpretation ignores whether the surface is
727 * depth/stencil or not and since multisampled depth buffers use
728 * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
729 * compression, this means that we can't even specify MSAA depth CCS
730 * in RENDER_SURFACE_STATE::AuxiliarySurfaceMode.
731 *
732 * On Xe2+, the above restriction is not mentioned in the
733 * RENDER_SURFACE_STATE::AuxiliarySurfaceMode.
734 *
735 * Bspec 57023 (r58975)
736 */
737 assert(GFX_VER >= 20 || info->surf->samples == 1);
738
739 /* Prior to Gfx12, the dimension must not be 3D */
740 if (info->aux_usage == ISL_AUX_USAGE_HIZ)
741 assert(info->surf->dim != ISL_SURF_DIM_3D);
742
743 /* The format must be one of the following: */
744 switch (info->view->format) {
745 case ISL_FORMAT_R32_FLOAT:
746 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
747 case ISL_FORMAT_R16_UNORM:
748 break;
749 default:
750 assert(!"Incompatible HiZ Sampling format");
751 break;
752 }
753 }
754
755 #if GFX_VERx10 >= 125
756 if (info->aux_usage == ISL_AUX_USAGE_MC) {
757 s.CompressionFormat =
758 get_media_compression_format(info->mc_format, info->surf->format);
759 } else {
760 s.CompressionFormat =
761 isl_get_render_compression_format(info->surf->format);
762 }
763 #endif
764 #if GFX_VER == 12
765 s.MemoryCompressionEnable = info->aux_usage == ISL_AUX_USAGE_MC;
766
767 /* The Tiger Lake PRM for RENDER_SURFACE_STATE::DecompressInL3 says:
768 *
769 * When this field is set to 1h, the associated compressible surface,
770 * when accessed by sampler and data-port, will be uncompressed in
771 * L3. If the surface is not compressible, this bit field is ignored.
772 *
773 * The sampler's decompressor seems to lack support for some types of
774 * format re-interpretation. Use the more capable decompressor for these
775 * cases.
776 */
777 s.DecompressInL3 =
778 !isl_formats_have_same_bits_per_channel(info->surf->format,
779 info->view->format);
780 #endif
781 #if GFX_VER >= 9
782 /* Some CCS aux usages have format restrictions. The Skylake PRM doc for
783 * RENDER_SURFACE_STATE::AuxiliarySurfaceMode says:
784 *
785 * If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_E setting
786 * is only allowed if Surface Format is supported for Render Target
787 * Compression. This setting enables render target compression.
788 *
789 * If CCS_E is in use, the format must support it.
790 */
791 if (isl_aux_usage_has_ccs_e(info->aux_usage))
792 assert(isl_format_supports_ccs_e(dev->info, info->view->format));
793
794 /* It also says:
795 *
796 * If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D setting
797 * is only allowed if Surface Format supported for Fast Clear. In
798 * addition, if the surface is bound to the sampling engine, Surface
799 * Format must be supported for Render Target Compression for
800 * surfaces bound to the sampling engine. For render target surfaces,
801 * this setting disables render target compression. For sampling
802 * engine surfaces, this mode behaves the same as AUX_CCS_E.
803 *
804 * If CCS_D is in use while rendering, the format must support it. If
805 * it's in use while sampling, the format must support CCS_E.
806 */
807 if (info->aux_usage == ISL_AUX_USAGE_CCS_D) {
808 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
809 assert(isl_format_supports_ccs_d(dev->info, info->view->format));
810 } else {
811 assert(info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT);
812 assert(isl_format_supports_ccs_e(dev->info, info->view->format));
813 }
814 }
815 #endif
816 #if GFX_VER >= 8
817 s.AuxiliarySurfaceMode = isl_encode_aux_mode[info->aux_usage];
818 #else
819 s.MCSEnable = true;
820 #endif
821 }
822
823 /* The auxiliary buffer info is filled when it's usable by the HW.
824 *
825 * Starting with Gfx12, the only form of compression that can be used
826 * with RENDER_SURFACE_STATE which requires an aux surface is MCS.
827 * HiZ still requires a surface but the HiZ surface can only be
828 * accessed through 3DSTATE_HIER_DEPTH_BUFFER.
829 *
830 * On all earlier hardware, an aux surface is required for all forms
831 * of compression.
832 */
833 if ((GFX_VER < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) ||
834 (GFX_VER >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) {
835
836 assert(info->aux_surf != NULL);
837
838 struct isl_tile_info tile_info;
839 isl_surf_get_tile_info(info->aux_surf, &tile_info);
840 uint32_t pitch_in_tiles =
841 info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
842
843 assert(info->aux_address % info->aux_surf->alignment_B == 0);
844 s.AuxiliarySurfaceBaseAddress = info->aux_address;
845 s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
846
847 #if GFX_VER >= 8
848 /* Auxiliary surfaces in ISL have compressed formats but the hardware
849 * doesn't expect our definition of the compression, it expects qpitch
850 * in units of samples on the main surface.
851 */
852 s.AuxiliarySurfaceQPitch =
853 isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
854 #endif
855 }
856 #endif
857
858 #if GFX_VER >= 8 && GFX_VER < 11
859 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
860 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
861 *
862 * This bit must be set for the following surface types: BC2_UNORM
863 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
864 */
865 if (GFX_VER >= 9 || dev->info->platform == INTEL_PLATFORM_CHV) {
866 switch (info->view->format) {
867 case ISL_FORMAT_BC2_UNORM:
868 case ISL_FORMAT_BC3_UNORM:
869 case ISL_FORMAT_BC5_UNORM:
870 case ISL_FORMAT_BC5_SNORM:
871 case ISL_FORMAT_BC7_UNORM:
872 s.SamplerL2BypassModeDisable = true;
873 break;
874 default:
875 /* From the SKL PRM, Programming Note under Sampler Output Channel
876 * Mapping:
877 *
878 * If a surface has an associated HiZ Auxiliary surface, the
879 * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
880 * must be set.
881 */
882 if (GFX_VER >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
883 s.SamplerL2BypassModeDisable = true;
884 break;
885 }
886 }
887 #endif
888
889 if (isl_aux_usage_has_fast_clears(info->aux_usage)) {
890 if (info->use_clear_address) {
891 #if GFX_VER > 10 && GFX_VER < 20
892 s.ClearValueAddressEnable = true;
893 s.ClearValueAddress = info->clear_address;
894 #else
895 unreachable("Only Gfx11 and Gfx12 support indirect clear colors");
896 #endif
897 }
898
899 #if GFX_VER >= 20
900 /* According to Bspec 57023 >> RENDER_SURFACE_STATE, the clear value
901 * address and explicit clear value are removed since Xe2.
902 */
903 assert(!info->use_clear_address);
904 #elif GFX_VER >= 12
905 assert(info->use_clear_address);
906 #elif GFX_VER >= 9
907 if (!info->use_clear_address) {
908 s.RedClearColor = info->clear_color.u32[0];
909 s.GreenClearColor = info->clear_color.u32[1];
910 s.BlueClearColor = info->clear_color.u32[2];
911 s.AlphaClearColor = info->clear_color.u32[3];
912 }
913 #elif GFX_VER >= 7
914 /* Prior to Sky Lake, we only have one bit for the clear color which
915 * gives us 0 or 1 in whatever the surface's format happens to be.
916 */
917 if (isl_format_has_int_channel(info->view->format)) {
918 for (unsigned i = 0; i < 4; i++) {
919 assert(info->clear_color.u32[i] == 0 ||
920 info->clear_color.u32[i] == 1);
921 }
922 s.RedClearColor = info->clear_color.u32[0] != 0;
923 s.GreenClearColor = info->clear_color.u32[1] != 0;
924 s.BlueClearColor = info->clear_color.u32[2] != 0;
925 s.AlphaClearColor = info->clear_color.u32[3] != 0;
926 } else {
927 for (unsigned i = 0; i < 4; i++) {
928 assert(info->clear_color.f32[i] == 0.0f ||
929 info->clear_color.f32[i] == 1.0f);
930 }
931 s.RedClearColor = info->clear_color.f32[0] != 0.0f;
932 s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
933 s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
934 s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
935 }
936 #endif
937 }
938
939 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
940 }
941
942 void
isl_genX(buffer_fill_state_s)943 isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
944 const struct isl_buffer_fill_state_info *restrict info)
945 {
946 uint64_t buffer_size = info->size_B;
947
948 /* Uniform and Storage buffers need to have surface size not less that the
949 * aligned 32-bit size of the buffer. To calculate the array length on
950 * unsized arrays in StorageBuffer the last 2 bits store the padding size
951 * added to the surface, so we can calculate latter the original buffer
952 * size to know the number of elements.
953 *
954 * surface_size = isl_align(buffer_size, 4) +
955 * (isl_align(buffer_size) - buffer_size)
956 *
957 * buffer_size = (surface_size & ~3) - (surface_size & 3)
958 */
959 if ((info->format == ISL_FORMAT_RAW ||
960 info->stride_B < isl_format_get_layout(info->format)->bpb / 8) &&
961 !info->is_scratch) {
962 assert(info->stride_B == 1);
963 uint64_t aligned_size = isl_align(buffer_size, 4);
964 buffer_size = aligned_size + (aligned_size - buffer_size);
965 }
966
967 uint32_t num_elements = buffer_size / info->stride_B;
968
969 assert(num_elements > 0);
970 if (info->format == ISL_FORMAT_RAW) {
971 assert(num_elements <= dev->max_buffer_size);
972 } else {
973 /* From the IVB PRM, SURFACE_STATE::Height,
974 *
975 * For typed buffer and structured buffer surfaces, the number
976 * of entries in the buffer ranges from 1 to 2^27.
977 *
978 * We could assert(num_elements <= (1 << 27)) here, but some DX12 games
979 * misbehave and there's nothing either vkd3d or Anv can do about it.
980 * Therefore we just allow those cases to happen in order to avoid
981 * crashing or further breaking the applications.
982 *
983 * Applications causing this issue generally ignore
984 * PhysicalDevice::maxTexelBufferElements, leading them to disrespect
985 * restrictions such as:
986 * VUID-VkDescriptorGetInfoEXT-type-09427
987 * VUID-VkDescriptorGetInfoEXT-type-09428
988 * VUID-VkBufferViewCreateInfo-range-00930
989 * VUID-VkBufferViewCreateInfo-range-04059
990 */
991 if (num_elements > (1 << 27)) {
992 mesa_logw("%s: num_elements is too big: %u (buffer size: %"PRIu64")\n",
993 __func__, num_elements, buffer_size);
994 num_elements = 1 << 27;
995 }
996 }
997
998 struct GENX(RENDER_SURFACE_STATE) s = { 0, };
999
1000 s.SurfaceFormat = info->format;
1001
1002 s.SurfaceType = SURFTYPE_BUFFER;
1003 #if GFX_VERx10 >= 125
1004 if (info->is_scratch) {
1005 /* From the BSpec:
1006 *
1007 * "For surfaces of type SURFTYPE_SCRATCH, valid range of pitch is:
1008 * [63,262143] -> [64B, 256KB]. Also, for SURFTYPE_SCRATCH, the
1009 * pitch must be a multiple of 64bytes."
1010 */
1011 assert(info->format == ISL_FORMAT_RAW);
1012 assert(info->stride_B % 64 == 0);
1013 assert(info->stride_B <= 256 * 1024);
1014 s.SurfaceType = SURFTYPE_SCRATCH;
1015 }
1016 #else
1017 assert(!info->is_scratch);
1018 #endif
1019
1020 s.SurfacePitch = info->stride_B - 1;
1021
1022 #if GFX_VER >= 6
1023 s.SurfaceVerticalAlignment = isl_encode_valign(4);
1024 #if GFX_VERx10 >= 125
1025 s.SurfaceHorizontalAlignment = isl_encode_halign(128);
1026 #elif GFX_VER >= 7
1027 s.SurfaceHorizontalAlignment = isl_encode_halign(4);
1028 s.SurfaceArray = false;
1029 #endif
1030 #endif
1031
1032 #if GFX_VER >= 9
1033 s.Height = ((num_elements - 1) >> 7) & 0x3fff;
1034 s.Width = (num_elements - 1) & 0x7f;
1035 s.Depth = ((num_elements - 1) >> 21) & 0x7ff;
1036 #elif GFX_VER >= 7
1037 s.Height = ((num_elements - 1) >> 7) & 0x3fff;
1038 s.Width = (num_elements - 1) & 0x7f;
1039 s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
1040 #else
1041 s.Height = ((num_elements - 1) >> 7) & 0x1fff;
1042 s.Width = (num_elements - 1) & 0x7f;
1043 s.Depth = ((num_elements - 1) >> 20) & 0x7f;
1044 #endif
1045
1046 #if GFX_VER >= 6
1047 s.NumberofMultisamples = MULTISAMPLECOUNT_1;
1048 #endif
1049
1050 #if (GFX_VER >= 8)
1051 s.TileMode = LINEAR;
1052 #else
1053 s.TiledSurface = false;
1054 #endif
1055
1056 #if (GFX_VER >= 8)
1057 s.RenderCacheReadWriteMode = WriteOnlyCache;
1058 #else
1059 s.RenderCacheReadWriteMode = 0;
1060 #endif
1061
1062 #if GFX_VERx10 >= 200
1063 s.EnableSamplerRoutetoLSC = isl_format_support_sampler_route_to_lsc(info->format);
1064 #endif /* if GFX_VERx10 >= 200 */
1065
1066 s.SurfaceBaseAddress = info->address;
1067 #if GFX_VER >= 6
1068 s.MOCS = info->mocs;
1069 #endif
1070
1071 #if GFX_VER >= 9
1072 /* Store the buffer size in the upper dword of the AUX surface base
1073 * address. Only enabled on Gfx9+ since Gfx8 has an Atom version with only
1074 * 32bits of address space.
1075 */
1076 if (dev->buffer_length_in_aux_addr) {
1077 assert(intel_needs_workaround(dev->info, 14019708328) == false);
1078 s.AuxiliarySurfaceBaseAddress = info->size_B << 32;
1079 } else {
1080 /* Wa_14019708328: all SURFTYPE_BUFFERs has
1081 * AuxiliarySurfaceMode == AUX_NONE so no need to check for it.
1082 * In case workaround is not needed and buffer_length_in_aux_addr is
1083 * false, it will set AuxiliarySurfaceBaseAddress to 0.
1084 */
1085 s.AuxiliarySurfaceBaseAddress = dev->dummy_aux_address;
1086 }
1087 #else
1088 assert(!dev->buffer_length_in_aux_addr);
1089 #endif
1090
1091 #if GFX_VERx10 >= 125
1092 /* Setting L1 caching policy to Write-back mode. */
1093 s.L1CacheControl = L1CC_WB;
1094 #endif
1095
1096 #if (GFX_VERx10 >= 75)
1097 struct isl_swizzle swz = isl_get_shader_channel_select(info->format,
1098 info->swizzle);
1099
1100 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) swz.r;
1101 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) swz.g;
1102 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) swz.b;
1103 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) swz.a;
1104 #endif
1105
1106 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
1107 }
1108
1109 void
isl_genX(null_fill_state_s)1110 isl_genX(null_fill_state_s)(const struct isl_device *dev, void *state,
1111 const struct isl_null_fill_state_info *restrict info)
1112 {
1113 struct GENX(RENDER_SURFACE_STATE) s = {
1114 .SurfaceType = SURFTYPE_NULL,
1115 /* We previously had this format set to B8G8R8A8_UNORM but ran into
1116 * hangs on IVB. R32_UINT seems to work for everybody.
1117 *
1118 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1872
1119 */
1120 .SurfaceFormat = ISL_FORMAT_R32_UINT,
1121 #if GFX_VER >= 7
1122 .SurfaceArray = info->size.depth > 1,
1123 #endif
1124 #if GFX_VERx10 >= 125
1125 .TileMode = TILE4,
1126 #elif GFX_VER >= 8
1127 .TileMode = YMAJOR,
1128 #else
1129 .TiledSurface = true,
1130 .TileWalk = TILEWALK_YMAJOR,
1131 #endif
1132 #if GFX_VER >= 6
1133 .MOCS = isl_mocs(dev, 0, false),
1134 #endif
1135 #if GFX_VER == 7
1136 /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
1137 * Functions"
1138 *
1139 * RENDER_SURFACE_STATE::Surface Vertical Alignment
1140 *
1141 * "This field must be set to VALIGN_4 for all tiled Y Render Target
1142 * surfaces."
1143 *
1144 * Affect IVB, HSW.
1145 */
1146 .SurfaceVerticalAlignment = VALIGN_4,
1147 #endif
1148 .MIPCountLOD = info->levels,
1149 .Width = info->size.width - 1,
1150 .Height = info->size.height - 1,
1151 .Depth = info->size.depth - 1,
1152 .RenderTargetViewExtent = info->size.depth - 1,
1153 #if GFX_VER <= 5
1154 .MinimumArrayElement = info->minimum_array_element,
1155 .ColorBufferComponentWriteDisables = 0xf,
1156 #endif
1157 };
1158 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
1159 }
1160