1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 */
6
7 #ifndef __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__
8 #define __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__
9
10 #include "isys_stream2mmio_public.h"
11 #include "device_access.h" /* ia_css_device_load_uint32 */
12 #include "assert_support.h" /* assert */
13 #include "print_support.h" /* print */
14
15 #define STREAM2MMIO_COMMAND_REG_ID 0
16 #define STREAM2MMIO_ACKNOWLEDGE_REG_ID 1
17 #define STREAM2MMIO_PIX_WIDTH_ID_REG_ID 2
18 #define STREAM2MMIO_START_ADDR_REG_ID 3 /* master port address,NOT Byte */
19 #define STREAM2MMIO_END_ADDR_REG_ID 4 /* master port address,NOT Byte */
20 #define STREAM2MMIO_STRIDE_REG_ID 5 /* stride in master port words, increment is per packet for long sids, stride is not used for short sid's*/
21 #define STREAM2MMIO_NUM_ITEMS_REG_ID 6 /* number of packets for store packets cmd, number of words for store_words cmd */
22 #define STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID 7 /* if this register is 1, input will be stalled if there is no pending command for this sid */
23 #define STREAM2MMIO_REGS_PER_SID 8
24
25 /*****************************************************
26 *
27 * Native command interface (NCI).
28 *
29 *****************************************************/
30 /**
31 * @brief Get the stream2mmio-controller state.
32 * Refer to "stream2mmio_public.h" for details.
33 */
stream2mmio_get_state(const stream2mmio_ID_t ID,stream2mmio_state_t * state)34 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_state(
35 const stream2mmio_ID_t ID,
36 stream2mmio_state_t *state)
37 {
38 stream2mmio_sid_ID_t i;
39
40 /*
41 * Get the values of the register-set per
42 * stream2mmio-controller sids.
43 */
44 for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) {
45 stream2mmio_get_sid_state(ID, i, &state->sid_state[i]);
46 }
47 }
48
49 /**
50 * @brief Get the state of the stream2mmio-controller sidess.
51 * Refer to "stream2mmio_public.h" for details.
52 */
stream2mmio_get_sid_state(const stream2mmio_ID_t ID,const stream2mmio_sid_ID_t sid_id,stream2mmio_sid_state_t * state)53 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_sid_state(
54 const stream2mmio_ID_t ID,
55 const stream2mmio_sid_ID_t sid_id,
56 stream2mmio_sid_state_t *state)
57 {
58 state->rcv_ack =
59 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID);
60
61 state->pix_width_id =
62 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_PIX_WIDTH_ID_REG_ID);
63
64 state->start_addr =
65 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_START_ADDR_REG_ID);
66
67 state->end_addr =
68 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_END_ADDR_REG_ID);
69
70 state->strides =
71 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_STRIDE_REG_ID);
72
73 state->num_items =
74 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_NUM_ITEMS_REG_ID);
75
76 state->block_when_no_cmd =
77 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID);
78 }
79
80 /**
81 * @brief Dump the state of the stream2mmio-controller sidess.
82 * Refer to "stream2mmio_public.h" for details.
83 */
stream2mmio_print_sid_state(stream2mmio_sid_state_t * state)84 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_print_sid_state(
85 stream2mmio_sid_state_t *state)
86 {
87 ia_css_print("\t \t Receive acks 0x%x\n", state->rcv_ack);
88 ia_css_print("\t \t Pixel width 0x%x\n", state->pix_width_id);
89 ia_css_print("\t \t Startaddr 0x%x\n", state->start_addr);
90 ia_css_print("\t \t Endaddr 0x%x\n", state->end_addr);
91 ia_css_print("\t \t Strides 0x%x\n", state->strides);
92 ia_css_print("\t \t Num Items 0x%x\n", state->num_items);
93 ia_css_print("\t \t block when no cmd 0x%x\n", state->block_when_no_cmd);
94 }
95
96 /**
97 * @brief Dump the ibuf-controller state.
98 * Refer to "stream2mmio_public.h" for details.
99 */
stream2mmio_dump_state(const stream2mmio_ID_t ID,stream2mmio_state_t * state)100 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_dump_state(
101 const stream2mmio_ID_t ID,
102 stream2mmio_state_t *state)
103 {
104 stream2mmio_sid_ID_t i;
105
106 /*
107 * Get the values of the register-set per
108 * stream2mmio-controller sids.
109 */
110 for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) {
111 ia_css_print("StREAM2MMIO ID %d SID %d\n", ID, i);
112 stream2mmio_print_sid_state(&state->sid_state[i]);
113 }
114 }
115
116 /* end of NCI */
117
118 /*****************************************************
119 *
120 * Device level interface (DLI).
121 *
122 *****************************************************/
123 /**
124 * @brief Load the register value.
125 * Refer to "stream2mmio_public.h" for details.
126 */
stream2mmio_reg_load(const stream2mmio_ID_t ID,const stream2mmio_sid_ID_t sid_id,const uint32_t reg_idx)127 STORAGE_CLASS_STREAM2MMIO_C hrt_data stream2mmio_reg_load(
128 const stream2mmio_ID_t ID,
129 const stream2mmio_sid_ID_t sid_id,
130 const uint32_t reg_idx)
131 {
132 u32 reg_bank_offset;
133
134 assert(ID < N_STREAM2MMIO_ID);
135
136 reg_bank_offset = STREAM2MMIO_REGS_PER_SID * sid_id;
137 return ia_css_device_load_uint32(STREAM2MMIO_CTRL_BASE[ID] +
138 (reg_bank_offset + reg_idx) * sizeof(hrt_data));
139 }
140
141 /**
142 * @brief Store a value to the register.
143 * Refer to "stream2mmio_public.h" for details.
144 */
stream2mmio_reg_store(const stream2mmio_ID_t ID,const hrt_address reg,const hrt_data value)145 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_reg_store(
146 const stream2mmio_ID_t ID,
147 const hrt_address reg,
148 const hrt_data value)
149 {
150 assert(ID < N_STREAM2MMIO_ID);
151 assert(STREAM2MMIO_CTRL_BASE[ID] != (hrt_address)-1);
152
153 ia_css_device_store_uint32(STREAM2MMIO_CTRL_BASE[ID] +
154 reg * sizeof(hrt_data), value);
155 }
156
157 /* end of DLI */
158
159 #endif /* __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ */
160