1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2018, 2020-2024 Intel Corporation 4 */ 5 #ifndef __iwl_context_info_file_gen3_h__ 6 #define __iwl_context_info_file_gen3_h__ 7 8 #include "iwl-context-info.h" 9 10 #define CSR_CTXT_INFO_BOOT_CTRL 0x0 11 #define CSR_CTXT_INFO_ADDR 0x118 12 #define CSR_IML_DATA_ADDR 0x120 13 #define CSR_IML_SIZE_ADDR 0x128 14 #define CSR_IML_RESP_ADDR 0x12c 15 16 #define UNFRAGMENTED_PNVM_PAYLOADS_NUMBER 2 17 18 /* Set bit for enabling automatic function boot */ 19 #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 20 /* Set bit for initiating function boot */ 21 #define CSR_AUTO_FUNC_INIT BIT(7) 22 23 /** 24 * enum iwl_prph_scratch_mtr_format - tfd size configuration 25 * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 26 * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 27 * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 28 * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 29 */ 30 enum iwl_prph_scratch_mtr_format { 31 IWL_PRPH_MTR_FORMAT_16B = 0x0, 32 IWL_PRPH_MTR_FORMAT_32B = 0x40000, 33 IWL_PRPH_MTR_FORMAT_64B = 0x80000, 34 IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 35 }; 36 37 /** 38 * enum iwl_prph_scratch_flags - PRPH scratch control flags 39 * @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug 40 * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 41 * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 42 * in hwm config. 43 * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 44 * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 45 * multicomm. 46 * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 47 * @IWL_PRPH_SCRATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 48 * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 49 * completion descriptor, 1 for responses (legacy) 50 * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 51 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 52 * 3: 256 bit. 53 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 54 * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K 55 * appropriately; use the below values for this. 56 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 57 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 58 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 59 * @IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE: Indicate fw to set SCU_FORCE_ACTIVE 60 * upon reset. 61 */ 62 enum iwl_prph_scratch_flags { 63 IWL_PRPH_SCRATCH_IMR_DEBUG_EN = BIT(1), 64 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 65 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 66 IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 67 IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 68 IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 69 IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 70 IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 71 IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 72 IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, 73 IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, 74 IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, 75 IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20, 76 IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE = BIT(29), 77 }; 78 79 /** 80 * enum iwl_prph_scratch_ext_flags - PRPH scratch control ext flags 81 * @IWL_PRPH_SCRATCH_EXT_URM_FW: switch to URM mode based on fw setting 82 * @IWL_PRPH_SCRATCH_EXT_URM_PERM: switch to permanent URM mode 83 */ 84 enum iwl_prph_scratch_ext_flags { 85 IWL_PRPH_SCRATCH_EXT_URM_FW = BIT(4), 86 IWL_PRPH_SCRATCH_EXT_URM_PERM = BIT(5), 87 }; 88 89 /** 90 * struct iwl_prph_scratch_version - version structure 91 * @mac_id: SKU and revision id 92 * @version: prph scratch information version id 93 * @size: the size of the context information in DWs 94 * @reserved: reserved 95 */ 96 struct iwl_prph_scratch_version { 97 __le16 mac_id; 98 __le16 version; 99 __le16 size; 100 __le16 reserved; 101 } __packed; /* PERIPH_SCRATCH_VERSION_S */ 102 103 /** 104 * struct iwl_prph_scratch_control - control structure 105 * @control_flags: context information flags see &enum iwl_prph_scratch_flags 106 * @control_flags_ext: context information for extended flags, 107 * see &enum iwl_prph_scratch_ext_flags 108 */ 109 struct iwl_prph_scratch_control { 110 __le32 control_flags; 111 __le32 control_flags_ext; 112 } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 113 114 /** 115 * struct iwl_prph_scratch_pnvm_cfg - PNVM scratch 116 * @pnvm_base_addr: PNVM start address 117 * @pnvm_size: the size of the PNVM image in bytes 118 * @reserved: reserved 119 */ 120 struct iwl_prph_scratch_pnvm_cfg { 121 __le64 pnvm_base_addr; 122 __le32 pnvm_size; 123 __le32 reserved; 124 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 125 126 /** 127 * struct iwl_prph_scrath_mem_desc_addr_array 128 * @mem_descs: array of dram addresses. 129 * Each address is the beggining of a pnvm payload. 130 */ 131 struct iwl_prph_scrath_mem_desc_addr_array { 132 __le64 mem_descs[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 133 } __packed; /* PERIPH_SCRATCH_MEM_DESC_ADDR_ARRAY_S_VER_1 */ 134 135 /** 136 * struct iwl_prph_scratch_hwm_cfg - hwm config 137 * @hwm_base_addr: hwm start address 138 * @hwm_size: hwm size in DWs 139 * @debug_token_config: debug preset 140 */ 141 struct iwl_prph_scratch_hwm_cfg { 142 __le64 hwm_base_addr; 143 __le32 hwm_size; 144 __le32 debug_token_config; 145 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 146 147 /** 148 * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 149 * @free_rbd_addr: default queue free RB CB base address 150 * @reserved: reserved 151 */ 152 struct iwl_prph_scratch_rbd_cfg { 153 __le64 free_rbd_addr; 154 __le32 reserved; 155 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 156 157 /** 158 * struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table 159 * @base_addr: reduce power table address 160 * @size: the size of the entire power table image 161 * @reserved: (reserved) 162 */ 163 struct iwl_prph_scratch_uefi_cfg { 164 __le64 base_addr; 165 __le32 size; 166 __le32 reserved; 167 } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */ 168 169 /** 170 * struct iwl_prph_scratch_step_cfg - prph scratch step configuration 171 * @mbx_addr_0: [0:7] revision, 172 * [8:15] cnvi_to_cnvr length, 173 * [16:23] cnvr_to_cnvi channel length, 174 * [24:31] radio1 reserved 175 * @mbx_addr_1: [0:7] radio2 reserved 176 */ 177 178 struct iwl_prph_scratch_step_cfg { 179 __le32 mbx_addr_0; 180 __le32 mbx_addr_1; 181 } __packed; 182 183 /** 184 * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 185 * @version: version information of context info and HW 186 * @control: control flags of FH configurations 187 * @pnvm_cfg: ror configuration 188 * @hwm_cfg: hwm configuration 189 * @rbd_cfg: default RX queue configuration 190 * @reduce_power_cfg: UEFI power reduction table 191 * @step_cfg: step configuration 192 */ 193 struct iwl_prph_scratch_ctrl_cfg { 194 struct iwl_prph_scratch_version version; 195 struct iwl_prph_scratch_control control; 196 struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; 197 struct iwl_prph_scratch_hwm_cfg hwm_cfg; 198 struct iwl_prph_scratch_rbd_cfg rbd_cfg; 199 struct iwl_prph_scratch_uefi_cfg reduce_power_cfg; 200 struct iwl_prph_scratch_step_cfg step_cfg; 201 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 202 203 /** 204 * struct iwl_prph_scratch - peripheral scratch mapping 205 * @ctrl_cfg: control and configuration of prph scratch 206 * @dram: firmware images addresses in DRAM 207 * @fseq_override: FSEQ override parameters 208 * @step_analog_params: STEP analog calibration values 209 * @reserved: reserved 210 */ 211 struct iwl_prph_scratch { 212 struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 213 __le32 fseq_override; 214 __le32 step_analog_params; 215 __le32 reserved[8]; 216 struct iwl_context_info_dram dram; 217 } __packed; /* PERIPH_SCRATCH_S */ 218 219 /** 220 * struct iwl_prph_info - peripheral information 221 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 222 * @ipc_status_mirror: reflects the value in the IPC Status CSR register 223 * @sleep_notif: indicates the peripheral sleep status 224 * @reserved: reserved 225 */ 226 struct iwl_prph_info { 227 __le32 boot_stage_mirror; 228 __le32 ipc_status_mirror; 229 __le32 sleep_notif; 230 __le32 reserved; 231 } __packed; /* PERIPH_INFO_S */ 232 233 /** 234 * struct iwl_context_info_gen3 - device INIT configuration 235 * @version: version of the context information 236 * @size: size of context information in DWs 237 * @config: context in which the peripheral would execute - a subset of 238 * capability csr register published by the peripheral 239 * @prph_info_base_addr: the peripheral information structure start address 240 * @cr_head_idx_arr_base_addr: the completion ring head index array 241 * start address 242 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 243 * start address 244 * @cr_tail_idx_arr_base_addr: the completion ring tail index array 245 * start address 246 * @tr_head_idx_arr_base_addr: the transfer ring head index array 247 * start address 248 * @cr_idx_arr_size: number of entries in the completion ring index array 249 * @tr_idx_arr_size: number of entries in the transfer ring index array 250 * @mtr_base_addr: the message transfer ring start address 251 * @mcr_base_addr: the message completion ring start address 252 * @mtr_size: number of entries which the message transfer ring can hold 253 * @mcr_size: number of entries which the message completion ring can hold 254 * @mtr_doorbell_vec: the doorbell vector associated with the message 255 * transfer ring 256 * @mcr_doorbell_vec: the doorbell vector associated with the message 257 * completion ring 258 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 259 * completing a transfer descriptor in the message transfer ring 260 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 261 * completing a completion descriptor in the message completion ring 262 * @mtr_opt_header_size: the size of the optional header in the transfer 263 * descriptor associated with the message transfer ring in DWs 264 * @mtr_opt_footer_size: the size of the optional footer in the transfer 265 * descriptor associated with the message transfer ring in DWs 266 * @mcr_opt_header_size: the size of the optional header in the completion 267 * descriptor associated with the message completion ring in DWs 268 * @mcr_opt_footer_size: the size of the optional footer in the completion 269 * descriptor associated with the message completion ring in DWs 270 * @msg_rings_ctrl_flags: message rings control flags 271 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 272 * after updating the Peripheral Information structure 273 * @prph_scratch_base_addr: the peripheral scratch structure start address 274 * @prph_scratch_size: the size of the peripheral scratch structure in DWs 275 * @reserved: reserved 276 */ 277 struct iwl_context_info_gen3 { 278 __le16 version; 279 __le16 size; 280 __le32 config; 281 __le64 prph_info_base_addr; 282 __le64 cr_head_idx_arr_base_addr; 283 __le64 tr_tail_idx_arr_base_addr; 284 __le64 cr_tail_idx_arr_base_addr; 285 __le64 tr_head_idx_arr_base_addr; 286 __le16 cr_idx_arr_size; 287 __le16 tr_idx_arr_size; 288 __le64 mtr_base_addr; 289 __le64 mcr_base_addr; 290 __le16 mtr_size; 291 __le16 mcr_size; 292 __le16 mtr_doorbell_vec; 293 __le16 mcr_doorbell_vec; 294 __le16 mtr_msi_vec; 295 __le16 mcr_msi_vec; 296 u8 mtr_opt_header_size; 297 u8 mtr_opt_footer_size; 298 u8 mcr_opt_header_size; 299 u8 mcr_opt_footer_size; 300 __le16 msg_rings_ctrl_flags; 301 __le16 prph_info_msi_vec; 302 __le64 prph_scratch_base_addr; 303 __le32 prph_scratch_size; 304 __le32 reserved; 305 } __packed; /* IPC_CONTEXT_INFO_S */ 306 307 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 308 const struct fw_img *fw); 309 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive); 310 311 int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans, 312 const struct iwl_pnvm_image *pnvm_payloads, 313 const struct iwl_ucode_capabilities *capa); 314 void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 315 const struct iwl_ucode_capabilities *capa); 316 int 317 iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans, 318 const struct iwl_pnvm_image *payloads, 319 const struct iwl_ucode_capabilities *capa); 320 void 321 iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 322 const struct iwl_ucode_capabilities *capa); 323 int iwl_trans_pcie_ctx_info_gen3_set_step(struct iwl_trans *trans, 324 u32 mbx_addr_0_step, u32 mbx_addr_1_step); 325 #endif /* __iwl_context_info_file_gen3_h__ */ 326