1 /* 2 * Copyright (C) 2023 The Android Open Source Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files 6 * (the "Software"), to deal in the Software without restriction, 7 * including without limitation the rights to use, copy, modify, merge, 8 * publish, distribute, sublicense, and/or sell copies of the Software, 9 * and to permit persons to whom the Software is furnished to do so, 10 * subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef PMU_ARCH_H 25 #define PMU_ARCH_H 26 27 #define U(_x) (_x##U) 28 29 /******************************************************************************* 30 * Definitions of register offsets and fields in the CNTBaseN Frame of the 31 * system level implementation of the Generic Timer. 32 ******************************************************************************/ 33 /* Physical Count register. */ 34 #define CNTPCT_LO U(0x0) 35 /* Counter Frequency register. */ 36 #define CNTBASEN_CNTFRQ U(0x10) 37 /* Physical Timer CompareValue register. */ 38 #define CNTP_CVAL_LO U(0x20) 39 /* Physical Timer Control register. */ 40 #define CNTP_CTL U(0x2c) 41 42 /* PMCR_EL0 definitions */ 43 #define PMCR_EL0_RESET_VAL U(0x0) 44 #define PMCR_EL0_N_SHIFT U(11) 45 #define PMCR_EL0_N_MASK U(0x1f) 46 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 47 #define PMCR_EL0_LC_BIT (U(1) << 6) 48 #define PMCR_EL0_DP_BIT (U(1) << 5) 49 #define PMCR_EL0_X_BIT (U(1) << 4) 50 #define PMCR_EL0_D_BIT (U(1) << 3) 51 #define PMCR_EL0_C_BIT (U(1) << 2) 52 #define PMCR_EL0_P_BIT (U(1) << 1) 53 #define PMCR_EL0_E_BIT (U(1) << 0) 54 55 /* PMCNTENSET_EL0 definitions */ 56 #define PMCNTENSET_EL0_C_BIT (U(1) << 31) 57 #define PMCNTENSET_EL0_P_BIT(x) (U(1) << x) 58 59 /* PMEVTYPER<n>_EL0 definitions */ 60 #define PMEVTYPER_EL0_P_BIT (U(1) << 31) 61 #define PMEVTYPER_EL0_NSK_BIT (U(1) << 29) 62 #define PMEVTYPER_EL0_NSH_BIT (U(1) << 27) 63 #define PMEVTYPER_EL0_M_BIT (U(1) << 26) 64 #define PMEVTYPER_EL0_MT_BIT (U(1) << 25) 65 #define PMEVTYPER_EL0_SH_BIT (U(1) << 24) 66 #define PMEVTYPER_EL0_EVTCOUNT_BITS U(0x000003FF) 67 68 /* PMCCFILTR_EL0 definitions */ 69 #define PMCCFILTR_EL0_P_BIT (U(1) << 31) 70 #define PMCCFILTR_EL0_U_BIT (U(1) << 30) 71 #define PMCCFILTR_EL0_NSK_BIT (U(1) << 29) 72 #define PMCCFILTR_EL0_NSH_BIT (U(1) << 27) 73 #define PMCCFILTR_EL0_M_BIT (U(1) << 26) 74 #define PMCCFILTR_EL0_MT_BIT (U(1) << 25) 75 #define PMCCFILTR_EL0_SH_BIT (U(1) << 24) 76 #define PMCCFILTR_EL0_T_BIT (U(1) << 23) 77 #define PMCCFILTR_EL0_RLK_BIT (U(1) << 22) 78 #define PMCCFILTR_EL0_RLU_BIT (U(1) << 21) 79 #define PMCCFILTR_EL0_RLH_BIT (U(1) << 20) 80 81 /* PMU event counter ID definitions */ 82 #define PMU_EV_SW_INCR U(0x00) 83 #define PMU_EV_L1I_CACHE_REFILL U(0x01) 84 #define PMU_EV_L1I_TLB_REFILL U(0x02) 85 #define PMU_EV_L1D_CACHE_REFILL U(0x03) 86 #define PMU_EV_L1D_CACHE U(0x04) 87 #define PMU_EV_L1D_TLB_REFILL U(0x05) 88 #define PMU_EV_LD_RETIRED U(0x06) 89 #define PMU_EV_ST_RETIRED U(0x07) 90 #define PMU_EV_INST_RETIRED U(0x08) 91 #define PMU_EV_EXC_TAKEN U(0x09) 92 #define PMU_EV_EXC_RETURN U(0x0A) 93 #define PMU_EV_CID_WRITE_RETIRED U(0x0B) 94 #define PMU_EV_PC_WRITE_RETIRED U(0x0C) 95 #define PMU_EV_BR_IMMED_RETIRED U(0x0D) 96 #define PMU_EV_BR_RETURN_RETIRED U(0x0E) 97 #define PMU_EV_UNALIGNED_LDST_RETIRED U(0x0F) 98 #define PMU_EV_BR_MIS_PRED U(0x10) 99 #define PMU_EV_CPU_CYCLES U(0x11) 100 #define PMU_EV_BR_PRED U(0x12) 101 #define PMU_EV_MEM_ACCESS U(0x13) 102 #define PMU_EV_L1I_CACHE U(0x14) 103 #define PMU_EV_L1D_CACHE_WB U(0x15) 104 #define PMU_EV_L2D_CACHE U(0x16) 105 #define PMU_EV_L2D_CACHE_REFILL U(0x17) 106 #define PMU_EV_L2D_CACHE_WB U(0x18) 107 #define PMU_EV_BUS_ACCESS U(0x19) 108 #define PMU_EV_MEMORY_ERROR U(0x1A) 109 #define PMU_EV_BUS_CYCLES U(0x1D) 110 #define PMU_EV_CHAIN U(0x1E) 111 #define PMU_EV_BUS_ACCESS_LD U(0x60) 112 #define PMU_EV_BUS_ACCESS_ST U(0x61) 113 #define PMU_EV_BR_INDIRECT_SPEC U(0x7A) 114 #define PMU_EV_EXC_IRQ U(0x86) 115 #define PMU_EV_EXC_FIQ U(0x87) 116 117 #endif /* PMU_ARCH_H */ 118