1 #ifndef __BDK_CSRS_L2C_TAD_H__
2 #define __BDK_CSRS_L2C_TAD_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
36 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
37 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
38 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
39 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium L2C_TAD.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration l2c_tad_bar_e
57 *
58 * L2C TAD Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_L2C_TAD_BAR_E_L2C_TADX_PF_BAR0(a) (0x87e050000000ll + 0x1000000ll * (a))
62 #define BDK_L2C_TAD_BAR_E_L2C_TADX_PF_BAR0_SIZE 0x800000ull
63 #define BDK_L2C_TAD_BAR_E_L2C_TADX_PF_BAR4(a) (0x87e050f00000ll + 0x1000000ll * (a))
64 #define BDK_L2C_TAD_BAR_E_L2C_TADX_PF_BAR4_SIZE 0x100000ull
65
66 /**
67 * Enumeration l2c_tad_int_vec_e
68 *
69 * L2C TAD MSI-X Vector Enumeration
70 * Enumerates the MSI-X interrupt vectors.
71 */
72 #define BDK_L2C_TAD_INT_VEC_E_INTS (0)
73
74 /**
75 * Register (RSL) l2c_tad#_int_ena_w1c
76 *
77 * L2C TAD Interrupt Enable Clear Registers
78 * This register clears interrupt enable bits.
79 */
80 union bdk_l2c_tadx_int_ena_w1c
81 {
82 uint64_t u;
83 struct bdk_l2c_tadx_int_ena_w1c_s
84 {
85 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
86 uint64_t reserved_36_63 : 28;
87 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
88 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
89 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
90 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
91 uint64_t reserved_19_31 : 13;
92 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
93 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
94 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
95 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
96 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
97 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
98 uint64_t reserved_11_12 : 2;
99 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
100 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
101 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
102 uint64_t reserved_6_7 : 2;
103 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
104 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
105 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
106 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
107 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
108 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
109 #else /* Word 0 - Little Endian */
110 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
111 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
112 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
113 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
114 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
115 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
116 uint64_t reserved_6_7 : 2;
117 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
118 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
119 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
120 uint64_t reserved_11_12 : 2;
121 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
122 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
123 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
124 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
125 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
126 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
127 uint64_t reserved_19_31 : 13;
128 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
129 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
130 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
131 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
132 uint64_t reserved_36_63 : 28;
133 #endif /* Word 0 - End */
134 } s;
135 struct bdk_l2c_tadx_int_ena_w1c_cn88xxp1
136 {
137 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
138 uint64_t reserved_36_63 : 28;
139 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
140 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
141 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
142 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
143 uint64_t reserved_19_31 : 13;
144 uint64_t reserved_18 : 1;
145 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
146 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
147 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
148 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
149 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
150 uint64_t reserved_11_12 : 2;
151 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
152 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
153 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
154 uint64_t reserved_6_7 : 2;
155 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
156 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
157 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
158 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
159 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
160 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
161 #else /* Word 0 - Little Endian */
162 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
163 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
164 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
165 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
166 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
167 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
168 uint64_t reserved_6_7 : 2;
169 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
170 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
171 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
172 uint64_t reserved_11_12 : 2;
173 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
174 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
175 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
176 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
177 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
178 uint64_t reserved_18 : 1;
179 uint64_t reserved_19_31 : 13;
180 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
181 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
182 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
183 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
184 uint64_t reserved_36_63 : 28;
185 #endif /* Word 0 - End */
186 } cn88xxp1;
187 struct bdk_l2c_tadx_int_ena_w1c_cn81xx
188 {
189 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
190 uint64_t reserved_36_63 : 28;
191 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[WRDISOCI]. */
192 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[RDDISOCI]. */
193 uint64_t reserved_19_33 : 15;
194 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[GSYNCTO]. */
195 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[LFBTO]. */
196 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[WRDISLMC]. */
197 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[RDDISLMC]. */
198 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[RDNXM]. */
199 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[WRNXM]. */
200 uint64_t reserved_11_12 : 2;
201 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[NOWAY]. */
202 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[TAGDBE]. */
203 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[TAGSBE]. */
204 uint64_t reserved_6_7 : 2;
205 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[FBFDBE]. */
206 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[FBFSBE]. */
207 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[SBFDBE]. */
208 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[SBFSBE]. */
209 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[L2DDBE]. */
210 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[L2DSBE]. */
211 #else /* Word 0 - Little Endian */
212 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[L2DSBE]. */
213 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[L2DDBE]. */
214 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[SBFSBE]. */
215 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[SBFDBE]. */
216 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[FBFSBE]. */
217 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[FBFDBE]. */
218 uint64_t reserved_6_7 : 2;
219 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[TAGSBE]. */
220 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[TAGDBE]. */
221 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[NOWAY]. */
222 uint64_t reserved_11_12 : 2;
223 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[WRNXM]. */
224 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[RDNXM]. */
225 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[RDDISLMC]. */
226 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[WRDISLMC]. */
227 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[LFBTO]. */
228 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[GSYNCTO]. */
229 uint64_t reserved_19_33 : 15;
230 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[RDDISOCI]. */
231 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Reads or clears enable for L2C_TAD(0)_INT_W1C[WRDISOCI]. */
232 uint64_t reserved_36_63 : 28;
233 #endif /* Word 0 - End */
234 } cn81xx;
235 struct bdk_l2c_tadx_int_ena_w1c_cn83xx
236 {
237 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
238 uint64_t reserved_36_63 : 28;
239 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[WRDISOCI]. */
240 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[RDDISOCI]. */
241 uint64_t reserved_19_33 : 15;
242 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
243 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[LFBTO]. */
244 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[WRDISLMC]. */
245 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[RDDISLMC]. */
246 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[RDNXM]. */
247 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[WRNXM]. */
248 uint64_t reserved_11_12 : 2;
249 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[NOWAY]. */
250 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[TAGDBE]. */
251 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[TAGSBE]. */
252 uint64_t reserved_6_7 : 2;
253 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[FBFDBE]. */
254 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[FBFSBE]. */
255 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[SBFDBE]. */
256 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[SBFSBE]. */
257 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[L2DDBE]. */
258 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[L2DSBE]. */
259 #else /* Word 0 - Little Endian */
260 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[L2DSBE]. */
261 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[L2DDBE]. */
262 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[SBFSBE]. */
263 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[SBFDBE]. */
264 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[FBFSBE]. */
265 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[FBFDBE]. */
266 uint64_t reserved_6_7 : 2;
267 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[TAGSBE]. */
268 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[TAGDBE]. */
269 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[NOWAY]. */
270 uint64_t reserved_11_12 : 2;
271 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[WRNXM]. */
272 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[RDNXM]. */
273 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[RDDISLMC]. */
274 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[WRDISLMC]. */
275 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[LFBTO]. */
276 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
277 uint64_t reserved_19_33 : 15;
278 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[RDDISOCI]. */
279 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Reads or clears enable for L2C_TAD(0..3)_INT_W1C[WRDISOCI]. */
280 uint64_t reserved_36_63 : 28;
281 #endif /* Word 0 - End */
282 } cn83xx;
283 struct bdk_l2c_tadx_int_ena_w1c_cn88xxp2
284 {
285 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
286 uint64_t reserved_36_63 : 28;
287 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
288 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
289 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
290 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
291 uint64_t reserved_19_31 : 13;
292 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[GSYNCTO]. */
293 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
294 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
295 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
296 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
297 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
298 uint64_t reserved_11_12 : 2;
299 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
300 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
301 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
302 uint64_t reserved_6_7 : 2;
303 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
304 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
305 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
306 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
307 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
308 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
309 #else /* Word 0 - Little Endian */
310 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
311 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
312 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
313 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
314 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
315 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
316 uint64_t reserved_6_7 : 2;
317 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
318 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
319 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
320 uint64_t reserved_11_12 : 2;
321 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
322 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
323 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
324 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
325 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
326 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[GSYNCTO]. */
327 uint64_t reserved_19_31 : 13;
328 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
329 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
330 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
331 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Reads or clears enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
332 uint64_t reserved_36_63 : 28;
333 #endif /* Word 0 - End */
334 } cn88xxp2;
335 };
336 typedef union bdk_l2c_tadx_int_ena_w1c bdk_l2c_tadx_int_ena_w1c_t;
337
338 static inline uint64_t BDK_L2C_TADX_INT_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_INT_ENA_W1C(unsigned long a)339 static inline uint64_t BDK_L2C_TADX_INT_ENA_W1C(unsigned long a)
340 {
341 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
342 return 0x87e050040020ll + 0x1000000ll * ((a) & 0x0);
343 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
344 return 0x87e050040020ll + 0x1000000ll * ((a) & 0x3);
345 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=7))
346 return 0x87e050040020ll + 0x1000000ll * ((a) & 0x7);
347 __bdk_csr_fatal("L2C_TADX_INT_ENA_W1C", 1, a, 0, 0, 0);
348 }
349
350 #define typedef_BDK_L2C_TADX_INT_ENA_W1C(a) bdk_l2c_tadx_int_ena_w1c_t
351 #define bustype_BDK_L2C_TADX_INT_ENA_W1C(a) BDK_CSR_TYPE_RSL
352 #define basename_BDK_L2C_TADX_INT_ENA_W1C(a) "L2C_TADX_INT_ENA_W1C"
353 #define device_bar_BDK_L2C_TADX_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
354 #define busnum_BDK_L2C_TADX_INT_ENA_W1C(a) (a)
355 #define arguments_BDK_L2C_TADX_INT_ENA_W1C(a) (a),-1,-1,-1
356
357 /**
358 * Register (RSL) l2c_tad#_int_ena_w1s
359 *
360 * L2C TAD Interrupt Enable Set Registers
361 * This register sets interrupt enable bits.
362 */
363 union bdk_l2c_tadx_int_ena_w1s
364 {
365 uint64_t u;
366 struct bdk_l2c_tadx_int_ena_w1s_s
367 {
368 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
369 uint64_t reserved_36_63 : 28;
370 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
371 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
372 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
373 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
374 uint64_t reserved_19_31 : 13;
375 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
376 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
377 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
378 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
379 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
380 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
381 uint64_t reserved_11_12 : 2;
382 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
383 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
384 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
385 uint64_t reserved_6_7 : 2;
386 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
387 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
388 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
389 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
390 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
391 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
392 #else /* Word 0 - Little Endian */
393 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
394 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
395 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
396 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
397 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
398 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
399 uint64_t reserved_6_7 : 2;
400 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
401 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
402 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
403 uint64_t reserved_11_12 : 2;
404 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
405 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
406 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
407 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
408 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
409 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
410 uint64_t reserved_19_31 : 13;
411 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
412 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
413 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
414 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
415 uint64_t reserved_36_63 : 28;
416 #endif /* Word 0 - End */
417 } s;
418 struct bdk_l2c_tadx_int_ena_w1s_cn88xxp1
419 {
420 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
421 uint64_t reserved_36_63 : 28;
422 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
423 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
424 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
425 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
426 uint64_t reserved_19_31 : 13;
427 uint64_t reserved_18 : 1;
428 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
429 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
430 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
431 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
432 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
433 uint64_t reserved_11_12 : 2;
434 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
435 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
436 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
437 uint64_t reserved_6_7 : 2;
438 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
439 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
440 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
441 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
442 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
443 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
444 #else /* Word 0 - Little Endian */
445 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
446 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
447 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
448 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
449 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
450 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
451 uint64_t reserved_6_7 : 2;
452 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
453 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
454 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
455 uint64_t reserved_11_12 : 2;
456 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
457 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
458 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
459 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
460 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
461 uint64_t reserved_18 : 1;
462 uint64_t reserved_19_31 : 13;
463 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
464 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
465 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
466 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
467 uint64_t reserved_36_63 : 28;
468 #endif /* Word 0 - End */
469 } cn88xxp1;
470 struct bdk_l2c_tadx_int_ena_w1s_cn81xx
471 {
472 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
473 uint64_t reserved_36_63 : 28;
474 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[WRDISOCI]. */
475 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[RDDISOCI]. */
476 uint64_t reserved_19_33 : 15;
477 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[GSYNCTO]. */
478 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[LFBTO]. */
479 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[WRDISLMC]. */
480 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[RDDISLMC]. */
481 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[RDNXM]. */
482 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[WRNXM]. */
483 uint64_t reserved_11_12 : 2;
484 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[NOWAY]. */
485 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[TAGDBE]. */
486 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[TAGSBE]. */
487 uint64_t reserved_6_7 : 2;
488 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[FBFDBE]. */
489 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[FBFSBE]. */
490 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[SBFDBE]. */
491 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[SBFSBE]. */
492 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[L2DDBE]. */
493 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[L2DSBE]. */
494 #else /* Word 0 - Little Endian */
495 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[L2DSBE]. */
496 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[L2DDBE]. */
497 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[SBFSBE]. */
498 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[SBFDBE]. */
499 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[FBFSBE]. */
500 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[FBFDBE]. */
501 uint64_t reserved_6_7 : 2;
502 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[TAGSBE]. */
503 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[TAGDBE]. */
504 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[NOWAY]. */
505 uint64_t reserved_11_12 : 2;
506 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[WRNXM]. */
507 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[RDNXM]. */
508 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[RDDISLMC]. */
509 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[WRDISLMC]. */
510 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[LFBTO]. */
511 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[GSYNCTO]. */
512 uint64_t reserved_19_33 : 15;
513 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[RDDISOCI]. */
514 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets enable for L2C_TAD(0)_INT_W1C[WRDISOCI]. */
515 uint64_t reserved_36_63 : 28;
516 #endif /* Word 0 - End */
517 } cn81xx;
518 struct bdk_l2c_tadx_int_ena_w1s_cn83xx
519 {
520 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
521 uint64_t reserved_36_63 : 28;
522 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[WRDISOCI]. */
523 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[RDDISOCI]. */
524 uint64_t reserved_19_33 : 15;
525 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
526 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[LFBTO]. */
527 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[WRDISLMC]. */
528 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[RDDISLMC]. */
529 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[RDNXM]. */
530 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[WRNXM]. */
531 uint64_t reserved_11_12 : 2;
532 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[NOWAY]. */
533 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[TAGDBE]. */
534 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[TAGSBE]. */
535 uint64_t reserved_6_7 : 2;
536 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[FBFDBE]. */
537 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[FBFSBE]. */
538 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[SBFDBE]. */
539 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[SBFSBE]. */
540 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[L2DDBE]. */
541 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[L2DSBE]. */
542 #else /* Word 0 - Little Endian */
543 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[L2DSBE]. */
544 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[L2DDBE]. */
545 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[SBFSBE]. */
546 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[SBFDBE]. */
547 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[FBFSBE]. */
548 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[FBFDBE]. */
549 uint64_t reserved_6_7 : 2;
550 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[TAGSBE]. */
551 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[TAGDBE]. */
552 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[NOWAY]. */
553 uint64_t reserved_11_12 : 2;
554 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[WRNXM]. */
555 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[RDNXM]. */
556 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[RDDISLMC]. */
557 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[WRDISLMC]. */
558 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[LFBTO]. */
559 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
560 uint64_t reserved_19_33 : 15;
561 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[RDDISOCI]. */
562 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets enable for L2C_TAD(0..3)_INT_W1C[WRDISOCI]. */
563 uint64_t reserved_36_63 : 28;
564 #endif /* Word 0 - End */
565 } cn83xx;
566 struct bdk_l2c_tadx_int_ena_w1s_cn88xxp2
567 {
568 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
569 uint64_t reserved_36_63 : 28;
570 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
571 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
572 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
573 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
574 uint64_t reserved_19_31 : 13;
575 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[GSYNCTO]. */
576 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
577 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
578 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
579 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
580 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
581 uint64_t reserved_11_12 : 2;
582 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
583 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
584 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
585 uint64_t reserved_6_7 : 2;
586 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
587 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
588 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
589 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
590 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
591 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
592 #else /* Word 0 - Little Endian */
593 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
594 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
595 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
596 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
597 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
598 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
599 uint64_t reserved_6_7 : 2;
600 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
601 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
602 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[NOWAY]. */
603 uint64_t reserved_11_12 : 2;
604 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRNXM]. */
605 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDNXM]. */
606 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
607 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
608 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[LFBTO]. */
609 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[GSYNCTO]. */
610 uint64_t reserved_19_31 : 13;
611 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
612 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
613 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
614 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets enable for L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
615 uint64_t reserved_36_63 : 28;
616 #endif /* Word 0 - End */
617 } cn88xxp2;
618 };
619 typedef union bdk_l2c_tadx_int_ena_w1s bdk_l2c_tadx_int_ena_w1s_t;
620
621 static inline uint64_t BDK_L2C_TADX_INT_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_INT_ENA_W1S(unsigned long a)622 static inline uint64_t BDK_L2C_TADX_INT_ENA_W1S(unsigned long a)
623 {
624 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
625 return 0x87e050040028ll + 0x1000000ll * ((a) & 0x0);
626 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
627 return 0x87e050040028ll + 0x1000000ll * ((a) & 0x3);
628 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=7))
629 return 0x87e050040028ll + 0x1000000ll * ((a) & 0x7);
630 __bdk_csr_fatal("L2C_TADX_INT_ENA_W1S", 1, a, 0, 0, 0);
631 }
632
633 #define typedef_BDK_L2C_TADX_INT_ENA_W1S(a) bdk_l2c_tadx_int_ena_w1s_t
634 #define bustype_BDK_L2C_TADX_INT_ENA_W1S(a) BDK_CSR_TYPE_RSL
635 #define basename_BDK_L2C_TADX_INT_ENA_W1S(a) "L2C_TADX_INT_ENA_W1S"
636 #define device_bar_BDK_L2C_TADX_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
637 #define busnum_BDK_L2C_TADX_INT_ENA_W1S(a) (a)
638 #define arguments_BDK_L2C_TADX_INT_ENA_W1S(a) (a),-1,-1,-1
639
640 /**
641 * Register (RSL) l2c_tad#_int_w1c
642 *
643 * L2C TAD Interrupt Registers
644 * This register is for TAD-based interrupts.
645 */
646 union bdk_l2c_tadx_int_w1c
647 {
648 uint64_t u;
649 struct bdk_l2c_tadx_int_w1c_s
650 {
651 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
652 uint64_t reserved_36_63 : 28;
653 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Illegal write operation to a remote node with L2C_OCI_CTL[ENAOCI][node] clear. See
654 L2C_TAD()_ERR for logged information.
655 During normal hardware operation, an indication of a software failure and may be
656 considered fatal. */
657 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Illegal read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
658 clear. Note [RDDISOCI] interrupts can occur during normal operation as the cores
659 are allowed to prefetch to nonexistent memory locations. Therefore, [RDDISOCI]
660 is for informational purposes only. See L2C_TAD()_ERR for logged information. */
661 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) RTG double-bit error.
662 See L2C_TAD()_RTG_ERR for logged information.
663 An indication of a hardware failure and may be considered fatal. */
664 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) RTG single-bit error on a read. See L2C_TAD()_RTG_ERR for logged
665 information. When [RTGSBE] is set, hardware corrected the error before using the
666 RTG tag, but did not correct any stored value. When [RTGSBE] is set, software
667 should eject the RTG location indicated by the corresponding
668 L2C_TAD()_RTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
669 before clearing [RTGSBE]. Otherwise, hardware may encounter the error again the
670 next time the same RTG location is referenced. Software may also choose to count
671 the number of these single-bit errors.
672
673 The SYS CVMCACHEWBIL2I instruction payload should have:
674 \<pre\>
675 payload\<24\> = 1
676 payload\<23:20\> = L2C_TAD()_RTG_ERR[WAY]
677 payload\<19:7\> = L2C_TAD()_RTG_ERR[L2IDX]
678 \</pre\>
679 Note that L2C_CTL[DISIDXALIAS] has no effect on the payload. */
680 uint64_t reserved_19_31 : 13;
681 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Global sync timeout. Should not occur during normal operation. This may be an
682 indication of hardware failure, and may be considered fatal. */
683 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) An LFB entry (or more) has encountered a timeout condition When [LFBTO] timeout
684 condition occurs L2C_TAD()_TIMEOUT is loaded. L2C_TAD()_TIMEOUT is loaded with
685 info from the first LFB that timed out. if multiple LFB timed out
686 simultaneously, then the it will capture info from the lowest LFB number that
687 timed out.
688 Should not occur during normal operation. OCI/CCPI link failures may cause this
689 failure. This may be an indication of hardware failure, and may be considered
690 fatal. */
691 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Illegal write to disabled LMC error. A DRAM write arrived before LMC was enabled.
692 Should not occur during normal operation.
693 This may be considered fatal. */
694 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Illegal read to disabled LMC error. A DRAM read arrived before LMC was enabled.
695 Should not occur during normal operation.
696 This may be considered fatal. */
697 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Read reference outside all the defined and enabled address space
698 control (ASC) regions, or secure read reference to an ASC region
699 not enabled for secure access, or nonsecure read reference to an ASC
700 region not enabled for nonsecure access.
701 [RDNXM] interrupts can occur during normal operation as the cores are
702 allowed to prefetch to nonexistent memory locations. Therefore,
703 [RDNXM] is for informational purposes only.
704 See L2C_TAD()_ERR for logged information.
705 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
706 L2C_ASC_REGION()_ATTR for ASC region specification. */
707 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Write reference outside all the defined and enabled address space
708 control (ASC) regions, or secure write reference to an ASC region
709 not enabled for secure access, or nonsecure write reference to an
710 ASC region not enabled for nonsecure access.
711 This may be an indication of software
712 failure, and may be considered fatal.
713 See L2C_TAD()_ERR for logged information.
714 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
715 L2C_ASC_REGION()_ATTR for ASC region specification. */
716 uint64_t reserved_11_12 : 2;
717 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) No way was available for allocation. L2C sets [NOWAY] during its processing of a
718 transaction whenever it needed/wanted to allocate a WAY in the L2 cache, but was
719 unable to. When this bit = 1, it is (generally) not an indication that L2C
720 failed to complete transactions. Rather, it is a hint of possible performance
721 degradation. (For example, L2C must read- modify-write DRAM for every
722 transaction that updates some, but not all, of the bytes in a cache block,
723 misses in the L2 cache, and cannot allocate a WAY.) There is one 'failure' case
724 where L2C sets [NOWAY]: when it cannot leave a block locked in the L2 cache as
725 part of a LCKL2 transaction. See L2C_TTG()_ERR for logged information. */
726 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) TAG double-bit error occurred. See L2C_TTG()_ERR for logged information.
727 This is an indication of a hardware failure and may be considered fatal. */
728 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) TAG single-bit error on a read. See L2C_TAD()_TTG_ERR for logged
729 information. When [TAGSBE] is set, hardware corrected the error before using the
730 tag, but did not correct any stored value. When [TAGSBE] is set, software should
731 eject the TAG location indicated by the corresponding
732 L2C_TAD()_TTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
733 before clearing [TAGSBE]. Otherwise, hardware may encounter the error again the
734 next time the same TAG location is referenced. Software may also choose to count
735 the number of these single-bit errors.
736
737 The SYS CVMCACHEWBIL2I instruction payload should have:
738 \<pre\>
739 payload\<24\> = 0
740 payload\<23:20\> = L2C_TAD()_TTG_ERR[WAY]
741 payload\<19:7\> = L2C_TAD()_TTG_ERR[L2IDX]
742 \</pre\>
743 Note that L2C_CTL[DISIDXALIAS] has no effect on this payload. */
744 uint64_t reserved_6_7 : 2;
745 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) FBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
746 indication of a hardware failure and may be considered fatal. */
747 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) FBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
748 information. Hardware automatically corrected the error. Software may choose to
749 count the number of these single-bit errors. */
750 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) SBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
751 indication of a hardware failure and may be considered fatal. */
752 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) SBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
753 information. Hardware automatically corrected the error. Software may choose to
754 count the number of these single-bit errors. */
755 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) L2D double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
756 indication of a hardware failure and may be considered fatal. */
757 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) L2D single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
758 information. When [L2DSBE] is set, hardware corrected the error before using the
759 data, but did not correct any stored value. When [L2DSBE] is set, software
760 should eject the cache block indicated by the corresponding
761 L2C_TAD()_TQD_ERR[QDNUM,L2DIDX] (via a SYS CVMCACHEWBIL2I instruction below)
762 before clearing [L2DSBE]. Otherwise, hardware may encounter the error again the
763 next time the same L2D location is referenced. Software may also choose to count
764 the number of these single-bit errors.
765
766 The SYS CVMCACHEWBIL2I instruction payload should have:
767 \<pre\>
768 payload\<24\> = 0
769 payload\<23:20\> = L2C_TAD()_TQD_ERR[L2DIDX]\<10:7\> // way
770 payload\<19:13\> = L2C_TAD()_TQD_ERR[L2DIDX]\<6:0\> // index\<12:6\>
771 payload\<12:11\> = L2C_TAD()_TQD_ERR[L2DIDX]\<12:11\> // index\<5:4\>
772 payload\<10\> = L2C_TAD()_TQD_ERR[QDNUM]\<2\> // index\<3\>
773 payload\<9:7\> = tad // index\<2:0\>
774 \</pre\>
775
776 where tad is the TAD index from this CSR. Note that L2C_CTL[DISIDXALIAS] has no
777 effect on the payload. */
778 #else /* Word 0 - Little Endian */
779 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) L2D single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
780 information. When [L2DSBE] is set, hardware corrected the error before using the
781 data, but did not correct any stored value. When [L2DSBE] is set, software
782 should eject the cache block indicated by the corresponding
783 L2C_TAD()_TQD_ERR[QDNUM,L2DIDX] (via a SYS CVMCACHEWBIL2I instruction below)
784 before clearing [L2DSBE]. Otherwise, hardware may encounter the error again the
785 next time the same L2D location is referenced. Software may also choose to count
786 the number of these single-bit errors.
787
788 The SYS CVMCACHEWBIL2I instruction payload should have:
789 \<pre\>
790 payload\<24\> = 0
791 payload\<23:20\> = L2C_TAD()_TQD_ERR[L2DIDX]\<10:7\> // way
792 payload\<19:13\> = L2C_TAD()_TQD_ERR[L2DIDX]\<6:0\> // index\<12:6\>
793 payload\<12:11\> = L2C_TAD()_TQD_ERR[L2DIDX]\<12:11\> // index\<5:4\>
794 payload\<10\> = L2C_TAD()_TQD_ERR[QDNUM]\<2\> // index\<3\>
795 payload\<9:7\> = tad // index\<2:0\>
796 \</pre\>
797
798 where tad is the TAD index from this CSR. Note that L2C_CTL[DISIDXALIAS] has no
799 effect on the payload. */
800 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) L2D double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
801 indication of a hardware failure and may be considered fatal. */
802 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) SBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
803 information. Hardware automatically corrected the error. Software may choose to
804 count the number of these single-bit errors. */
805 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) SBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
806 indication of a hardware failure and may be considered fatal. */
807 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) FBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
808 information. Hardware automatically corrected the error. Software may choose to
809 count the number of these single-bit errors. */
810 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) FBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
811 indication of a hardware failure and may be considered fatal. */
812 uint64_t reserved_6_7 : 2;
813 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) TAG single-bit error on a read. See L2C_TAD()_TTG_ERR for logged
814 information. When [TAGSBE] is set, hardware corrected the error before using the
815 tag, but did not correct any stored value. When [TAGSBE] is set, software should
816 eject the TAG location indicated by the corresponding
817 L2C_TAD()_TTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
818 before clearing [TAGSBE]. Otherwise, hardware may encounter the error again the
819 next time the same TAG location is referenced. Software may also choose to count
820 the number of these single-bit errors.
821
822 The SYS CVMCACHEWBIL2I instruction payload should have:
823 \<pre\>
824 payload\<24\> = 0
825 payload\<23:20\> = L2C_TAD()_TTG_ERR[WAY]
826 payload\<19:7\> = L2C_TAD()_TTG_ERR[L2IDX]
827 \</pre\>
828 Note that L2C_CTL[DISIDXALIAS] has no effect on this payload. */
829 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) TAG double-bit error occurred. See L2C_TTG()_ERR for logged information.
830 This is an indication of a hardware failure and may be considered fatal. */
831 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) No way was available for allocation. L2C sets [NOWAY] during its processing of a
832 transaction whenever it needed/wanted to allocate a WAY in the L2 cache, but was
833 unable to. When this bit = 1, it is (generally) not an indication that L2C
834 failed to complete transactions. Rather, it is a hint of possible performance
835 degradation. (For example, L2C must read- modify-write DRAM for every
836 transaction that updates some, but not all, of the bytes in a cache block,
837 misses in the L2 cache, and cannot allocate a WAY.) There is one 'failure' case
838 where L2C sets [NOWAY]: when it cannot leave a block locked in the L2 cache as
839 part of a LCKL2 transaction. See L2C_TTG()_ERR for logged information. */
840 uint64_t reserved_11_12 : 2;
841 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Write reference outside all the defined and enabled address space
842 control (ASC) regions, or secure write reference to an ASC region
843 not enabled for secure access, or nonsecure write reference to an
844 ASC region not enabled for nonsecure access.
845 This may be an indication of software
846 failure, and may be considered fatal.
847 See L2C_TAD()_ERR for logged information.
848 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
849 L2C_ASC_REGION()_ATTR for ASC region specification. */
850 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Read reference outside all the defined and enabled address space
851 control (ASC) regions, or secure read reference to an ASC region
852 not enabled for secure access, or nonsecure read reference to an ASC
853 region not enabled for nonsecure access.
854 [RDNXM] interrupts can occur during normal operation as the cores are
855 allowed to prefetch to nonexistent memory locations. Therefore,
856 [RDNXM] is for informational purposes only.
857 See L2C_TAD()_ERR for logged information.
858 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
859 L2C_ASC_REGION()_ATTR for ASC region specification. */
860 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Illegal read to disabled LMC error. A DRAM read arrived before LMC was enabled.
861 Should not occur during normal operation.
862 This may be considered fatal. */
863 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Illegal write to disabled LMC error. A DRAM write arrived before LMC was enabled.
864 Should not occur during normal operation.
865 This may be considered fatal. */
866 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) An LFB entry (or more) has encountered a timeout condition When [LFBTO] timeout
867 condition occurs L2C_TAD()_TIMEOUT is loaded. L2C_TAD()_TIMEOUT is loaded with
868 info from the first LFB that timed out. if multiple LFB timed out
869 simultaneously, then the it will capture info from the lowest LFB number that
870 timed out.
871 Should not occur during normal operation. OCI/CCPI link failures may cause this
872 failure. This may be an indication of hardware failure, and may be considered
873 fatal. */
874 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Global sync timeout. Should not occur during normal operation. This may be an
875 indication of hardware failure, and may be considered fatal. */
876 uint64_t reserved_19_31 : 13;
877 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) RTG single-bit error on a read. See L2C_TAD()_RTG_ERR for logged
878 information. When [RTGSBE] is set, hardware corrected the error before using the
879 RTG tag, but did not correct any stored value. When [RTGSBE] is set, software
880 should eject the RTG location indicated by the corresponding
881 L2C_TAD()_RTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
882 before clearing [RTGSBE]. Otherwise, hardware may encounter the error again the
883 next time the same RTG location is referenced. Software may also choose to count
884 the number of these single-bit errors.
885
886 The SYS CVMCACHEWBIL2I instruction payload should have:
887 \<pre\>
888 payload\<24\> = 1
889 payload\<23:20\> = L2C_TAD()_RTG_ERR[WAY]
890 payload\<19:7\> = L2C_TAD()_RTG_ERR[L2IDX]
891 \</pre\>
892 Note that L2C_CTL[DISIDXALIAS] has no effect on the payload. */
893 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) RTG double-bit error.
894 See L2C_TAD()_RTG_ERR for logged information.
895 An indication of a hardware failure and may be considered fatal. */
896 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Illegal read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
897 clear. Note [RDDISOCI] interrupts can occur during normal operation as the cores
898 are allowed to prefetch to nonexistent memory locations. Therefore, [RDDISOCI]
899 is for informational purposes only. See L2C_TAD()_ERR for logged information. */
900 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Illegal write operation to a remote node with L2C_OCI_CTL[ENAOCI][node] clear. See
901 L2C_TAD()_ERR for logged information.
902 During normal hardware operation, an indication of a software failure and may be
903 considered fatal. */
904 uint64_t reserved_36_63 : 28;
905 #endif /* Word 0 - End */
906 } s;
907 struct bdk_l2c_tadx_int_w1c_cn88xxp1
908 {
909 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
910 uint64_t reserved_36_63 : 28;
911 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Illegal write operation to a remote node with L2C_OCI_CTL[ENAOCI][node] clear. See
912 L2C_TAD()_ERR for logged information.
913 During normal hardware operation, an indication of a software failure and may be
914 considered fatal. */
915 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Illegal read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
916 clear. Note [RDDISOCI] interrupts can occur during normal operation as the cores
917 are allowed to prefetch to nonexistent memory locations. Therefore, [RDDISOCI]
918 is for informational purposes only. See L2C_TAD()_ERR for logged information. */
919 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) RTG double-bit error.
920 See L2C_TAD()_RTG_ERR for logged information.
921 An indication of a hardware failure and may be considered fatal. */
922 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) RTG single-bit error on a read. See L2C_TAD()_RTG_ERR for logged
923 information. When [RTGSBE] is set, hardware corrected the error before using the
924 RTG tag, but did not correct any stored value. When [RTGSBE] is set, software
925 should eject the RTG location indicated by the corresponding
926 L2C_TAD()_RTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
927 before clearing [RTGSBE]. Otherwise, hardware may encounter the error again the
928 next time the same RTG location is referenced. Software may also choose to count
929 the number of these single-bit errors.
930
931 The SYS CVMCACHEWBIL2I instruction payload should have:
932 \<pre\>
933 payload\<24\> = 1
934 payload\<23:20\> = L2C_TAD()_RTG_ERR[WAY]
935 payload\<19:7\> = L2C_TAD()_RTG_ERR[L2IDX]
936 \</pre\>
937 Note that L2C_CTL[DISIDXALIAS] has no effect on the payload. */
938 uint64_t reserved_19_31 : 13;
939 uint64_t reserved_18 : 1;
940 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) An LFB entry (or more) has encountered a timeout condition When [LFBTO] timeout
941 condition occurs L2C_TAD()_TIMEOUT is loaded. L2C_TAD()_TIMEOUT is loaded with
942 info from the first LFB that timed out. if multiple LFB timed out
943 simultaneously, then the it will capture info from the lowest LFB number that
944 timed out.
945 Should not occur during normal operation. OCI/CCPI link failures may cause this
946 failure. This may be an indication of hardware failure, and may be considered
947 fatal. */
948 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Illegal write to disabled LMC error. A DRAM write arrived before LMC was enabled.
949 Should not occur during normal operation.
950 This may be considered fatal. */
951 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Illegal read to disabled LMC error. A DRAM read arrived before LMC was enabled.
952 Should not occur during normal operation.
953 This may be considered fatal. */
954 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Read reference outside all the defined and enabled address space
955 control (ASC) regions, or secure read reference to an ASC region
956 not enabled for secure access, or nonsecure read reference to an ASC
957 region not enabled for nonsecure access.
958 [RDNXM] interrupts can occur during normal operation as the cores are
959 allowed to prefetch to nonexistent memory locations. Therefore,
960 [RDNXM] is for informational purposes only.
961 See L2C_TAD()_ERR for logged information.
962 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
963 L2C_ASC_REGION()_ATTR for ASC region specification. */
964 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Write reference outside all the defined and enabled address space
965 control (ASC) regions, or secure write reference to an ASC region
966 not enabled for secure access, or nonsecure write reference to an
967 ASC region not enabled for nonsecure access.
968 This may be an indication of software
969 failure, and may be considered fatal.
970 See L2C_TAD()_ERR for logged information.
971 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
972 L2C_ASC_REGION()_ATTR for ASC region specification. */
973 uint64_t reserved_11_12 : 2;
974 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) No way was available for allocation. L2C sets [NOWAY] during its processing of a
975 transaction whenever it needed/wanted to allocate a WAY in the L2 cache, but was
976 unable to. When this bit = 1, it is (generally) not an indication that L2C
977 failed to complete transactions. Rather, it is a hint of possible performance
978 degradation. (For example, L2C must read- modify-write DRAM for every
979 transaction that updates some, but not all, of the bytes in a cache block,
980 misses in the L2 cache, and cannot allocate a WAY.) There is one 'failure' case
981 where L2C sets [NOWAY]: when it cannot leave a block locked in the L2 cache as
982 part of a LCKL2 transaction. See L2C_TTG()_ERR for logged information. */
983 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) TAG double-bit error occurred. See L2C_TTG()_ERR for logged information.
984 This is an indication of a hardware failure and may be considered fatal. */
985 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) TAG single-bit error on a read. See L2C_TAD()_TTG_ERR for logged
986 information. When [TAGSBE] is set, hardware corrected the error before using the
987 tag, but did not correct any stored value. When [TAGSBE] is set, software should
988 eject the TAG location indicated by the corresponding
989 L2C_TAD()_TTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
990 before clearing [TAGSBE]. Otherwise, hardware may encounter the error again the
991 next time the same TAG location is referenced. Software may also choose to count
992 the number of these single-bit errors.
993
994 The SYS CVMCACHEWBIL2I instruction payload should have:
995 \<pre\>
996 payload\<24\> = 0
997 payload\<23:20\> = L2C_TAD()_TTG_ERR[WAY]
998 payload\<19:7\> = L2C_TAD()_TTG_ERR[L2IDX]
999 \</pre\>
1000 Note that L2C_CTL[DISIDXALIAS] has no effect on this payload. */
1001 uint64_t reserved_6_7 : 2;
1002 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) FBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1003 indication of a hardware failure and may be considered fatal. */
1004 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) FBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1005 information. Hardware automatically corrected the error. Software may choose to
1006 count the number of these single-bit errors. */
1007 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) SBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1008 indication of a hardware failure and may be considered fatal. */
1009 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) SBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1010 information. Hardware automatically corrected the error. Software may choose to
1011 count the number of these single-bit errors. */
1012 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) L2D double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1013 indication of a hardware failure and may be considered fatal. */
1014 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) L2D single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1015 information. When [L2DSBE] is set, hardware corrected the error before using the
1016 data, but did not correct any stored value. When [L2DSBE] is set, software
1017 should eject the cache block indicated by the corresponding
1018 L2C_TAD()_TQD_ERR[QDNUM,L2DIDX] (via a SYS CVMCACHEWBIL2I instruction below)
1019 before clearing [L2DSBE]. Otherwise, hardware may encounter the error again the
1020 next time the same L2D location is referenced. Software may also choose to count
1021 the number of these single-bit errors.
1022
1023 The SYS CVMCACHEWBIL2I instruction payload should have:
1024 \<pre\>
1025 payload\<24\> = 0
1026 payload\<23:20\> = L2C_TAD()_TQD_ERR[L2DIDX]\<10:7\> // way
1027 payload\<19:13\> = L2C_TAD()_TQD_ERR[L2DIDX]\<6:0\> // index\<12:6\>
1028 payload\<12:11\> = L2C_TAD()_TQD_ERR[L2DIDX]\<12:11\> // index\<5:4\>
1029 payload\<10\> = L2C_TAD()_TQD_ERR[QDNUM]\<2\> // index\<3\>
1030 payload\<9:7\> = tad // index\<2:0\>
1031 \</pre\>
1032
1033 where tad is the TAD index from this CSR. Note that L2C_CTL[DISIDXALIAS] has no
1034 effect on the payload. */
1035 #else /* Word 0 - Little Endian */
1036 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) L2D single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1037 information. When [L2DSBE] is set, hardware corrected the error before using the
1038 data, but did not correct any stored value. When [L2DSBE] is set, software
1039 should eject the cache block indicated by the corresponding
1040 L2C_TAD()_TQD_ERR[QDNUM,L2DIDX] (via a SYS CVMCACHEWBIL2I instruction below)
1041 before clearing [L2DSBE]. Otherwise, hardware may encounter the error again the
1042 next time the same L2D location is referenced. Software may also choose to count
1043 the number of these single-bit errors.
1044
1045 The SYS CVMCACHEWBIL2I instruction payload should have:
1046 \<pre\>
1047 payload\<24\> = 0
1048 payload\<23:20\> = L2C_TAD()_TQD_ERR[L2DIDX]\<10:7\> // way
1049 payload\<19:13\> = L2C_TAD()_TQD_ERR[L2DIDX]\<6:0\> // index\<12:6\>
1050 payload\<12:11\> = L2C_TAD()_TQD_ERR[L2DIDX]\<12:11\> // index\<5:4\>
1051 payload\<10\> = L2C_TAD()_TQD_ERR[QDNUM]\<2\> // index\<3\>
1052 payload\<9:7\> = tad // index\<2:0\>
1053 \</pre\>
1054
1055 where tad is the TAD index from this CSR. Note that L2C_CTL[DISIDXALIAS] has no
1056 effect on the payload. */
1057 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) L2D double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1058 indication of a hardware failure and may be considered fatal. */
1059 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) SBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1060 information. Hardware automatically corrected the error. Software may choose to
1061 count the number of these single-bit errors. */
1062 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) SBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1063 indication of a hardware failure and may be considered fatal. */
1064 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) FBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1065 information. Hardware automatically corrected the error. Software may choose to
1066 count the number of these single-bit errors. */
1067 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) FBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1068 indication of a hardware failure and may be considered fatal. */
1069 uint64_t reserved_6_7 : 2;
1070 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) TAG single-bit error on a read. See L2C_TAD()_TTG_ERR for logged
1071 information. When [TAGSBE] is set, hardware corrected the error before using the
1072 tag, but did not correct any stored value. When [TAGSBE] is set, software should
1073 eject the TAG location indicated by the corresponding
1074 L2C_TAD()_TTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
1075 before clearing [TAGSBE]. Otherwise, hardware may encounter the error again the
1076 next time the same TAG location is referenced. Software may also choose to count
1077 the number of these single-bit errors.
1078
1079 The SYS CVMCACHEWBIL2I instruction payload should have:
1080 \<pre\>
1081 payload\<24\> = 0
1082 payload\<23:20\> = L2C_TAD()_TTG_ERR[WAY]
1083 payload\<19:7\> = L2C_TAD()_TTG_ERR[L2IDX]
1084 \</pre\>
1085 Note that L2C_CTL[DISIDXALIAS] has no effect on this payload. */
1086 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) TAG double-bit error occurred. See L2C_TTG()_ERR for logged information.
1087 This is an indication of a hardware failure and may be considered fatal. */
1088 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) No way was available for allocation. L2C sets [NOWAY] during its processing of a
1089 transaction whenever it needed/wanted to allocate a WAY in the L2 cache, but was
1090 unable to. When this bit = 1, it is (generally) not an indication that L2C
1091 failed to complete transactions. Rather, it is a hint of possible performance
1092 degradation. (For example, L2C must read- modify-write DRAM for every
1093 transaction that updates some, but not all, of the bytes in a cache block,
1094 misses in the L2 cache, and cannot allocate a WAY.) There is one 'failure' case
1095 where L2C sets [NOWAY]: when it cannot leave a block locked in the L2 cache as
1096 part of a LCKL2 transaction. See L2C_TTG()_ERR for logged information. */
1097 uint64_t reserved_11_12 : 2;
1098 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Write reference outside all the defined and enabled address space
1099 control (ASC) regions, or secure write reference to an ASC region
1100 not enabled for secure access, or nonsecure write reference to an
1101 ASC region not enabled for nonsecure access.
1102 This may be an indication of software
1103 failure, and may be considered fatal.
1104 See L2C_TAD()_ERR for logged information.
1105 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1106 L2C_ASC_REGION()_ATTR for ASC region specification. */
1107 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Read reference outside all the defined and enabled address space
1108 control (ASC) regions, or secure read reference to an ASC region
1109 not enabled for secure access, or nonsecure read reference to an ASC
1110 region not enabled for nonsecure access.
1111 [RDNXM] interrupts can occur during normal operation as the cores are
1112 allowed to prefetch to nonexistent memory locations. Therefore,
1113 [RDNXM] is for informational purposes only.
1114 See L2C_TAD()_ERR for logged information.
1115 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1116 L2C_ASC_REGION()_ATTR for ASC region specification. */
1117 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Illegal read to disabled LMC error. A DRAM read arrived before LMC was enabled.
1118 Should not occur during normal operation.
1119 This may be considered fatal. */
1120 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Illegal write to disabled LMC error. A DRAM write arrived before LMC was enabled.
1121 Should not occur during normal operation.
1122 This may be considered fatal. */
1123 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) An LFB entry (or more) has encountered a timeout condition When [LFBTO] timeout
1124 condition occurs L2C_TAD()_TIMEOUT is loaded. L2C_TAD()_TIMEOUT is loaded with
1125 info from the first LFB that timed out. if multiple LFB timed out
1126 simultaneously, then the it will capture info from the lowest LFB number that
1127 timed out.
1128 Should not occur during normal operation. OCI/CCPI link failures may cause this
1129 failure. This may be an indication of hardware failure, and may be considered
1130 fatal. */
1131 uint64_t reserved_18 : 1;
1132 uint64_t reserved_19_31 : 13;
1133 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) RTG single-bit error on a read. See L2C_TAD()_RTG_ERR for logged
1134 information. When [RTGSBE] is set, hardware corrected the error before using the
1135 RTG tag, but did not correct any stored value. When [RTGSBE] is set, software
1136 should eject the RTG location indicated by the corresponding
1137 L2C_TAD()_RTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
1138 before clearing [RTGSBE]. Otherwise, hardware may encounter the error again the
1139 next time the same RTG location is referenced. Software may also choose to count
1140 the number of these single-bit errors.
1141
1142 The SYS CVMCACHEWBIL2I instruction payload should have:
1143 \<pre\>
1144 payload\<24\> = 1
1145 payload\<23:20\> = L2C_TAD()_RTG_ERR[WAY]
1146 payload\<19:7\> = L2C_TAD()_RTG_ERR[L2IDX]
1147 \</pre\>
1148 Note that L2C_CTL[DISIDXALIAS] has no effect on the payload. */
1149 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) RTG double-bit error.
1150 See L2C_TAD()_RTG_ERR for logged information.
1151 An indication of a hardware failure and may be considered fatal. */
1152 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Illegal read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
1153 clear. Note [RDDISOCI] interrupts can occur during normal operation as the cores
1154 are allowed to prefetch to nonexistent memory locations. Therefore, [RDDISOCI]
1155 is for informational purposes only. See L2C_TAD()_ERR for logged information. */
1156 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Illegal write operation to a remote node with L2C_OCI_CTL[ENAOCI][node] clear. See
1157 L2C_TAD()_ERR for logged information.
1158 During normal hardware operation, an indication of a software failure and may be
1159 considered fatal. */
1160 uint64_t reserved_36_63 : 28;
1161 #endif /* Word 0 - End */
1162 } cn88xxp1;
1163 struct bdk_l2c_tadx_int_w1c_cn81xx
1164 {
1165 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1166 uint64_t reserved_36_63 : 28;
1167 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Illegal write operation to a remote node with L2C_OCI_CTL[ENAOCI][node] clear. See
1168 L2C_TAD()_ERR for logged information.
1169 During normal hardware operation, an indication of a software failure and may be
1170 considered fatal. */
1171 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Illegal read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
1172 clear. Note [RDDISOCI] interrupts can occur during normal operation as the cores
1173 are allowed to prefetch to nonexistent memory locations. Therefore, [RDDISOCI]
1174 is for informational purposes only. See L2C_TAD()_ERR for logged information. */
1175 uint64_t reserved_19_33 : 15;
1176 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Global sync timeout. Should not occur during normal operation. This may be an
1177 indication of hardware failure, and may be considered fatal. */
1178 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) An LFB entry (or more) has encountered a timeout condition When [LFBTO] timeout
1179 condition occurs L2C_TAD()_TIMEOUT is loaded. L2C_TAD()_TIMEOUT is loaded with
1180 info from the first LFB that timed out. if multiple LFB timed out
1181 simultaneously, then the it will capture info from the lowest LFB number that
1182 timed out.
1183 Should not occur during normal operation. OCI/CCPI link failures may cause this
1184 failure. This may be an indication of hardware failure, and may be considered
1185 fatal. */
1186 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Illegal write to disabled LMC error. A DRAM write arrived before LMC was enabled.
1187 Should not occur during normal operation.
1188 This may be considered fatal. */
1189 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Illegal read to disabled LMC error. A DRAM read arrived before LMC was enabled.
1190 Should not occur during normal operation.
1191 This may be considered fatal. */
1192 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Read reference outside all the defined and enabled address space
1193 control (ASC) regions, or secure read reference to an ASC region
1194 not enabled for secure access, or nonsecure read reference to an ASC
1195 region not enabled for nonsecure access.
1196 [RDNXM] interrupts can occur during normal operation as the cores are
1197 allowed to prefetch to nonexistent memory locations. Therefore,
1198 [RDNXM] is for informational purposes only.
1199 See L2C_TAD()_ERR for logged information.
1200 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1201 L2C_ASC_REGION()_ATTR for ASC region specification. */
1202 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Write reference outside all the defined and enabled address space
1203 control (ASC) regions, or secure write reference to an ASC region
1204 not enabled for secure access, or nonsecure write reference to an
1205 ASC region not enabled for nonsecure access.
1206 This may be an indication of software
1207 failure, and may be considered fatal.
1208 See L2C_TAD()_ERR for logged information.
1209 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1210 L2C_ASC_REGION()_ATTR for ASC region specification. */
1211 uint64_t reserved_11_12 : 2;
1212 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) No way was available for allocation. L2C sets [NOWAY] during its processing of a
1213 transaction whenever it needed/wanted to allocate a WAY in the L2 cache, but was
1214 unable to. When this bit = 1, it is (generally) not an indication that L2C
1215 failed to complete transactions. Rather, it is a hint of possible performance
1216 degradation. (For example, L2C must read- modify-write DRAM for every
1217 transaction that updates some, but not all, of the bytes in a cache block,
1218 misses in the L2 cache, and cannot allocate a WAY.) There is one 'failure' case
1219 where L2C sets [NOWAY]: when it cannot leave a block locked in the L2 cache as
1220 part of a LCKL2 transaction. See L2C_TTG()_ERR for logged information. */
1221 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) TAG double-bit error occurred. See L2C_TTG()_ERR for logged information.
1222 This is an indication of a hardware failure and may be considered fatal. */
1223 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) TAG single-bit error on a read. See L2C_TAD()_TTG_ERR for logged
1224 information. When [TAGSBE] is set, hardware corrected the error before using the
1225 tag, but did not correct any stored value. When [TAGSBE] is set, software should
1226 eject the TAG location indicated by the corresponding
1227 L2C_TAD()_TTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
1228 before clearing [TAGSBE]. Otherwise, hardware may encounter the error again the
1229 next time the same TAG location is referenced. Software may also choose to count
1230 the number of these single-bit errors.
1231
1232 The SYS CVMCACHEWBIL2I instruction payload should have:
1233 \<pre\>
1234 payload\<24\> = 0
1235 payload\<23:20\> = L2C_TAD()_TTG_ERR[WAY]
1236 payload\<19:7\> = L2C_TAD()_TTG_ERR[L2IDX]
1237 \</pre\>
1238 Note that L2C_CTL[DISIDXALIAS] has no effect on this payload. */
1239 uint64_t reserved_6_7 : 2;
1240 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) FBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1241 indication of a hardware failure and may be considered fatal. */
1242 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) FBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1243 information. Hardware automatically corrected the error. Software may choose to
1244 count the number of these single-bit errors. */
1245 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) SBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1246 indication of a hardware failure and may be considered fatal. */
1247 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) SBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1248 information. Hardware automatically corrected the error. Software may choose to
1249 count the number of these single-bit errors. */
1250 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) L2D double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1251 indication of a hardware failure and may be considered fatal. */
1252 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) L2D single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1253 information. When [L2DSBE] is set, hardware corrected the error before using the
1254 data, but did not correct any stored value. When [L2DSBE] is set, software
1255 should eject the cache block indicated by the corresponding
1256 L2C_TAD()_TQD_ERR[QDNUM,L2DIDX] (via a SYS CVMCACHEWBIL2I instruction below)
1257 before clearing [L2DSBE]. Otherwise, hardware may encounter the error again the
1258 next time the same L2D location is referenced. Software may also choose to count
1259 the number of these single-bit errors.
1260
1261 The SYS CVMCACHEWBIL2I instruction payload should have:
1262 \<pre\>
1263 payload\<24:21\> = 0
1264 payload\<20:17\> = L2C_TAD()_TQD_ERR[L2DIDX]\<10:7\> // way
1265 payload\<16:10\> = L2C_TAD()_TQD_ERR[L2DIDX]\<6:0\> // index\<9:3\>
1266 payload\<9:8\> = L2C_TAD()_TQD_ERR[L2DIDX]\<12:11\> // index\<2:1\>
1267 payload\<7\> = L2C_TAD()_TQD_ERR[QDNUM]\<2\> // index\<0\>
1268 \</pre\>
1269
1270 Note that L2C_CTL[DISIDXALIAS] has no effect on the payload. */
1271 #else /* Word 0 - Little Endian */
1272 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) L2D single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1273 information. When [L2DSBE] is set, hardware corrected the error before using the
1274 data, but did not correct any stored value. When [L2DSBE] is set, software
1275 should eject the cache block indicated by the corresponding
1276 L2C_TAD()_TQD_ERR[QDNUM,L2DIDX] (via a SYS CVMCACHEWBIL2I instruction below)
1277 before clearing [L2DSBE]. Otherwise, hardware may encounter the error again the
1278 next time the same L2D location is referenced. Software may also choose to count
1279 the number of these single-bit errors.
1280
1281 The SYS CVMCACHEWBIL2I instruction payload should have:
1282 \<pre\>
1283 payload\<24:21\> = 0
1284 payload\<20:17\> = L2C_TAD()_TQD_ERR[L2DIDX]\<10:7\> // way
1285 payload\<16:10\> = L2C_TAD()_TQD_ERR[L2DIDX]\<6:0\> // index\<9:3\>
1286 payload\<9:8\> = L2C_TAD()_TQD_ERR[L2DIDX]\<12:11\> // index\<2:1\>
1287 payload\<7\> = L2C_TAD()_TQD_ERR[QDNUM]\<2\> // index\<0\>
1288 \</pre\>
1289
1290 Note that L2C_CTL[DISIDXALIAS] has no effect on the payload. */
1291 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) L2D double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1292 indication of a hardware failure and may be considered fatal. */
1293 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) SBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1294 information. Hardware automatically corrected the error. Software may choose to
1295 count the number of these single-bit errors. */
1296 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) SBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1297 indication of a hardware failure and may be considered fatal. */
1298 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) FBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1299 information. Hardware automatically corrected the error. Software may choose to
1300 count the number of these single-bit errors. */
1301 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) FBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1302 indication of a hardware failure and may be considered fatal. */
1303 uint64_t reserved_6_7 : 2;
1304 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) TAG single-bit error on a read. See L2C_TAD()_TTG_ERR for logged
1305 information. When [TAGSBE] is set, hardware corrected the error before using the
1306 tag, but did not correct any stored value. When [TAGSBE] is set, software should
1307 eject the TAG location indicated by the corresponding
1308 L2C_TAD()_TTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
1309 before clearing [TAGSBE]. Otherwise, hardware may encounter the error again the
1310 next time the same TAG location is referenced. Software may also choose to count
1311 the number of these single-bit errors.
1312
1313 The SYS CVMCACHEWBIL2I instruction payload should have:
1314 \<pre\>
1315 payload\<24\> = 0
1316 payload\<23:20\> = L2C_TAD()_TTG_ERR[WAY]
1317 payload\<19:7\> = L2C_TAD()_TTG_ERR[L2IDX]
1318 \</pre\>
1319 Note that L2C_CTL[DISIDXALIAS] has no effect on this payload. */
1320 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) TAG double-bit error occurred. See L2C_TTG()_ERR for logged information.
1321 This is an indication of a hardware failure and may be considered fatal. */
1322 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) No way was available for allocation. L2C sets [NOWAY] during its processing of a
1323 transaction whenever it needed/wanted to allocate a WAY in the L2 cache, but was
1324 unable to. When this bit = 1, it is (generally) not an indication that L2C
1325 failed to complete transactions. Rather, it is a hint of possible performance
1326 degradation. (For example, L2C must read- modify-write DRAM for every
1327 transaction that updates some, but not all, of the bytes in a cache block,
1328 misses in the L2 cache, and cannot allocate a WAY.) There is one 'failure' case
1329 where L2C sets [NOWAY]: when it cannot leave a block locked in the L2 cache as
1330 part of a LCKL2 transaction. See L2C_TTG()_ERR for logged information. */
1331 uint64_t reserved_11_12 : 2;
1332 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Write reference outside all the defined and enabled address space
1333 control (ASC) regions, or secure write reference to an ASC region
1334 not enabled for secure access, or nonsecure write reference to an
1335 ASC region not enabled for nonsecure access.
1336 This may be an indication of software
1337 failure, and may be considered fatal.
1338 See L2C_TAD()_ERR for logged information.
1339 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1340 L2C_ASC_REGION()_ATTR for ASC region specification. */
1341 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Read reference outside all the defined and enabled address space
1342 control (ASC) regions, or secure read reference to an ASC region
1343 not enabled for secure access, or nonsecure read reference to an ASC
1344 region not enabled for nonsecure access.
1345 [RDNXM] interrupts can occur during normal operation as the cores are
1346 allowed to prefetch to nonexistent memory locations. Therefore,
1347 [RDNXM] is for informational purposes only.
1348 See L2C_TAD()_ERR for logged information.
1349 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1350 L2C_ASC_REGION()_ATTR for ASC region specification. */
1351 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Illegal read to disabled LMC error. A DRAM read arrived before LMC was enabled.
1352 Should not occur during normal operation.
1353 This may be considered fatal. */
1354 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Illegal write to disabled LMC error. A DRAM write arrived before LMC was enabled.
1355 Should not occur during normal operation.
1356 This may be considered fatal. */
1357 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) An LFB entry (or more) has encountered a timeout condition When [LFBTO] timeout
1358 condition occurs L2C_TAD()_TIMEOUT is loaded. L2C_TAD()_TIMEOUT is loaded with
1359 info from the first LFB that timed out. if multiple LFB timed out
1360 simultaneously, then the it will capture info from the lowest LFB number that
1361 timed out.
1362 Should not occur during normal operation. OCI/CCPI link failures may cause this
1363 failure. This may be an indication of hardware failure, and may be considered
1364 fatal. */
1365 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Global sync timeout. Should not occur during normal operation. This may be an
1366 indication of hardware failure, and may be considered fatal. */
1367 uint64_t reserved_19_33 : 15;
1368 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Illegal read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
1369 clear. Note [RDDISOCI] interrupts can occur during normal operation as the cores
1370 are allowed to prefetch to nonexistent memory locations. Therefore, [RDDISOCI]
1371 is for informational purposes only. See L2C_TAD()_ERR for logged information. */
1372 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Illegal write operation to a remote node with L2C_OCI_CTL[ENAOCI][node] clear. See
1373 L2C_TAD()_ERR for logged information.
1374 During normal hardware operation, an indication of a software failure and may be
1375 considered fatal. */
1376 uint64_t reserved_36_63 : 28;
1377 #endif /* Word 0 - End */
1378 } cn81xx;
1379 struct bdk_l2c_tadx_int_w1c_cn83xx
1380 {
1381 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1382 uint64_t reserved_36_63 : 28;
1383 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Illegal write operation to a remote node with L2C_OCI_CTL[ENAOCI][node] clear. See
1384 L2C_TAD()_ERR for logged information.
1385 During normal hardware operation, an indication of a software failure and may be
1386 considered fatal. */
1387 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Illegal read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
1388 clear. Note [RDDISOCI] interrupts can occur during normal operation as the cores
1389 are allowed to prefetch to nonexistent memory locations. Therefore, [RDDISOCI]
1390 is for informational purposes only. See L2C_TAD()_ERR for logged information. */
1391 uint64_t reserved_19_33 : 15;
1392 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Global sync timeout. Should not occur during normal operation. This may be an
1393 indication of hardware failure, and may be considered fatal. */
1394 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) An LFB entry (or more) has encountered a timeout condition When [LFBTO] timeout
1395 condition occurs L2C_TAD()_TIMEOUT is loaded. L2C_TAD()_TIMEOUT is loaded with
1396 info from the first LFB that timed out. if multiple LFB timed out
1397 simultaneously, then the it will capture info from the lowest LFB number that
1398 timed out.
1399 Should not occur during normal operation. OCI/CCPI link failures may cause this
1400 failure. This may be an indication of hardware failure, and may be considered
1401 fatal. */
1402 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Illegal write to disabled LMC error. A DRAM write arrived before LMC was enabled.
1403 Should not occur during normal operation.
1404 This may be considered fatal. */
1405 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Illegal read to disabled LMC error. A DRAM read arrived before LMC was enabled.
1406 Should not occur during normal operation.
1407 This may be considered fatal. */
1408 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Read reference outside all the defined and enabled address space
1409 control (ASC) regions, or secure read reference to an ASC region
1410 not enabled for secure access, or nonsecure read reference to an ASC
1411 region not enabled for nonsecure access.
1412 [RDNXM] interrupts can occur during normal operation as the cores are
1413 allowed to prefetch to nonexistent memory locations. Therefore,
1414 [RDNXM] is for informational purposes only.
1415 See L2C_TAD()_ERR for logged information.
1416 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1417 L2C_ASC_REGION()_ATTR for ASC region specification. */
1418 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Write reference outside all the defined and enabled address space
1419 control (ASC) regions, or secure write reference to an ASC region
1420 not enabled for secure access, or nonsecure write reference to an
1421 ASC region not enabled for nonsecure access.
1422 This may be an indication of software
1423 failure, and may be considered fatal.
1424 See L2C_TAD()_ERR for logged information.
1425 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1426 L2C_ASC_REGION()_ATTR for ASC region specification. */
1427 uint64_t reserved_11_12 : 2;
1428 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) No way was available for allocation. L2C sets [NOWAY] during its processing of a
1429 transaction whenever it needed/wanted to allocate a WAY in the L2 cache, but was
1430 unable to. When this bit = 1, it is (generally) not an indication that L2C
1431 failed to complete transactions. Rather, it is a hint of possible performance
1432 degradation. (For example, L2C must read- modify-write DRAM for every
1433 transaction that updates some, but not all, of the bytes in a cache block,
1434 misses in the L2 cache, and cannot allocate a WAY.) There is one 'failure' case
1435 where L2C sets [NOWAY]: when it cannot leave a block locked in the L2 cache as
1436 part of a LCKL2 transaction. See L2C_TTG()_ERR for logged information. */
1437 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) TAG double-bit error occurred. See L2C_TTG()_ERR for logged information.
1438 This is an indication of a hardware failure and may be considered fatal. */
1439 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) TAG single-bit error on a read. See L2C_TAD()_TTG_ERR for logged
1440 information. When [TAGSBE] is set, hardware corrected the error before using the
1441 tag, but did not correct any stored value. When [TAGSBE] is set, software should
1442 eject the TAG location indicated by the corresponding
1443 L2C_TAD()_TTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
1444 before clearing [TAGSBE]. Otherwise, hardware may encounter the error again the
1445 next time the same TAG location is referenced. Software may also choose to count
1446 the number of these single-bit errors.
1447
1448 The SYS CVMCACHEWBIL2I instruction payload should have:
1449 \<pre\>
1450 payload\<24\> = 0
1451 payload\<23:20\> = L2C_TAD()_TTG_ERR[WAY]
1452 payload\<19:7\> = L2C_TAD()_TTG_ERR[L2IDX]
1453 \</pre\>
1454 Note that L2C_CTL[DISIDXALIAS] has no effect on this payload. */
1455 uint64_t reserved_6_7 : 2;
1456 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) FBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1457 indication of a hardware failure and may be considered fatal. */
1458 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) FBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1459 information. Hardware automatically corrected the error. Software may choose to
1460 count the number of these single-bit errors. */
1461 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) SBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1462 indication of a hardware failure and may be considered fatal. */
1463 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) SBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1464 information. Hardware automatically corrected the error. Software may choose to
1465 count the number of these single-bit errors. */
1466 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) L2D double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1467 indication of a hardware failure and may be considered fatal. */
1468 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) L2D single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1469 information. When [L2DSBE] is set, hardware corrected the error before using the
1470 data, but did not correct any stored value. When [L2DSBE] is set, software
1471 should eject the cache block indicated by the corresponding
1472 L2C_TAD()_TQD_ERR[QDNUM,L2DIDX] (via a SYS CVMCACHEWBIL2I instruction below)
1473 before clearing [L2DSBE]. Otherwise, hardware may encounter the error again the
1474 next time the same L2D location is referenced. Software may also choose to count
1475 the number of these single-bit errors.
1476
1477 The SYS CVMCACHEWBIL2I instruction payload should have:
1478 \<pre\>
1479 payload\<24:23\> = 0
1480 payload\<22:19\> = L2C_TAD()_TQD_ERR[L2DIDX]\<10:7\> // way
1481 payload\<18:12\> = L2C_TAD()_TQD_ERR[L2DIDX]\<6:0\> // index\<11:5\>
1482 payload\<11:10\> = L2C_TAD()_TQD_ERR[L2DIDX]\<12:11\> // index\<4:3\>
1483 payload\<9\> = L2C_TAD()_TQD_ERR[QDNUM]\<2\> // index\<2\>
1484 payload\<8:7\> = tad // index\<1:0\>
1485 \</pre\>
1486
1487 where tad is the TAD index from this CSR. Note that L2C_CTL[DISIDXALIAS] has no
1488 effect on the payload. */
1489 #else /* Word 0 - Little Endian */
1490 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) L2D single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1491 information. When [L2DSBE] is set, hardware corrected the error before using the
1492 data, but did not correct any stored value. When [L2DSBE] is set, software
1493 should eject the cache block indicated by the corresponding
1494 L2C_TAD()_TQD_ERR[QDNUM,L2DIDX] (via a SYS CVMCACHEWBIL2I instruction below)
1495 before clearing [L2DSBE]. Otherwise, hardware may encounter the error again the
1496 next time the same L2D location is referenced. Software may also choose to count
1497 the number of these single-bit errors.
1498
1499 The SYS CVMCACHEWBIL2I instruction payload should have:
1500 \<pre\>
1501 payload\<24:23\> = 0
1502 payload\<22:19\> = L2C_TAD()_TQD_ERR[L2DIDX]\<10:7\> // way
1503 payload\<18:12\> = L2C_TAD()_TQD_ERR[L2DIDX]\<6:0\> // index\<11:5\>
1504 payload\<11:10\> = L2C_TAD()_TQD_ERR[L2DIDX]\<12:11\> // index\<4:3\>
1505 payload\<9\> = L2C_TAD()_TQD_ERR[QDNUM]\<2\> // index\<2\>
1506 payload\<8:7\> = tad // index\<1:0\>
1507 \</pre\>
1508
1509 where tad is the TAD index from this CSR. Note that L2C_CTL[DISIDXALIAS] has no
1510 effect on the payload. */
1511 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) L2D double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1512 indication of a hardware failure and may be considered fatal. */
1513 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) SBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1514 information. Hardware automatically corrected the error. Software may choose to
1515 count the number of these single-bit errors. */
1516 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) SBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1517 indication of a hardware failure and may be considered fatal. */
1518 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) FBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1519 information. Hardware automatically corrected the error. Software may choose to
1520 count the number of these single-bit errors. */
1521 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) FBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1522 indication of a hardware failure and may be considered fatal. */
1523 uint64_t reserved_6_7 : 2;
1524 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) TAG single-bit error on a read. See L2C_TAD()_TTG_ERR for logged
1525 information. When [TAGSBE] is set, hardware corrected the error before using the
1526 tag, but did not correct any stored value. When [TAGSBE] is set, software should
1527 eject the TAG location indicated by the corresponding
1528 L2C_TAD()_TTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
1529 before clearing [TAGSBE]. Otherwise, hardware may encounter the error again the
1530 next time the same TAG location is referenced. Software may also choose to count
1531 the number of these single-bit errors.
1532
1533 The SYS CVMCACHEWBIL2I instruction payload should have:
1534 \<pre\>
1535 payload\<24\> = 0
1536 payload\<23:20\> = L2C_TAD()_TTG_ERR[WAY]
1537 payload\<19:7\> = L2C_TAD()_TTG_ERR[L2IDX]
1538 \</pre\>
1539 Note that L2C_CTL[DISIDXALIAS] has no effect on this payload. */
1540 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) TAG double-bit error occurred. See L2C_TTG()_ERR for logged information.
1541 This is an indication of a hardware failure and may be considered fatal. */
1542 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) No way was available for allocation. L2C sets [NOWAY] during its processing of a
1543 transaction whenever it needed/wanted to allocate a WAY in the L2 cache, but was
1544 unable to. When this bit = 1, it is (generally) not an indication that L2C
1545 failed to complete transactions. Rather, it is a hint of possible performance
1546 degradation. (For example, L2C must read- modify-write DRAM for every
1547 transaction that updates some, but not all, of the bytes in a cache block,
1548 misses in the L2 cache, and cannot allocate a WAY.) There is one 'failure' case
1549 where L2C sets [NOWAY]: when it cannot leave a block locked in the L2 cache as
1550 part of a LCKL2 transaction. See L2C_TTG()_ERR for logged information. */
1551 uint64_t reserved_11_12 : 2;
1552 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Write reference outside all the defined and enabled address space
1553 control (ASC) regions, or secure write reference to an ASC region
1554 not enabled for secure access, or nonsecure write reference to an
1555 ASC region not enabled for nonsecure access.
1556 This may be an indication of software
1557 failure, and may be considered fatal.
1558 See L2C_TAD()_ERR for logged information.
1559 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1560 L2C_ASC_REGION()_ATTR for ASC region specification. */
1561 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Read reference outside all the defined and enabled address space
1562 control (ASC) regions, or secure read reference to an ASC region
1563 not enabled for secure access, or nonsecure read reference to an ASC
1564 region not enabled for nonsecure access.
1565 [RDNXM] interrupts can occur during normal operation as the cores are
1566 allowed to prefetch to nonexistent memory locations. Therefore,
1567 [RDNXM] is for informational purposes only.
1568 See L2C_TAD()_ERR for logged information.
1569 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1570 L2C_ASC_REGION()_ATTR for ASC region specification. */
1571 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Illegal read to disabled LMC error. A DRAM read arrived before LMC was enabled.
1572 Should not occur during normal operation.
1573 This may be considered fatal. */
1574 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Illegal write to disabled LMC error. A DRAM write arrived before LMC was enabled.
1575 Should not occur during normal operation.
1576 This may be considered fatal. */
1577 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) An LFB entry (or more) has encountered a timeout condition When [LFBTO] timeout
1578 condition occurs L2C_TAD()_TIMEOUT is loaded. L2C_TAD()_TIMEOUT is loaded with
1579 info from the first LFB that timed out. if multiple LFB timed out
1580 simultaneously, then the it will capture info from the lowest LFB number that
1581 timed out.
1582 Should not occur during normal operation. OCI/CCPI link failures may cause this
1583 failure. This may be an indication of hardware failure, and may be considered
1584 fatal. */
1585 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Global sync timeout. Should not occur during normal operation. This may be an
1586 indication of hardware failure, and may be considered fatal. */
1587 uint64_t reserved_19_33 : 15;
1588 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Illegal read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
1589 clear. Note [RDDISOCI] interrupts can occur during normal operation as the cores
1590 are allowed to prefetch to nonexistent memory locations. Therefore, [RDDISOCI]
1591 is for informational purposes only. See L2C_TAD()_ERR for logged information. */
1592 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Illegal write operation to a remote node with L2C_OCI_CTL[ENAOCI][node] clear. See
1593 L2C_TAD()_ERR for logged information.
1594 During normal hardware operation, an indication of a software failure and may be
1595 considered fatal. */
1596 uint64_t reserved_36_63 : 28;
1597 #endif /* Word 0 - End */
1598 } cn83xx;
1599 struct bdk_l2c_tadx_int_w1c_cn88xxp2
1600 {
1601 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1602 uint64_t reserved_36_63 : 28;
1603 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Illegal write operation to a remote node with L2C_OCI_CTL[ENAOCI][node] clear. See
1604 L2C_TAD()_ERR for logged information.
1605 During normal hardware operation, an indication of a software failure and may be
1606 considered fatal. */
1607 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Illegal read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
1608 clear. Note [RDDISOCI] interrupts can occur during normal operation as the cores
1609 are allowed to prefetch to nonexistent memory locations. Therefore, [RDDISOCI]
1610 is for informational purposes only. See L2C_TAD()_ERR for logged information. */
1611 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) RTG double-bit error.
1612 See L2C_TAD()_RTG_ERR for logged information.
1613 An indication of a hardware failure and may be considered fatal. */
1614 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) RTG single-bit error on a read. See L2C_TAD()_RTG_ERR for logged
1615 information. When [RTGSBE] is set, hardware corrected the error before using the
1616 RTG tag, but did not correct any stored value. When [RTGSBE] is set, software
1617 should eject the RTG location indicated by the corresponding
1618 L2C_TAD()_RTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
1619 before clearing [RTGSBE]. Otherwise, hardware may encounter the error again the
1620 next time the same RTG location is referenced. Software may also choose to count
1621 the number of these single-bit errors.
1622
1623 The SYS CVMCACHEWBIL2I instruction payload should have:
1624 \<pre\>
1625 payload\<24\> = 1
1626 payload\<23:20\> = L2C_TAD()_RTG_ERR[WAY]
1627 payload\<19:7\> = L2C_TAD()_RTG_ERR[L2IDX]
1628 \</pre\>
1629 Note that L2C_CTL[DISIDXALIAS] has no effect on the payload. */
1630 uint64_t reserved_19_31 : 13;
1631 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Global sync OCI timeout. Should not occur during normal operation. OCI/CCPI link
1632 failures may cause this failure. This may be an indication of hardware failure,
1633 and may be considered fatal. */
1634 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) An LFB entry (or more) has encountered a timeout condition When [LFBTO] timeout
1635 condition occurs L2C_TAD()_TIMEOUT is loaded. L2C_TAD()_TIMEOUT is loaded with
1636 info from the first LFB that timed out. if multiple LFB timed out
1637 simultaneously, then the it will capture info from the lowest LFB number that
1638 timed out.
1639 Should not occur during normal operation. OCI/CCPI link failures may cause this
1640 failure. This may be an indication of hardware failure, and may be considered
1641 fatal. */
1642 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Illegal write to disabled LMC error. A DRAM write arrived before LMC was enabled.
1643 Should not occur during normal operation.
1644 This may be considered fatal. */
1645 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Illegal read to disabled LMC error. A DRAM read arrived before LMC was enabled.
1646 Should not occur during normal operation.
1647 This may be considered fatal. */
1648 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Read reference outside all the defined and enabled address space
1649 control (ASC) regions, or secure read reference to an ASC region
1650 not enabled for secure access, or nonsecure read reference to an ASC
1651 region not enabled for nonsecure access.
1652 [RDNXM] interrupts can occur during normal operation as the cores are
1653 allowed to prefetch to nonexistent memory locations. Therefore,
1654 [RDNXM] is for informational purposes only.
1655 See L2C_TAD()_ERR for logged information.
1656 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1657 L2C_ASC_REGION()_ATTR for ASC region specification. */
1658 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Write reference outside all the defined and enabled address space
1659 control (ASC) regions, or secure write reference to an ASC region
1660 not enabled for secure access, or nonsecure write reference to an
1661 ASC region not enabled for nonsecure access.
1662 This may be an indication of software
1663 failure, and may be considered fatal.
1664 See L2C_TAD()_ERR for logged information.
1665 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1666 L2C_ASC_REGION()_ATTR for ASC region specification. */
1667 uint64_t reserved_11_12 : 2;
1668 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) No way was available for allocation. L2C sets [NOWAY] during its processing of a
1669 transaction whenever it needed/wanted to allocate a WAY in the L2 cache, but was
1670 unable to. When this bit = 1, it is (generally) not an indication that L2C
1671 failed to complete transactions. Rather, it is a hint of possible performance
1672 degradation. (For example, L2C must read- modify-write DRAM for every
1673 transaction that updates some, but not all, of the bytes in a cache block,
1674 misses in the L2 cache, and cannot allocate a WAY.) There is one 'failure' case
1675 where L2C sets [NOWAY]: when it cannot leave a block locked in the L2 cache as
1676 part of a LCKL2 transaction. See L2C_TTG()_ERR for logged information. */
1677 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) TAG double-bit error occurred. See L2C_TTG()_ERR for logged information.
1678 This is an indication of a hardware failure and may be considered fatal. */
1679 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) TAG single-bit error on a read. See L2C_TAD()_TTG_ERR for logged
1680 information. When [TAGSBE] is set, hardware corrected the error before using the
1681 tag, but did not correct any stored value. When [TAGSBE] is set, software should
1682 eject the TAG location indicated by the corresponding
1683 L2C_TAD()_TTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
1684 before clearing [TAGSBE]. Otherwise, hardware may encounter the error again the
1685 next time the same TAG location is referenced. Software may also choose to count
1686 the number of these single-bit errors.
1687
1688 The SYS CVMCACHEWBIL2I instruction payload should have:
1689 \<pre\>
1690 payload\<24\> = 0
1691 payload\<23:20\> = L2C_TAD()_TTG_ERR[WAY]
1692 payload\<19:7\> = L2C_TAD()_TTG_ERR[L2IDX]
1693 \</pre\>
1694 Note that L2C_CTL[DISIDXALIAS] has no effect on this payload. */
1695 uint64_t reserved_6_7 : 2;
1696 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) FBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1697 indication of a hardware failure and may be considered fatal. */
1698 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) FBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1699 information. Hardware automatically corrected the error. Software may choose to
1700 count the number of these single-bit errors. */
1701 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) SBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1702 indication of a hardware failure and may be considered fatal. */
1703 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) SBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1704 information. Hardware automatically corrected the error. Software may choose to
1705 count the number of these single-bit errors. */
1706 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) L2D double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1707 indication of a hardware failure and may be considered fatal. */
1708 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) L2D single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1709 information. When [L2DSBE] is set, hardware corrected the error before using the
1710 data, but did not correct any stored value. When [L2DSBE] is set, software
1711 should eject the cache block indicated by the corresponding
1712 L2C_TAD()_TQD_ERR[QDNUM,L2DIDX] (via a SYS CVMCACHEWBIL2I instruction below)
1713 before clearing [L2DSBE]. Otherwise, hardware may encounter the error again the
1714 next time the same L2D location is referenced. Software may also choose to count
1715 the number of these single-bit errors.
1716
1717 The SYS CVMCACHEWBIL2I instruction payload should have:
1718 \<pre\>
1719 payload\<24\> = 0
1720 payload\<23:20\> = L2C_TAD()_TQD_ERR[L2DIDX]\<10:7\> // way
1721 payload\<19:13\> = L2C_TAD()_TQD_ERR[L2DIDX]\<6:0\> // index\<12:6\>
1722 payload\<12:11\> = L2C_TAD()_TQD_ERR[L2DIDX]\<12:11\> // index\<5:4\>
1723 payload\<10\> = L2C_TAD()_TQD_ERR[QDNUM]\<2\> // index\<3\>
1724 payload\<9:7\> = tad // index\<2:0\>
1725 \</pre\>
1726
1727 where tad is the TAD index from this CSR. Note that L2C_CTL[DISIDXALIAS] has no
1728 effect on the payload. */
1729 #else /* Word 0 - Little Endian */
1730 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1C/H) L2D single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1731 information. When [L2DSBE] is set, hardware corrected the error before using the
1732 data, but did not correct any stored value. When [L2DSBE] is set, software
1733 should eject the cache block indicated by the corresponding
1734 L2C_TAD()_TQD_ERR[QDNUM,L2DIDX] (via a SYS CVMCACHEWBIL2I instruction below)
1735 before clearing [L2DSBE]. Otherwise, hardware may encounter the error again the
1736 next time the same L2D location is referenced. Software may also choose to count
1737 the number of these single-bit errors.
1738
1739 The SYS CVMCACHEWBIL2I instruction payload should have:
1740 \<pre\>
1741 payload\<24\> = 0
1742 payload\<23:20\> = L2C_TAD()_TQD_ERR[L2DIDX]\<10:7\> // way
1743 payload\<19:13\> = L2C_TAD()_TQD_ERR[L2DIDX]\<6:0\> // index\<12:6\>
1744 payload\<12:11\> = L2C_TAD()_TQD_ERR[L2DIDX]\<12:11\> // index\<5:4\>
1745 payload\<10\> = L2C_TAD()_TQD_ERR[QDNUM]\<2\> // index\<3\>
1746 payload\<9:7\> = tad // index\<2:0\>
1747 \</pre\>
1748
1749 where tad is the TAD index from this CSR. Note that L2C_CTL[DISIDXALIAS] has no
1750 effect on the payload. */
1751 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1C/H) L2D double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1752 indication of a hardware failure and may be considered fatal. */
1753 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1C/H) SBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1754 information. Hardware automatically corrected the error. Software may choose to
1755 count the number of these single-bit errors. */
1756 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1C/H) SBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1757 indication of a hardware failure and may be considered fatal. */
1758 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1C/H) FBF single-bit error on a read. See L2C_TAD()_TQD_ERR for logged
1759 information. Hardware automatically corrected the error. Software may choose to
1760 count the number of these single-bit errors. */
1761 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1C/H) FBF double-bit error occurred. See L2C_TAD()_TQD_ERR for logged information. An
1762 indication of a hardware failure and may be considered fatal. */
1763 uint64_t reserved_6_7 : 2;
1764 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1C/H) TAG single-bit error on a read. See L2C_TAD()_TTG_ERR for logged
1765 information. When [TAGSBE] is set, hardware corrected the error before using the
1766 tag, but did not correct any stored value. When [TAGSBE] is set, software should
1767 eject the TAG location indicated by the corresponding
1768 L2C_TAD()_TTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
1769 before clearing [TAGSBE]. Otherwise, hardware may encounter the error again the
1770 next time the same TAG location is referenced. Software may also choose to count
1771 the number of these single-bit errors.
1772
1773 The SYS CVMCACHEWBIL2I instruction payload should have:
1774 \<pre\>
1775 payload\<24\> = 0
1776 payload\<23:20\> = L2C_TAD()_TTG_ERR[WAY]
1777 payload\<19:7\> = L2C_TAD()_TTG_ERR[L2IDX]
1778 \</pre\>
1779 Note that L2C_CTL[DISIDXALIAS] has no effect on this payload. */
1780 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1C/H) TAG double-bit error occurred. See L2C_TTG()_ERR for logged information.
1781 This is an indication of a hardware failure and may be considered fatal. */
1782 uint64_t noway : 1; /**< [ 10: 10](R/W1C/H) No way was available for allocation. L2C sets [NOWAY] during its processing of a
1783 transaction whenever it needed/wanted to allocate a WAY in the L2 cache, but was
1784 unable to. When this bit = 1, it is (generally) not an indication that L2C
1785 failed to complete transactions. Rather, it is a hint of possible performance
1786 degradation. (For example, L2C must read- modify-write DRAM for every
1787 transaction that updates some, but not all, of the bytes in a cache block,
1788 misses in the L2 cache, and cannot allocate a WAY.) There is one 'failure' case
1789 where L2C sets [NOWAY]: when it cannot leave a block locked in the L2 cache as
1790 part of a LCKL2 transaction. See L2C_TTG()_ERR for logged information. */
1791 uint64_t reserved_11_12 : 2;
1792 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1C/H) Write reference outside all the defined and enabled address space
1793 control (ASC) regions, or secure write reference to an ASC region
1794 not enabled for secure access, or nonsecure write reference to an
1795 ASC region not enabled for nonsecure access.
1796 This may be an indication of software
1797 failure, and may be considered fatal.
1798 See L2C_TAD()_ERR for logged information.
1799 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1800 L2C_ASC_REGION()_ATTR for ASC region specification. */
1801 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1C/H) Read reference outside all the defined and enabled address space
1802 control (ASC) regions, or secure read reference to an ASC region
1803 not enabled for secure access, or nonsecure read reference to an ASC
1804 region not enabled for nonsecure access.
1805 [RDNXM] interrupts can occur during normal operation as the cores are
1806 allowed to prefetch to nonexistent memory locations. Therefore,
1807 [RDNXM] is for informational purposes only.
1808 See L2C_TAD()_ERR for logged information.
1809 See L2C_ASC_REGION()_START, L2C_ASC_REGION()_END, and
1810 L2C_ASC_REGION()_ATTR for ASC region specification. */
1811 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1C/H) Illegal read to disabled LMC error. A DRAM read arrived before LMC was enabled.
1812 Should not occur during normal operation.
1813 This may be considered fatal. */
1814 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1C/H) Illegal write to disabled LMC error. A DRAM write arrived before LMC was enabled.
1815 Should not occur during normal operation.
1816 This may be considered fatal. */
1817 uint64_t lfbto : 1; /**< [ 17: 17](R/W1C/H) An LFB entry (or more) has encountered a timeout condition When [LFBTO] timeout
1818 condition occurs L2C_TAD()_TIMEOUT is loaded. L2C_TAD()_TIMEOUT is loaded with
1819 info from the first LFB that timed out. if multiple LFB timed out
1820 simultaneously, then the it will capture info from the lowest LFB number that
1821 timed out.
1822 Should not occur during normal operation. OCI/CCPI link failures may cause this
1823 failure. This may be an indication of hardware failure, and may be considered
1824 fatal. */
1825 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1C/H) Global sync OCI timeout. Should not occur during normal operation. OCI/CCPI link
1826 failures may cause this failure. This may be an indication of hardware failure,
1827 and may be considered fatal. */
1828 uint64_t reserved_19_31 : 13;
1829 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1C/H) RTG single-bit error on a read. See L2C_TAD()_RTG_ERR for logged
1830 information. When [RTGSBE] is set, hardware corrected the error before using the
1831 RTG tag, but did not correct any stored value. When [RTGSBE] is set, software
1832 should eject the RTG location indicated by the corresponding
1833 L2C_TAD()_RTG_ERR[WAY,L2IDX] (via a SYS CVMCACHEWBIL2I instruction below)
1834 before clearing [RTGSBE]. Otherwise, hardware may encounter the error again the
1835 next time the same RTG location is referenced. Software may also choose to count
1836 the number of these single-bit errors.
1837
1838 The SYS CVMCACHEWBIL2I instruction payload should have:
1839 \<pre\>
1840 payload\<24\> = 1
1841 payload\<23:20\> = L2C_TAD()_RTG_ERR[WAY]
1842 payload\<19:7\> = L2C_TAD()_RTG_ERR[L2IDX]
1843 \</pre\>
1844 Note that L2C_CTL[DISIDXALIAS] has no effect on the payload. */
1845 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1C/H) RTG double-bit error.
1846 See L2C_TAD()_RTG_ERR for logged information.
1847 An indication of a hardware failure and may be considered fatal. */
1848 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1C/H) Illegal read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
1849 clear. Note [RDDISOCI] interrupts can occur during normal operation as the cores
1850 are allowed to prefetch to nonexistent memory locations. Therefore, [RDDISOCI]
1851 is for informational purposes only. See L2C_TAD()_ERR for logged information. */
1852 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1C/H) Illegal write operation to a remote node with L2C_OCI_CTL[ENAOCI][node] clear. See
1853 L2C_TAD()_ERR for logged information.
1854 During normal hardware operation, an indication of a software failure and may be
1855 considered fatal. */
1856 uint64_t reserved_36_63 : 28;
1857 #endif /* Word 0 - End */
1858 } cn88xxp2;
1859 };
1860 typedef union bdk_l2c_tadx_int_w1c bdk_l2c_tadx_int_w1c_t;
1861
1862 static inline uint64_t BDK_L2C_TADX_INT_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_INT_W1C(unsigned long a)1863 static inline uint64_t BDK_L2C_TADX_INT_W1C(unsigned long a)
1864 {
1865 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
1866 return 0x87e050040000ll + 0x1000000ll * ((a) & 0x0);
1867 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
1868 return 0x87e050040000ll + 0x1000000ll * ((a) & 0x3);
1869 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=7))
1870 return 0x87e050040000ll + 0x1000000ll * ((a) & 0x7);
1871 __bdk_csr_fatal("L2C_TADX_INT_W1C", 1, a, 0, 0, 0);
1872 }
1873
1874 #define typedef_BDK_L2C_TADX_INT_W1C(a) bdk_l2c_tadx_int_w1c_t
1875 #define bustype_BDK_L2C_TADX_INT_W1C(a) BDK_CSR_TYPE_RSL
1876 #define basename_BDK_L2C_TADX_INT_W1C(a) "L2C_TADX_INT_W1C"
1877 #define device_bar_BDK_L2C_TADX_INT_W1C(a) 0x0 /* PF_BAR0 */
1878 #define busnum_BDK_L2C_TADX_INT_W1C(a) (a)
1879 #define arguments_BDK_L2C_TADX_INT_W1C(a) (a),-1,-1,-1
1880
1881 /**
1882 * Register (RSL) l2c_tad#_int_w1s
1883 *
1884 * L2C TAD Interrupt Set Registers
1885 * This register sets interrupt bits.
1886 */
1887 union bdk_l2c_tadx_int_w1s
1888 {
1889 uint64_t u;
1890 struct bdk_l2c_tadx_int_w1s_s
1891 {
1892 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1893 uint64_t reserved_36_63 : 28;
1894 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
1895 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
1896 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
1897 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
1898 uint64_t reserved_19_31 : 13;
1899 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
1900 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[LFBTO]. */
1901 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
1902 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
1903 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDNXM]. */
1904 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRNXM]. */
1905 uint64_t reserved_11_12 : 2;
1906 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[NOWAY]. */
1907 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
1908 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
1909 uint64_t reserved_6_7 : 2;
1910 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
1911 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
1912 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
1913 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
1914 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
1915 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
1916 #else /* Word 0 - Little Endian */
1917 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
1918 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
1919 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
1920 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
1921 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
1922 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
1923 uint64_t reserved_6_7 : 2;
1924 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
1925 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
1926 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[NOWAY]. */
1927 uint64_t reserved_11_12 : 2;
1928 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRNXM]. */
1929 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDNXM]. */
1930 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
1931 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
1932 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[LFBTO]. */
1933 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
1934 uint64_t reserved_19_31 : 13;
1935 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
1936 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
1937 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
1938 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
1939 uint64_t reserved_36_63 : 28;
1940 #endif /* Word 0 - End */
1941 } s;
1942 struct bdk_l2c_tadx_int_w1s_cn88xxp1
1943 {
1944 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1945 uint64_t reserved_36_63 : 28;
1946 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
1947 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
1948 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
1949 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
1950 uint64_t reserved_19_31 : 13;
1951 uint64_t reserved_18 : 1;
1952 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[LFBTO]. */
1953 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
1954 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
1955 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDNXM]. */
1956 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRNXM]. */
1957 uint64_t reserved_11_12 : 2;
1958 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[NOWAY]. */
1959 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
1960 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
1961 uint64_t reserved_6_7 : 2;
1962 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
1963 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
1964 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
1965 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
1966 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
1967 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
1968 #else /* Word 0 - Little Endian */
1969 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
1970 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
1971 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
1972 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
1973 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
1974 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
1975 uint64_t reserved_6_7 : 2;
1976 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
1977 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
1978 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[NOWAY]. */
1979 uint64_t reserved_11_12 : 2;
1980 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRNXM]. */
1981 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDNXM]. */
1982 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
1983 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
1984 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[LFBTO]. */
1985 uint64_t reserved_18 : 1;
1986 uint64_t reserved_19_31 : 13;
1987 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
1988 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
1989 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
1990 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
1991 uint64_t reserved_36_63 : 28;
1992 #endif /* Word 0 - End */
1993 } cn88xxp1;
1994 struct bdk_l2c_tadx_int_w1s_cn81xx
1995 {
1996 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1997 uint64_t reserved_36_63 : 28;
1998 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[WRDISOCI]. */
1999 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[RDDISOCI]. */
2000 uint64_t reserved_19_33 : 15;
2001 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[GSYNCTO]. */
2002 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[LFBTO]. */
2003 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[WRDISLMC]. */
2004 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[RDDISLMC]. */
2005 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[RDNXM]. */
2006 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[WRNXM]. */
2007 uint64_t reserved_11_12 : 2;
2008 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[NOWAY]. */
2009 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[TAGDBE]. */
2010 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[TAGSBE]. */
2011 uint64_t reserved_6_7 : 2;
2012 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[FBFDBE]. */
2013 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[FBFSBE]. */
2014 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[SBFDBE]. */
2015 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[SBFSBE]. */
2016 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[L2DDBE]. */
2017 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[L2DSBE]. */
2018 #else /* Word 0 - Little Endian */
2019 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[L2DSBE]. */
2020 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[L2DDBE]. */
2021 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[SBFSBE]. */
2022 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[SBFDBE]. */
2023 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[FBFSBE]. */
2024 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[FBFDBE]. */
2025 uint64_t reserved_6_7 : 2;
2026 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[TAGSBE]. */
2027 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[TAGDBE]. */
2028 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[NOWAY]. */
2029 uint64_t reserved_11_12 : 2;
2030 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[WRNXM]. */
2031 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[RDNXM]. */
2032 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[RDDISLMC]. */
2033 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[WRDISLMC]. */
2034 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[LFBTO]. */
2035 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[GSYNCTO]. */
2036 uint64_t reserved_19_33 : 15;
2037 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[RDDISOCI]. */
2038 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets L2C_TAD(0)_INT_W1C[WRDISOCI]. */
2039 uint64_t reserved_36_63 : 28;
2040 #endif /* Word 0 - End */
2041 } cn81xx;
2042 struct bdk_l2c_tadx_int_w1s_cn83xx
2043 {
2044 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2045 uint64_t reserved_36_63 : 28;
2046 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[WRDISOCI]. */
2047 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[RDDISOCI]. */
2048 uint64_t reserved_19_33 : 15;
2049 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
2050 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[LFBTO]. */
2051 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[WRDISLMC]. */
2052 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[RDDISLMC]. */
2053 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[RDNXM]. */
2054 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[WRNXM]. */
2055 uint64_t reserved_11_12 : 2;
2056 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[NOWAY]. */
2057 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[TAGDBE]. */
2058 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[TAGSBE]. */
2059 uint64_t reserved_6_7 : 2;
2060 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[FBFDBE]. */
2061 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[FBFSBE]. */
2062 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[SBFDBE]. */
2063 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[SBFSBE]. */
2064 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[L2DDBE]. */
2065 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[L2DSBE]. */
2066 #else /* Word 0 - Little Endian */
2067 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[L2DSBE]. */
2068 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[L2DDBE]. */
2069 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[SBFSBE]. */
2070 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[SBFDBE]. */
2071 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[FBFSBE]. */
2072 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[FBFDBE]. */
2073 uint64_t reserved_6_7 : 2;
2074 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[TAGSBE]. */
2075 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[TAGDBE]. */
2076 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[NOWAY]. */
2077 uint64_t reserved_11_12 : 2;
2078 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[WRNXM]. */
2079 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[RDNXM]. */
2080 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[RDDISLMC]. */
2081 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[WRDISLMC]. */
2082 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[LFBTO]. */
2083 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[GSYNCTO]. */
2084 uint64_t reserved_19_33 : 15;
2085 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[RDDISOCI]. */
2086 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets L2C_TAD(0..3)_INT_W1C[WRDISOCI]. */
2087 uint64_t reserved_36_63 : 28;
2088 #endif /* Word 0 - End */
2089 } cn83xx;
2090 struct bdk_l2c_tadx_int_w1s_cn88xxp2
2091 {
2092 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2093 uint64_t reserved_36_63 : 28;
2094 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
2095 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
2096 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
2097 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
2098 uint64_t reserved_19_31 : 13;
2099 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[GSYNCTO]. */
2100 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[LFBTO]. */
2101 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
2102 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
2103 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDNXM]. */
2104 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRNXM]. */
2105 uint64_t reserved_11_12 : 2;
2106 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[NOWAY]. */
2107 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
2108 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
2109 uint64_t reserved_6_7 : 2;
2110 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
2111 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
2112 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
2113 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
2114 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
2115 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
2116 #else /* Word 0 - Little Endian */
2117 uint64_t l2dsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DSBE]. */
2118 uint64_t l2ddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[L2DDBE]. */
2119 uint64_t sbfsbe : 1; /**< [ 2: 2](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFSBE]. */
2120 uint64_t sbfdbe : 1; /**< [ 3: 3](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[SBFDBE]. */
2121 uint64_t fbfsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFSBE]. */
2122 uint64_t fbfdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[FBFDBE]. */
2123 uint64_t reserved_6_7 : 2;
2124 uint64_t tagsbe : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGSBE]. */
2125 uint64_t tagdbe : 1; /**< [ 9: 9](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[TAGDBE]. */
2126 uint64_t noway : 1; /**< [ 10: 10](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[NOWAY]. */
2127 uint64_t reserved_11_12 : 2;
2128 uint64_t wrnxm : 1; /**< [ 13: 13](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRNXM]. */
2129 uint64_t rdnxm : 1; /**< [ 14: 14](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDNXM]. */
2130 uint64_t rddislmc : 1; /**< [ 15: 15](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISLMC]. */
2131 uint64_t wrdislmc : 1; /**< [ 16: 16](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISLMC]. */
2132 uint64_t lfbto : 1; /**< [ 17: 17](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[LFBTO]. */
2133 uint64_t gsyncto : 1; /**< [ 18: 18](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[GSYNCTO]. */
2134 uint64_t reserved_19_31 : 13;
2135 uint64_t rtgsbe : 1; /**< [ 32: 32](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGSBE]. */
2136 uint64_t rtgdbe : 1; /**< [ 33: 33](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RTGDBE]. */
2137 uint64_t rddisoci : 1; /**< [ 34: 34](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[RDDISOCI]. */
2138 uint64_t wrdisoci : 1; /**< [ 35: 35](R/W1S/H) Reads or sets L2C_TAD(0..7)_INT_W1C[WRDISOCI]. */
2139 uint64_t reserved_36_63 : 28;
2140 #endif /* Word 0 - End */
2141 } cn88xxp2;
2142 };
2143 typedef union bdk_l2c_tadx_int_w1s bdk_l2c_tadx_int_w1s_t;
2144
2145 static inline uint64_t BDK_L2C_TADX_INT_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_INT_W1S(unsigned long a)2146 static inline uint64_t BDK_L2C_TADX_INT_W1S(unsigned long a)
2147 {
2148 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
2149 return 0x87e050040008ll + 0x1000000ll * ((a) & 0x0);
2150 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
2151 return 0x87e050040008ll + 0x1000000ll * ((a) & 0x3);
2152 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=7))
2153 return 0x87e050040008ll + 0x1000000ll * ((a) & 0x7);
2154 __bdk_csr_fatal("L2C_TADX_INT_W1S", 1, a, 0, 0, 0);
2155 }
2156
2157 #define typedef_BDK_L2C_TADX_INT_W1S(a) bdk_l2c_tadx_int_w1s_t
2158 #define bustype_BDK_L2C_TADX_INT_W1S(a) BDK_CSR_TYPE_RSL
2159 #define basename_BDK_L2C_TADX_INT_W1S(a) "L2C_TADX_INT_W1S"
2160 #define device_bar_BDK_L2C_TADX_INT_W1S(a) 0x0 /* PF_BAR0 */
2161 #define busnum_BDK_L2C_TADX_INT_W1S(a) (a)
2162 #define arguments_BDK_L2C_TADX_INT_W1S(a) (a),-1,-1,-1
2163
2164 /**
2165 * Register (RSL) l2c_tad#_msix_pba#
2166 *
2167 * L2C TAD MSI-X Pending Bit Array Registers
2168 * This register is the MSI-X PBA table; the bit number is indexed by the L2C_TAD_INT_VEC_E
2169 * enumeration.
2170 */
2171 union bdk_l2c_tadx_msix_pbax
2172 {
2173 uint64_t u;
2174 struct bdk_l2c_tadx_msix_pbax_s
2175 {
2176 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2177 uint64_t pend : 64; /**< [ 63: 0](RO) Pending message for the associated L2C_TAD()_MSIX_VEC()_CTL, enumerated by
2178 L2C_TAD_INT_VEC_E. Bits
2179 that have no associated L2C_TAD_INT_VEC_E are 0. */
2180 #else /* Word 0 - Little Endian */
2181 uint64_t pend : 64; /**< [ 63: 0](RO) Pending message for the associated L2C_TAD()_MSIX_VEC()_CTL, enumerated by
2182 L2C_TAD_INT_VEC_E. Bits
2183 that have no associated L2C_TAD_INT_VEC_E are 0. */
2184 #endif /* Word 0 - End */
2185 } s;
2186 /* struct bdk_l2c_tadx_msix_pbax_s cn; */
2187 };
2188 typedef union bdk_l2c_tadx_msix_pbax bdk_l2c_tadx_msix_pbax_t;
2189
2190 static inline uint64_t BDK_L2C_TADX_MSIX_PBAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_MSIX_PBAX(unsigned long a,unsigned long b)2191 static inline uint64_t BDK_L2C_TADX_MSIX_PBAX(unsigned long a, unsigned long b)
2192 {
2193 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
2194 return 0x87e050ff0000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0x0);
2195 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b==0)))
2196 return 0x87e050ff0000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x0);
2197 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=7) && (b==0)))
2198 return 0x87e050ff0000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x0);
2199 __bdk_csr_fatal("L2C_TADX_MSIX_PBAX", 2, a, b, 0, 0);
2200 }
2201
2202 #define typedef_BDK_L2C_TADX_MSIX_PBAX(a,b) bdk_l2c_tadx_msix_pbax_t
2203 #define bustype_BDK_L2C_TADX_MSIX_PBAX(a,b) BDK_CSR_TYPE_RSL
2204 #define basename_BDK_L2C_TADX_MSIX_PBAX(a,b) "L2C_TADX_MSIX_PBAX"
2205 #define device_bar_BDK_L2C_TADX_MSIX_PBAX(a,b) 0x4 /* PF_BAR4 */
2206 #define busnum_BDK_L2C_TADX_MSIX_PBAX(a,b) (a)
2207 #define arguments_BDK_L2C_TADX_MSIX_PBAX(a,b) (a),(b),-1,-1
2208
2209 /**
2210 * Register (RSL) l2c_tad#_msix_vec#_addr
2211 *
2212 * L2C TAD MSI-X Vector-Table Address Register
2213 * This register is the MSI-X vector table, indexed by the L2C_TAD_INT_VEC_E enumeration.
2214 */
2215 union bdk_l2c_tadx_msix_vecx_addr
2216 {
2217 uint64_t u;
2218 struct bdk_l2c_tadx_msix_vecx_addr_s
2219 {
2220 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2221 uint64_t reserved_49_63 : 15;
2222 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
2223 uint64_t reserved_1 : 1;
2224 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
2225 0 = This vector may be read or written by either secure or nonsecure states.
2226 1 = This vector's L2C_TAD()_MSIX_VEC()_ADDR, L2C_TAD()_MSIX_VEC()_CTL, and corresponding
2227 bit of L2C_TAD()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
2228 by the nonsecure world.
2229
2230 If PCCPF_L2C_TAD_VSEC_SCTL[MSIX_SEC] (for documentation, see
2231 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
2232 set, all vectors are secure and function as if [SECVEC] was set. */
2233 #else /* Word 0 - Little Endian */
2234 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
2235 0 = This vector may be read or written by either secure or nonsecure states.
2236 1 = This vector's L2C_TAD()_MSIX_VEC()_ADDR, L2C_TAD()_MSIX_VEC()_CTL, and corresponding
2237 bit of L2C_TAD()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
2238 by the nonsecure world.
2239
2240 If PCCPF_L2C_TAD_VSEC_SCTL[MSIX_SEC] (for documentation, see
2241 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
2242 set, all vectors are secure and function as if [SECVEC] was set. */
2243 uint64_t reserved_1 : 1;
2244 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
2245 uint64_t reserved_49_63 : 15;
2246 #endif /* Word 0 - End */
2247 } s;
2248 /* struct bdk_l2c_tadx_msix_vecx_addr_s cn; */
2249 };
2250 typedef union bdk_l2c_tadx_msix_vecx_addr bdk_l2c_tadx_msix_vecx_addr_t;
2251
2252 static inline uint64_t BDK_L2C_TADX_MSIX_VECX_ADDR(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_MSIX_VECX_ADDR(unsigned long a,unsigned long b)2253 static inline uint64_t BDK_L2C_TADX_MSIX_VECX_ADDR(unsigned long a, unsigned long b)
2254 {
2255 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
2256 return 0x87e050f00000ll + 0x1000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x0);
2257 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b==0)))
2258 return 0x87e050f00000ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x0);
2259 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=7) && (b==0)))
2260 return 0x87e050f00000ll + 0x1000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x0);
2261 __bdk_csr_fatal("L2C_TADX_MSIX_VECX_ADDR", 2, a, b, 0, 0);
2262 }
2263
2264 #define typedef_BDK_L2C_TADX_MSIX_VECX_ADDR(a,b) bdk_l2c_tadx_msix_vecx_addr_t
2265 #define bustype_BDK_L2C_TADX_MSIX_VECX_ADDR(a,b) BDK_CSR_TYPE_RSL
2266 #define basename_BDK_L2C_TADX_MSIX_VECX_ADDR(a,b) "L2C_TADX_MSIX_VECX_ADDR"
2267 #define device_bar_BDK_L2C_TADX_MSIX_VECX_ADDR(a,b) 0x4 /* PF_BAR4 */
2268 #define busnum_BDK_L2C_TADX_MSIX_VECX_ADDR(a,b) (a)
2269 #define arguments_BDK_L2C_TADX_MSIX_VECX_ADDR(a,b) (a),(b),-1,-1
2270
2271 /**
2272 * Register (RSL) l2c_tad#_msix_vec#_ctl
2273 *
2274 * L2C TAD MSI-X Vector-Table Control and Data Register
2275 * This register is the MSI-X vector table, indexed by the L2C_TAD_INT_VEC_E enumeration.
2276 */
2277 union bdk_l2c_tadx_msix_vecx_ctl
2278 {
2279 uint64_t u;
2280 struct bdk_l2c_tadx_msix_vecx_ctl_s
2281 {
2282 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2283 uint64_t reserved_33_63 : 31;
2284 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
2285 uint64_t reserved_20_31 : 12;
2286 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
2287 #else /* Word 0 - Little Endian */
2288 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
2289 uint64_t reserved_20_31 : 12;
2290 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
2291 uint64_t reserved_33_63 : 31;
2292 #endif /* Word 0 - End */
2293 } s;
2294 /* struct bdk_l2c_tadx_msix_vecx_ctl_s cn; */
2295 };
2296 typedef union bdk_l2c_tadx_msix_vecx_ctl bdk_l2c_tadx_msix_vecx_ctl_t;
2297
2298 static inline uint64_t BDK_L2C_TADX_MSIX_VECX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_MSIX_VECX_CTL(unsigned long a,unsigned long b)2299 static inline uint64_t BDK_L2C_TADX_MSIX_VECX_CTL(unsigned long a, unsigned long b)
2300 {
2301 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
2302 return 0x87e050f00008ll + 0x1000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x0);
2303 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=3) && (b==0)))
2304 return 0x87e050f00008ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x0);
2305 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=7) && (b==0)))
2306 return 0x87e050f00008ll + 0x1000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x0);
2307 __bdk_csr_fatal("L2C_TADX_MSIX_VECX_CTL", 2, a, b, 0, 0);
2308 }
2309
2310 #define typedef_BDK_L2C_TADX_MSIX_VECX_CTL(a,b) bdk_l2c_tadx_msix_vecx_ctl_t
2311 #define bustype_BDK_L2C_TADX_MSIX_VECX_CTL(a,b) BDK_CSR_TYPE_RSL
2312 #define basename_BDK_L2C_TADX_MSIX_VECX_CTL(a,b) "L2C_TADX_MSIX_VECX_CTL"
2313 #define device_bar_BDK_L2C_TADX_MSIX_VECX_CTL(a,b) 0x4 /* PF_BAR4 */
2314 #define busnum_BDK_L2C_TADX_MSIX_VECX_CTL(a,b) (a)
2315 #define arguments_BDK_L2C_TADX_MSIX_VECX_CTL(a,b) (a),(b),-1,-1
2316
2317 /**
2318 * Register (RSL) l2c_tad#_rtg_err
2319 *
2320 * Level 2 Cache TAD RTG Error Information Registers
2321 * This register records error information for all RTG SBE/DBE errors.
2322 * The priority of errors (lowest to highest) is SBE, DBE. An error locks [SYN], [WAY],
2323 * and [L2IDX] for equal or lower priority errors until cleared by software.
2324 * The syndrome is recorded for DBE errors, though the utility of the value is not clear.
2325 * [L2IDX]\<19:7\> is the L2 block index associated with the command which had no way to allocate.
2326 */
2327 union bdk_l2c_tadx_rtg_err
2328 {
2329 uint64_t u;
2330 struct bdk_l2c_tadx_rtg_err_s
2331 {
2332 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2333 uint64_t rtgdbe : 1; /**< [ 63: 63](RO/H) Information refers to a double-bit RTG ECC error. */
2334 uint64_t rtgsbe : 1; /**< [ 62: 62](RO/H) Information refers to a single-bit RTG ECC error. */
2335 uint64_t reserved_39_61 : 23;
2336 uint64_t syn : 7; /**< [ 38: 32](RO/H) Syndrome for the single-bit error. */
2337 uint64_t reserved_24_31 : 8;
2338 uint64_t way : 4; /**< [ 23: 20](RO/H) Way of the L2 block containing the error. */
2339 uint64_t l2idx : 13; /**< [ 19: 7](RO/H) Index of the L2 block containing the error.
2340 See L2C_TAD()_INT_W1C[RTGSBE] for an important use of this field. */
2341 uint64_t reserved_0_6 : 7;
2342 #else /* Word 0 - Little Endian */
2343 uint64_t reserved_0_6 : 7;
2344 uint64_t l2idx : 13; /**< [ 19: 7](RO/H) Index of the L2 block containing the error.
2345 See L2C_TAD()_INT_W1C[RTGSBE] for an important use of this field. */
2346 uint64_t way : 4; /**< [ 23: 20](RO/H) Way of the L2 block containing the error. */
2347 uint64_t reserved_24_31 : 8;
2348 uint64_t syn : 7; /**< [ 38: 32](RO/H) Syndrome for the single-bit error. */
2349 uint64_t reserved_39_61 : 23;
2350 uint64_t rtgsbe : 1; /**< [ 62: 62](RO/H) Information refers to a single-bit RTG ECC error. */
2351 uint64_t rtgdbe : 1; /**< [ 63: 63](RO/H) Information refers to a double-bit RTG ECC error. */
2352 #endif /* Word 0 - End */
2353 } s;
2354 /* struct bdk_l2c_tadx_rtg_err_s cn; */
2355 };
2356 typedef union bdk_l2c_tadx_rtg_err bdk_l2c_tadx_rtg_err_t;
2357
2358 static inline uint64_t BDK_L2C_TADX_RTG_ERR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_RTG_ERR(unsigned long a)2359 static inline uint64_t BDK_L2C_TADX_RTG_ERR(unsigned long a)
2360 {
2361 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && (a<=7))
2362 return 0x87e050060300ll + 0x1000000ll * ((a) & 0x7);
2363 __bdk_csr_fatal("L2C_TADX_RTG_ERR", 1, a, 0, 0, 0);
2364 }
2365
2366 #define typedef_BDK_L2C_TADX_RTG_ERR(a) bdk_l2c_tadx_rtg_err_t
2367 #define bustype_BDK_L2C_TADX_RTG_ERR(a) BDK_CSR_TYPE_RSL
2368 #define basename_BDK_L2C_TADX_RTG_ERR(a) "L2C_TADX_RTG_ERR"
2369 #define device_bar_BDK_L2C_TADX_RTG_ERR(a) 0x0 /* PF_BAR0 */
2370 #define busnum_BDK_L2C_TADX_RTG_ERR(a) (a)
2371 #define arguments_BDK_L2C_TADX_RTG_ERR(a) (a),-1,-1,-1
2372
2373 /**
2374 * Register (RSL) l2c_tad#_tbf_bist_status
2375 *
2376 * L2C TAD Quad Buffer BIST Status Registers
2377 */
2378 union bdk_l2c_tadx_tbf_bist_status
2379 {
2380 uint64_t u;
2381 struct bdk_l2c_tadx_tbf_bist_status_s
2382 {
2383 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2384 uint64_t vbffl : 16; /**< [ 63: 48](RO/H) BIST failure status for VBF ({QD7H1,QD7H0, ... , QD0H1, QD0H0}). */
2385 uint64_t sbffl : 16; /**< [ 47: 32](RO/H) BIST failure status for SBF ({QD7H1,QD7H0, ... , QD0H1, QD0H0}). */
2386 uint64_t fbfrspfl : 16; /**< [ 31: 16](RO/H) BIST failure status for FBF RSP port ({QD7H1,QD7H0, ... , QD0H1, QD0H0}). */
2387 uint64_t fbfwrpfl : 16; /**< [ 15: 0](RO/H) BIST failure status for FBF WRP port ({QD7H1,QD7H0, ... , QD0H1, QD0H0}). */
2388 #else /* Word 0 - Little Endian */
2389 uint64_t fbfwrpfl : 16; /**< [ 15: 0](RO/H) BIST failure status for FBF WRP port ({QD7H1,QD7H0, ... , QD0H1, QD0H0}). */
2390 uint64_t fbfrspfl : 16; /**< [ 31: 16](RO/H) BIST failure status for FBF RSP port ({QD7H1,QD7H0, ... , QD0H1, QD0H0}). */
2391 uint64_t sbffl : 16; /**< [ 47: 32](RO/H) BIST failure status for SBF ({QD7H1,QD7H0, ... , QD0H1, QD0H0}). */
2392 uint64_t vbffl : 16; /**< [ 63: 48](RO/H) BIST failure status for VBF ({QD7H1,QD7H0, ... , QD0H1, QD0H0}). */
2393 #endif /* Word 0 - End */
2394 } s;
2395 /* struct bdk_l2c_tadx_tbf_bist_status_s cn; */
2396 };
2397 typedef union bdk_l2c_tadx_tbf_bist_status bdk_l2c_tadx_tbf_bist_status_t;
2398
2399 static inline uint64_t BDK_L2C_TADX_TBF_BIST_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_TBF_BIST_STATUS(unsigned long a)2400 static inline uint64_t BDK_L2C_TADX_TBF_BIST_STATUS(unsigned long a)
2401 {
2402 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
2403 return 0x87e050070000ll + 0x1000000ll * ((a) & 0x0);
2404 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
2405 return 0x87e050070000ll + 0x1000000ll * ((a) & 0x3);
2406 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=7))
2407 return 0x87e050070000ll + 0x1000000ll * ((a) & 0x7);
2408 __bdk_csr_fatal("L2C_TADX_TBF_BIST_STATUS", 1, a, 0, 0, 0);
2409 }
2410
2411 #define typedef_BDK_L2C_TADX_TBF_BIST_STATUS(a) bdk_l2c_tadx_tbf_bist_status_t
2412 #define bustype_BDK_L2C_TADX_TBF_BIST_STATUS(a) BDK_CSR_TYPE_RSL
2413 #define basename_BDK_L2C_TADX_TBF_BIST_STATUS(a) "L2C_TADX_TBF_BIST_STATUS"
2414 #define device_bar_BDK_L2C_TADX_TBF_BIST_STATUS(a) 0x0 /* PF_BAR0 */
2415 #define busnum_BDK_L2C_TADX_TBF_BIST_STATUS(a) (a)
2416 #define arguments_BDK_L2C_TADX_TBF_BIST_STATUS(a) (a),-1,-1,-1
2417
2418 /**
2419 * Register (RSL) l2c_tad#_tdt_bist_status
2420 *
2421 * L2C TAD Data BIST Status Registers
2422 */
2423 union bdk_l2c_tadx_tdt_bist_status
2424 {
2425 uint64_t u;
2426 struct bdk_l2c_tadx_tdt_bist_status_s
2427 {
2428 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2429 uint64_t reserved_16_63 : 48;
2430 uint64_t l2dfl : 16; /**< [ 15: 0](RO/H) BIST failure status for L2D ({QD7H1,QD7H0, ... , QD0H1, QD0H0}). */
2431 #else /* Word 0 - Little Endian */
2432 uint64_t l2dfl : 16; /**< [ 15: 0](RO/H) BIST failure status for L2D ({QD7H1,QD7H0, ... , QD0H1, QD0H0}). */
2433 uint64_t reserved_16_63 : 48;
2434 #endif /* Word 0 - End */
2435 } s;
2436 /* struct bdk_l2c_tadx_tdt_bist_status_s cn; */
2437 };
2438 typedef union bdk_l2c_tadx_tdt_bist_status bdk_l2c_tadx_tdt_bist_status_t;
2439
2440 static inline uint64_t BDK_L2C_TADX_TDT_BIST_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_TDT_BIST_STATUS(unsigned long a)2441 static inline uint64_t BDK_L2C_TADX_TDT_BIST_STATUS(unsigned long a)
2442 {
2443 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
2444 return 0x87e050070100ll + 0x1000000ll * ((a) & 0x0);
2445 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
2446 return 0x87e050070100ll + 0x1000000ll * ((a) & 0x3);
2447 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=7))
2448 return 0x87e050070100ll + 0x1000000ll * ((a) & 0x7);
2449 __bdk_csr_fatal("L2C_TADX_TDT_BIST_STATUS", 1, a, 0, 0, 0);
2450 }
2451
2452 #define typedef_BDK_L2C_TADX_TDT_BIST_STATUS(a) bdk_l2c_tadx_tdt_bist_status_t
2453 #define bustype_BDK_L2C_TADX_TDT_BIST_STATUS(a) BDK_CSR_TYPE_RSL
2454 #define basename_BDK_L2C_TADX_TDT_BIST_STATUS(a) "L2C_TADX_TDT_BIST_STATUS"
2455 #define device_bar_BDK_L2C_TADX_TDT_BIST_STATUS(a) 0x0 /* PF_BAR0 */
2456 #define busnum_BDK_L2C_TADX_TDT_BIST_STATUS(a) (a)
2457 #define arguments_BDK_L2C_TADX_TDT_BIST_STATUS(a) (a),-1,-1,-1
2458
2459 /**
2460 * Register (RSL) l2c_tad#_tqd_err
2461 *
2462 * L2C TAD Quad Error Information Registers
2463 * This register records error information for all L2D/SBF/FBF errors.
2464 * An error locks the [L2DIDX] and [SYN] fields and sets the bit corresponding to the error
2465 * received.
2466 * DBE errors take priority and overwrite an earlier logged SBE error. Only one of SBE/DBE is set
2467 * at any given time and serves to document which error the [L2DIDX]/[SYN] is associated with.
2468 * The syndrome is recorded for DBE errors, though the utility of the value is not clear.
2469 */
2470 union bdk_l2c_tadx_tqd_err
2471 {
2472 uint64_t u;
2473 struct bdk_l2c_tadx_tqd_err_s
2474 {
2475 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2476 uint64_t l2ddbe : 1; /**< [ 63: 63](RO/H) L2DIDX/SYN corresponds to a double-bit L2D ECC error. */
2477 uint64_t sbfdbe : 1; /**< [ 62: 62](RO/H) L2DIDX/SYN corresponds to a double-bit SBF ECC error. */
2478 uint64_t fbfdbe : 1; /**< [ 61: 61](RO/H) L2DIDX/SYN corresponds to a double-bit FBF ECC error. */
2479 uint64_t l2dsbe : 1; /**< [ 60: 60](RO/H) L2DIDX/SYN corresponds to a single-bit L2D ECC error. */
2480 uint64_t sbfsbe : 1; /**< [ 59: 59](RO/H) L2DIDX/SYN corresponds to a single-bit SBF ECC error. */
2481 uint64_t fbfsbe : 1; /**< [ 58: 58](RO/H) L2DIDX/SYN corresponds to a single-bit FBF ECC error. */
2482 uint64_t reserved_40_57 : 18;
2483 uint64_t syn : 8; /**< [ 39: 32](RO/H) Error syndrome. */
2484 uint64_t reserved_18_31 : 14;
2485 uint64_t qdnum : 3; /**< [ 17: 15](RO/H) Quad containing the error. */
2486 uint64_t qdhlf : 1; /**< [ 14: 14](RO/H) Quad half of the containing the error. */
2487 uint64_t l2didx : 14; /**< [ 13: 0](RO/H) For L2D errors, index within the quad-half containing the error. For SBF and FBF errors
2488 \<13:5\> is 0x0 and \<4:0\> is the index of the error (\<4:1\> is lfbnum\<3:0\>, \<0\> is addr\<5\>).
2489 See L2C_TAD()_INT_W1C[L2DSBE] for an important use of this field. */
2490 #else /* Word 0 - Little Endian */
2491 uint64_t l2didx : 14; /**< [ 13: 0](RO/H) For L2D errors, index within the quad-half containing the error. For SBF and FBF errors
2492 \<13:5\> is 0x0 and \<4:0\> is the index of the error (\<4:1\> is lfbnum\<3:0\>, \<0\> is addr\<5\>).
2493 See L2C_TAD()_INT_W1C[L2DSBE] for an important use of this field. */
2494 uint64_t qdhlf : 1; /**< [ 14: 14](RO/H) Quad half of the containing the error. */
2495 uint64_t qdnum : 3; /**< [ 17: 15](RO/H) Quad containing the error. */
2496 uint64_t reserved_18_31 : 14;
2497 uint64_t syn : 8; /**< [ 39: 32](RO/H) Error syndrome. */
2498 uint64_t reserved_40_57 : 18;
2499 uint64_t fbfsbe : 1; /**< [ 58: 58](RO/H) L2DIDX/SYN corresponds to a single-bit FBF ECC error. */
2500 uint64_t sbfsbe : 1; /**< [ 59: 59](RO/H) L2DIDX/SYN corresponds to a single-bit SBF ECC error. */
2501 uint64_t l2dsbe : 1; /**< [ 60: 60](RO/H) L2DIDX/SYN corresponds to a single-bit L2D ECC error. */
2502 uint64_t fbfdbe : 1; /**< [ 61: 61](RO/H) L2DIDX/SYN corresponds to a double-bit FBF ECC error. */
2503 uint64_t sbfdbe : 1; /**< [ 62: 62](RO/H) L2DIDX/SYN corresponds to a double-bit SBF ECC error. */
2504 uint64_t l2ddbe : 1; /**< [ 63: 63](RO/H) L2DIDX/SYN corresponds to a double-bit L2D ECC error. */
2505 #endif /* Word 0 - End */
2506 } s;
2507 /* struct bdk_l2c_tadx_tqd_err_s cn; */
2508 };
2509 typedef union bdk_l2c_tadx_tqd_err bdk_l2c_tadx_tqd_err_t;
2510
2511 static inline uint64_t BDK_L2C_TADX_TQD_ERR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_TQD_ERR(unsigned long a)2512 static inline uint64_t BDK_L2C_TADX_TQD_ERR(unsigned long a)
2513 {
2514 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
2515 return 0x87e050060100ll + 0x1000000ll * ((a) & 0x0);
2516 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
2517 return 0x87e050060100ll + 0x1000000ll * ((a) & 0x3);
2518 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=7))
2519 return 0x87e050060100ll + 0x1000000ll * ((a) & 0x7);
2520 __bdk_csr_fatal("L2C_TADX_TQD_ERR", 1, a, 0, 0, 0);
2521 }
2522
2523 #define typedef_BDK_L2C_TADX_TQD_ERR(a) bdk_l2c_tadx_tqd_err_t
2524 #define bustype_BDK_L2C_TADX_TQD_ERR(a) BDK_CSR_TYPE_RSL
2525 #define basename_BDK_L2C_TADX_TQD_ERR(a) "L2C_TADX_TQD_ERR"
2526 #define device_bar_BDK_L2C_TADX_TQD_ERR(a) 0x0 /* PF_BAR0 */
2527 #define busnum_BDK_L2C_TADX_TQD_ERR(a) (a)
2528 #define arguments_BDK_L2C_TADX_TQD_ERR(a) (a),-1,-1,-1
2529
2530 /**
2531 * Register (RSL) l2c_tad#_ttg_bist_status
2532 *
2533 * L2C TAD Tag BIST Status Registers
2534 */
2535 union bdk_l2c_tadx_ttg_bist_status
2536 {
2537 uint64_t u;
2538 struct bdk_l2c_tadx_ttg_bist_status_s
2539 {
2540 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2541 uint64_t reserved_50_63 : 14;
2542 uint64_t xmdmskfl : 2; /**< [ 49: 48](RO/H) BIST failure status for RSTP XMDMSK memories. */
2543 uint64_t rtgfl : 16; /**< [ 47: 32](RO/H) BIST failure status for RTG ways. */
2544 uint64_t reserved_18_31 : 14;
2545 uint64_t lrulfbfl : 1; /**< [ 17: 17](RO) Reserved, always zero. */
2546 uint64_t lrufl : 1; /**< [ 16: 16](RO/H) BIST failure status for tag LRU. */
2547 uint64_t tagfl : 16; /**< [ 15: 0](RO/H) BIST failure status for TAG ways. */
2548 #else /* Word 0 - Little Endian */
2549 uint64_t tagfl : 16; /**< [ 15: 0](RO/H) BIST failure status for TAG ways. */
2550 uint64_t lrufl : 1; /**< [ 16: 16](RO/H) BIST failure status for tag LRU. */
2551 uint64_t lrulfbfl : 1; /**< [ 17: 17](RO) Reserved, always zero. */
2552 uint64_t reserved_18_31 : 14;
2553 uint64_t rtgfl : 16; /**< [ 47: 32](RO/H) BIST failure status for RTG ways. */
2554 uint64_t xmdmskfl : 2; /**< [ 49: 48](RO/H) BIST failure status for RSTP XMDMSK memories. */
2555 uint64_t reserved_50_63 : 14;
2556 #endif /* Word 0 - End */
2557 } s;
2558 struct bdk_l2c_tadx_ttg_bist_status_cn81xx
2559 {
2560 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2561 uint64_t reserved_50_63 : 14;
2562 uint64_t xmdmskfl : 2; /**< [ 49: 48](RO/H) Reserved, always zero. */
2563 uint64_t reserved_18_47 : 30;
2564 uint64_t lrulfbfl : 1; /**< [ 17: 17](RO) Reserved, always zero. */
2565 uint64_t lrufl : 1; /**< [ 16: 16](RO/H) BIST failure status for tag LRU. */
2566 uint64_t tagfl : 16; /**< [ 15: 0](RO/H) BIST failure status for TAG ways. */
2567 #else /* Word 0 - Little Endian */
2568 uint64_t tagfl : 16; /**< [ 15: 0](RO/H) BIST failure status for TAG ways. */
2569 uint64_t lrufl : 1; /**< [ 16: 16](RO/H) BIST failure status for tag LRU. */
2570 uint64_t lrulfbfl : 1; /**< [ 17: 17](RO) Reserved, always zero. */
2571 uint64_t reserved_18_47 : 30;
2572 uint64_t xmdmskfl : 2; /**< [ 49: 48](RO/H) Reserved, always zero. */
2573 uint64_t reserved_50_63 : 14;
2574 #endif /* Word 0 - End */
2575 } cn81xx;
2576 /* struct bdk_l2c_tadx_ttg_bist_status_s cn88xx; */
2577 struct bdk_l2c_tadx_ttg_bist_status_cn83xx
2578 {
2579 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2580 uint64_t reserved_50_63 : 14;
2581 uint64_t xmdmskfl : 2; /**< [ 49: 48](RO/H) BIST failure status for RSTP XMDMSK memories. */
2582 uint64_t reserved_18_47 : 30;
2583 uint64_t lrulfbfl : 1; /**< [ 17: 17](RO) Reserved, always zero. */
2584 uint64_t lrufl : 1; /**< [ 16: 16](RO/H) BIST failure status for tag LRU. */
2585 uint64_t tagfl : 16; /**< [ 15: 0](RO/H) BIST failure status for TAG ways. */
2586 #else /* Word 0 - Little Endian */
2587 uint64_t tagfl : 16; /**< [ 15: 0](RO/H) BIST failure status for TAG ways. */
2588 uint64_t lrufl : 1; /**< [ 16: 16](RO/H) BIST failure status for tag LRU. */
2589 uint64_t lrulfbfl : 1; /**< [ 17: 17](RO) Reserved, always zero. */
2590 uint64_t reserved_18_47 : 30;
2591 uint64_t xmdmskfl : 2; /**< [ 49: 48](RO/H) BIST failure status for RSTP XMDMSK memories. */
2592 uint64_t reserved_50_63 : 14;
2593 #endif /* Word 0 - End */
2594 } cn83xx;
2595 };
2596 typedef union bdk_l2c_tadx_ttg_bist_status bdk_l2c_tadx_ttg_bist_status_t;
2597
2598 static inline uint64_t BDK_L2C_TADX_TTG_BIST_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_TTG_BIST_STATUS(unsigned long a)2599 static inline uint64_t BDK_L2C_TADX_TTG_BIST_STATUS(unsigned long a)
2600 {
2601 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
2602 return 0x87e050070200ll + 0x1000000ll * ((a) & 0x0);
2603 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
2604 return 0x87e050070200ll + 0x1000000ll * ((a) & 0x3);
2605 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=7))
2606 return 0x87e050070200ll + 0x1000000ll * ((a) & 0x7);
2607 __bdk_csr_fatal("L2C_TADX_TTG_BIST_STATUS", 1, a, 0, 0, 0);
2608 }
2609
2610 #define typedef_BDK_L2C_TADX_TTG_BIST_STATUS(a) bdk_l2c_tadx_ttg_bist_status_t
2611 #define bustype_BDK_L2C_TADX_TTG_BIST_STATUS(a) BDK_CSR_TYPE_RSL
2612 #define basename_BDK_L2C_TADX_TTG_BIST_STATUS(a) "L2C_TADX_TTG_BIST_STATUS"
2613 #define device_bar_BDK_L2C_TADX_TTG_BIST_STATUS(a) 0x0 /* PF_BAR0 */
2614 #define busnum_BDK_L2C_TADX_TTG_BIST_STATUS(a) (a)
2615 #define arguments_BDK_L2C_TADX_TTG_BIST_STATUS(a) (a),-1,-1,-1
2616
2617 /**
2618 * Register (RSL) l2c_tad#_ttg_err
2619 *
2620 * L2C TAD Tag Error Information Registers
2621 * This register records error information for all TAG SBE/DBE/NOWAY errors.
2622 * The priority of errors (lowest to highest) is NOWAY, SBE, DBE. An error locks [SYN], [WAY],
2623 * and [L2IDX] for equal or lower priority errors until cleared by software.
2624 * The syndrome is recorded for DBE errors, though the utility of the value is not clear.
2625 * A NOWAY error does not change the value of the [SYN] field, and leaves [WAY] unpredictable.
2626 * [L2IDX]\<19:7\> is the L2 block index associated with the command which had no way to allocate.
2627 */
2628 union bdk_l2c_tadx_ttg_err
2629 {
2630 uint64_t u;
2631 struct bdk_l2c_tadx_ttg_err_s
2632 {
2633 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2634 uint64_t tagdbe : 1; /**< [ 63: 63](RO/H) Information refers to a double-bit TAG ECC error. */
2635 uint64_t tagsbe : 1; /**< [ 62: 62](RO/H) Information refers to a single-bit TAG ECC error. */
2636 uint64_t noway : 1; /**< [ 61: 61](RO/H) Information refers to a NOWAY error. */
2637 uint64_t reserved_39_60 : 22;
2638 uint64_t syn : 7; /**< [ 38: 32](RO/H) Syndrome for the single-bit error. */
2639 uint64_t reserved_0_31 : 32;
2640 #else /* Word 0 - Little Endian */
2641 uint64_t reserved_0_31 : 32;
2642 uint64_t syn : 7; /**< [ 38: 32](RO/H) Syndrome for the single-bit error. */
2643 uint64_t reserved_39_60 : 22;
2644 uint64_t noway : 1; /**< [ 61: 61](RO/H) Information refers to a NOWAY error. */
2645 uint64_t tagsbe : 1; /**< [ 62: 62](RO/H) Information refers to a single-bit TAG ECC error. */
2646 uint64_t tagdbe : 1; /**< [ 63: 63](RO/H) Information refers to a double-bit TAG ECC error. */
2647 #endif /* Word 0 - End */
2648 } s;
2649 struct bdk_l2c_tadx_ttg_err_cn81xx
2650 {
2651 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2652 uint64_t tagdbe : 1; /**< [ 63: 63](RO/H) Information refers to a double-bit TAG ECC error. */
2653 uint64_t tagsbe : 1; /**< [ 62: 62](RO/H) Information refers to a single-bit TAG ECC error. */
2654 uint64_t noway : 1; /**< [ 61: 61](RO/H) Information refers to a NOWAY error. */
2655 uint64_t reserved_39_60 : 22;
2656 uint64_t syn : 7; /**< [ 38: 32](RO/H) Syndrome for the single-bit error. */
2657 uint64_t reserved_21_31 : 11;
2658 uint64_t way : 4; /**< [ 20: 17](RO/H) Way of the L2 block containing the error. */
2659 uint64_t l2idx : 10; /**< [ 16: 7](RO/H) Index of the L2 block containing the error.
2660 See L2C_TAD()_INT_W1C[TAGSBE] for an important use of this field. */
2661 uint64_t reserved_0_6 : 7;
2662 #else /* Word 0 - Little Endian */
2663 uint64_t reserved_0_6 : 7;
2664 uint64_t l2idx : 10; /**< [ 16: 7](RO/H) Index of the L2 block containing the error.
2665 See L2C_TAD()_INT_W1C[TAGSBE] for an important use of this field. */
2666 uint64_t way : 4; /**< [ 20: 17](RO/H) Way of the L2 block containing the error. */
2667 uint64_t reserved_21_31 : 11;
2668 uint64_t syn : 7; /**< [ 38: 32](RO/H) Syndrome for the single-bit error. */
2669 uint64_t reserved_39_60 : 22;
2670 uint64_t noway : 1; /**< [ 61: 61](RO/H) Information refers to a NOWAY error. */
2671 uint64_t tagsbe : 1; /**< [ 62: 62](RO/H) Information refers to a single-bit TAG ECC error. */
2672 uint64_t tagdbe : 1; /**< [ 63: 63](RO/H) Information refers to a double-bit TAG ECC error. */
2673 #endif /* Word 0 - End */
2674 } cn81xx;
2675 struct bdk_l2c_tadx_ttg_err_cn88xx
2676 {
2677 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2678 uint64_t tagdbe : 1; /**< [ 63: 63](RO/H) Information refers to a double-bit TAG ECC error. */
2679 uint64_t tagsbe : 1; /**< [ 62: 62](RO/H) Information refers to a single-bit TAG ECC error. */
2680 uint64_t noway : 1; /**< [ 61: 61](RO/H) Information refers to a NOWAY error. */
2681 uint64_t reserved_39_60 : 22;
2682 uint64_t syn : 7; /**< [ 38: 32](RO/H) Syndrome for the single-bit error. */
2683 uint64_t reserved_24_31 : 8;
2684 uint64_t way : 4; /**< [ 23: 20](RO/H) Way of the L2 block containing the error. */
2685 uint64_t l2idx : 13; /**< [ 19: 7](RO/H) Index of the L2 block containing the error.
2686 See L2C_TAD()_INT_W1C[TAGSBE] for an important use of this field. */
2687 uint64_t reserved_0_6 : 7;
2688 #else /* Word 0 - Little Endian */
2689 uint64_t reserved_0_6 : 7;
2690 uint64_t l2idx : 13; /**< [ 19: 7](RO/H) Index of the L2 block containing the error.
2691 See L2C_TAD()_INT_W1C[TAGSBE] for an important use of this field. */
2692 uint64_t way : 4; /**< [ 23: 20](RO/H) Way of the L2 block containing the error. */
2693 uint64_t reserved_24_31 : 8;
2694 uint64_t syn : 7; /**< [ 38: 32](RO/H) Syndrome for the single-bit error. */
2695 uint64_t reserved_39_60 : 22;
2696 uint64_t noway : 1; /**< [ 61: 61](RO/H) Information refers to a NOWAY error. */
2697 uint64_t tagsbe : 1; /**< [ 62: 62](RO/H) Information refers to a single-bit TAG ECC error. */
2698 uint64_t tagdbe : 1; /**< [ 63: 63](RO/H) Information refers to a double-bit TAG ECC error. */
2699 #endif /* Word 0 - End */
2700 } cn88xx;
2701 struct bdk_l2c_tadx_ttg_err_cn83xx
2702 {
2703 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2704 uint64_t tagdbe : 1; /**< [ 63: 63](RO/H) Information refers to a double-bit TAG ECC error. */
2705 uint64_t tagsbe : 1; /**< [ 62: 62](RO/H) Information refers to a single-bit TAG ECC error. */
2706 uint64_t noway : 1; /**< [ 61: 61](RO/H) Information refers to a NOWAY error. */
2707 uint64_t reserved_39_60 : 22;
2708 uint64_t syn : 7; /**< [ 38: 32](RO/H) Syndrome for the single-bit error. */
2709 uint64_t reserved_23_31 : 9;
2710 uint64_t way : 4; /**< [ 22: 19](RO/H) Way of the L2 block containing the error. */
2711 uint64_t l2idx : 12; /**< [ 18: 7](RO/H) Index of the L2 block containing the error.
2712 See L2C_TAD()_INT_W1C[TAGSBE] for an important use of this field. */
2713 uint64_t reserved_0_6 : 7;
2714 #else /* Word 0 - Little Endian */
2715 uint64_t reserved_0_6 : 7;
2716 uint64_t l2idx : 12; /**< [ 18: 7](RO/H) Index of the L2 block containing the error.
2717 See L2C_TAD()_INT_W1C[TAGSBE] for an important use of this field. */
2718 uint64_t way : 4; /**< [ 22: 19](RO/H) Way of the L2 block containing the error. */
2719 uint64_t reserved_23_31 : 9;
2720 uint64_t syn : 7; /**< [ 38: 32](RO/H) Syndrome for the single-bit error. */
2721 uint64_t reserved_39_60 : 22;
2722 uint64_t noway : 1; /**< [ 61: 61](RO/H) Information refers to a NOWAY error. */
2723 uint64_t tagsbe : 1; /**< [ 62: 62](RO/H) Information refers to a single-bit TAG ECC error. */
2724 uint64_t tagdbe : 1; /**< [ 63: 63](RO/H) Information refers to a double-bit TAG ECC error. */
2725 #endif /* Word 0 - End */
2726 } cn83xx;
2727 };
2728 typedef union bdk_l2c_tadx_ttg_err bdk_l2c_tadx_ttg_err_t;
2729
2730 static inline uint64_t BDK_L2C_TADX_TTG_ERR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_TADX_TTG_ERR(unsigned long a)2731 static inline uint64_t BDK_L2C_TADX_TTG_ERR(unsigned long a)
2732 {
2733 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
2734 return 0x87e050060200ll + 0x1000000ll * ((a) & 0x0);
2735 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
2736 return 0x87e050060200ll + 0x1000000ll * ((a) & 0x3);
2737 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=7))
2738 return 0x87e050060200ll + 0x1000000ll * ((a) & 0x7);
2739 __bdk_csr_fatal("L2C_TADX_TTG_ERR", 1, a, 0, 0, 0);
2740 }
2741
2742 #define typedef_BDK_L2C_TADX_TTG_ERR(a) bdk_l2c_tadx_ttg_err_t
2743 #define bustype_BDK_L2C_TADX_TTG_ERR(a) BDK_CSR_TYPE_RSL
2744 #define basename_BDK_L2C_TADX_TTG_ERR(a) "L2C_TADX_TTG_ERR"
2745 #define device_bar_BDK_L2C_TADX_TTG_ERR(a) 0x0 /* PF_BAR0 */
2746 #define busnum_BDK_L2C_TADX_TTG_ERR(a) (a)
2747 #define arguments_BDK_L2C_TADX_TTG_ERR(a) (a),-1,-1,-1
2748
2749 #endif /* __BDK_CSRS_L2C_TAD_H__ */
2750