1 #ifndef __CB_BDK_MODEL_H__
2 #define __CB_BDK_MODEL_H__
3
4 /***********************license start***********************************
5 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
6 * reserved.
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are
11 * met:
12 *
13 * * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * * Redistributions in binary form must reproduce the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer in the documentation and/or other materials provided
19 * with the distribution.
20 *
21 * * Neither the name of Cavium Inc. nor the names of
22 * its contributors may be used to endorse or promote products
23 * derived from this software without specific prior written
24 * permission.
25 *
26 * This Software, including technical data, may be subject to U.S. export
27 * control laws, including the U.S. Export Administration Act and its
28 * associated regulations, and may be subject to export or import
29 * regulations in other countries.
30 *
31 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
32 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
33 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT
34 * TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
35 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
36 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
37 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
38 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT,
39 * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK
40 * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
41 ***********************license end**************************************/
42
43 /**
44 * @file
45 *
46 * Functions for determining which Cavium chip you are running
47 * on.
48 *
49 * <hr>$Revision: 49448 $<hr>
50 * @addtogroup chips
51 * @{
52 */
53
54
55 /* Flag bits in top byte. The top byte of MIDR_EL1 is defined
56 as ox43, the Cavium implementer code. In this number, bits
57 7,5,4 are defiend as zero. We use these bits to signal
58 that revision numbers should be ignored. It isn't ideal
59 that these are in the middle of an already defined field,
60 but this keeps the model numbers as 32 bits */
61 #define __OM_IGNORE_REVISION 0x80000000
62 #define __OM_IGNORE_MINOR_REVISION 0x20000000
63 #define __OM_IGNORE_MODEL 0x10000000
64
65 #define CAVIUM_CN88XX_PASS1_0 0x430f0a10
66 #define CAVIUM_CN88XX_PASS1_1 0x430f0a11
67 #define CAVIUM_CN88XX_PASS2_0 0x431f0a10
68 #define CAVIUM_CN88XX_PASS2_1 0x431f0a11
69 #define CAVIUM_CN88XX_PASS2_2 0x431f0a12
70 #define CAVIUM_CN88XX (CAVIUM_CN88XX_PASS1_0 | __OM_IGNORE_REVISION)
71 #define CAVIUM_CN88XX_PASS1_X (CAVIUM_CN88XX_PASS1_0 | __OM_IGNORE_MINOR_REVISION)
72 #define CAVIUM_CN88XX_PASS2_X (CAVIUM_CN88XX_PASS2_0 | __OM_IGNORE_MINOR_REVISION)
73 /* Note CN86XX will also match the CN88XX macros above. See comment in
74 CAVIUM_IS_MODEL() about MIO_FUS_FUSE_NUM_E::CHIP_IDX bits 6-7 */
75
76 #define CAVIUM_CN83XX_PASS1_0 0x430f0a30
77 #define CAVIUM_CN83XX (CAVIUM_CN83XX_PASS1_0 | __OM_IGNORE_REVISION)
78 #define CAVIUM_CN83XX_PASS1_X (CAVIUM_CN83XX_PASS1_0 | __OM_IGNORE_MINOR_REVISION)
79
80 #define CAVIUM_CN81XX_PASS1_0 0x430f0a20
81 #define CAVIUM_CN81XX (CAVIUM_CN81XX_PASS1_0 | __OM_IGNORE_REVISION)
82 #define CAVIUM_CN81XX_PASS1_X (CAVIUM_CN81XX_PASS1_0 | __OM_IGNORE_MINOR_REVISION)
83 /* Note CN80XX will also match the CN81XX macros above. See comment in
84 CAVIUM_IS_MODEL() about MIO_FUS_FUSE_NUM_E::CHIP_IDX bits 6-7 */
85
86 #define CAVIUM_CN93XX_PASS1_0 0x430f0b20
87 #define CAVIUM_CN93XX (CAVIUM_CN93XX_PASS1_0 | __OM_IGNORE_REVISION)
88 #define CAVIUM_CN93XX_PASS1_X (CAVIUM_CN93XX_PASS1_0 | __OM_IGNORE_MINOR_REVISION)
89
90 /* These match entire families of chips */
91 #define CAVIUM_CN8XXX (CAVIUM_CN88XX_PASS1_0 | __OM_IGNORE_MODEL)
92 #define CAVIUM_CN9XXX (CAVIUM_CN93XX_PASS1_0 | __OM_IGNORE_MODEL)
93
94 static inline uint64_t cavium_get_model(void) __attribute__ ((pure, always_inline));
cavium_get_model(void)95 static inline uint64_t cavium_get_model(void)
96 {
97 #ifdef BDK_BUILD_HOST
98 extern uint32_t thunder_remote_get_model(void) __attribute__ ((pure));
99 return thunder_remote_get_model();
100 #else
101 uint64_t result;
102 asm ("mrs %[rd],MIDR_EL1" : [rd] "=r" (result));
103 return result;
104 #endif
105 }
106
107 /**
108 * Return non-zero if the chip matech the passed model.
109 *
110 * @param arg_model One of the CAVIUM_* constants for chip models and passes
111 *
112 * @return Non-zero if match
113 */
114 static inline int CAVIUM_IS_MODEL(uint32_t arg_model) __attribute__ ((pure, always_inline));
CAVIUM_IS_MODEL(uint32_t arg_model)115 static inline int CAVIUM_IS_MODEL(uint32_t arg_model)
116 {
117 const uint32_t FAMILY = 0xff00; /* Bits 15:8, generation t8x=0xa, t9x=0xb */
118 const uint32_t PARTNUM = 0xfff0; /* Bits 15:4, chip t88=0x81, t81=0xa2, t83=0xa3, etc */
119 const uint32_t VARIANT = 0xf00000; /* Bits 23:20, major pass */
120 const uint32_t REVISION = 0xf; /* Bits 3:0, minor pass */
121
122 /* Note that the model matching here is unaffected by
123 MIO_FUS_FUSE_NUM_E::CHIP_IDX bits 6-7, which are the alternate package
124 fuses. These bits don't affect MIDR_EL1, so:
125 CN80XX will match CN81XX (CHIP_IDX 6 is set for 676 ball package)
126 CN80XX will match CN81XX (CHIP_IDX 7 is set for 555 ball package)
127 CN86XX will match CN88XX (CHIP_IDX 6 is set for 676 ball package)
128 Alternate package parts are detected using MIO_FUS_DAT2[chip_id],
129 specifically the upper two bits */
130
131 uint32_t my_model = cavium_get_model();
132 uint32_t mask;
133
134 if (arg_model & __OM_IGNORE_MODEL)
135 mask = FAMILY; /* Matches chip generation (CN8XXX, CN9XXX) */
136 else if (arg_model & __OM_IGNORE_REVISION)
137 mask = PARTNUM; /* Matches chip model (CN88XX, CN81XX, CN83XX) */
138 else if (arg_model & __OM_IGNORE_MINOR_REVISION)
139 mask = PARTNUM | VARIANT; /* Matches chip model and major version */
140 else
141 mask = PARTNUM | VARIANT | REVISION; /* Matches chip model, major version, and minor version */
142 return ((arg_model & mask) == (my_model & mask));
143 }
144
145 /**
146 * Return non-zero if the die is in an alternate package. The
147 * normal is_model() checks will treat alternate package parts
148 * as all the same, where this function can be used to detect
149 * them. The return value is the upper two bits of
150 * MIO_FUS_DAT2[chip_id]. Most alternate packages use bit 6,
151 * which will return 1 here. Parts with a second alternative
152 * will use bit 7, which will return 2.
153 *
154 * @param arg_model One of the CAVIUM_* constants for chip models and passes
155 *
156 * @return Non-zero if an alternate package
157 * 0 = Normal package
158 * 1 = Alternate package 1 (CN86XX, CN80XX with 555 balls)
159 * 2 = Alternate package 2 (CN80XX with 676 balls)
160 * 3 = Alternate package 3 (Currently unused)
161 */
162 extern int cavium_is_altpkg(uint32_t arg_model);
163
164 /** @} */
165 #endif
166